Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses

Depósito de Investigación de la Universidad de Sevilla https://idus.us.es This is an Accepted Manuscript of an article published by Elsevier in Microelectronics Reliability, Vol.116, on January 2021, available at: https://doi.org/10.1016/j.future.2020.03.033 Copyright 2020 Elsevier. En idUS Licencia CC BY-NC-ND IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 1 Ionizing radiation damage in 65 nm CMOS technology: influence of geometry, bias and temperature at ultra-high doses Giulio Borghello, Edoardo Lerario, Federico Faccio, Henri D. Koch, Stefano Michelis, Fernando J. Marquez, Francisco R. Palomo and Fernando Mu˜ noz Abstract—We studied the radiation response of 3 different 65 nm CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. Similar dependencies on device geometry, applied polarization and ambient temperature have been found in all the processes studied, demonstrating that the radiation response of nanoscale CMOS technologies is regulated by the same mechanisms. The results obtained confirmed that the performance of MOS transistors exposed at ultra-high doses is mainly affected by radiation-induced charge trapped in auxiliary oxides such as shallow trench isolation oxides and spacers. The extensive data collected has been used to develop guidelines to properly qualify ASICs designed with the 65 nm technology node. Index Terms—65 nm CMOS technology, high luminosity-large hadron collider (HL-LHC), MOSFET reliability, spacers, shallow trench isolation (STI), total ionizing dose (TID), ultra-high doses I. INTRODUCTION WHILE the Large Hadron Collider (LHC) at CERN is already the most powerful particle accelerator in the world, an on-going upgrade program aims at increasing its luminosity in a decade from now. The upgraded machine is referred to as HL-LHC (High Luminosity) [1]. The higher luminosity directly translates into a considerably larger radiation environment for the detector systems, threatening the reliable functionality of the associated electronics components. In the innermost detector layers, closer to the place where accelerated particles collide, the Application Specific Integrated Circuits (ASICs) reading the signal from silicon detectors will be exposed to unprecedented radiation levels over their lifetime of 10 years: a Total Ionizing Dose (TID) of TID = 1 Grad(SiO2) and a fluence of 1016 n/cm2(integrated flux expressed in 1 MeV equivalent neutrons for displacement damage) [2]. G. Borghello, F. Faccio and S. Michelis are with the ME section of CERN-EP department, CH-1211 Geneva 23, Switzerland (e-mail: [email protected]; federico.f[email protected]; [email protected]) E. Lerario was with the ME section of CERN-EP department, CH- 1211 Geneva 23, Switzerland. He is now with the Department of Engineering for Innovation, University of Salento, Lecce, Italy (e-mail: [email protected]) H. D. Koch was with the ME section of CERN-EP department, CH- 1211 Geneva 23, Switzerland. He resides in Neuchˆ atel, 2008 CH (e-mail: [email protected]) F. Marquez, F. R. Palomo and F. Mu˜ noz are with the Department of Electronic Engineering, School of Engineering, University of Seville, 41092 Seville, Spain (e-mail: [email protected]; [email protected]; [email protected]) The present LHC detector systems, designed for radiation levels of the order of TID = 10 Mrad(SiO2), make use of ASICs designed and manufactured in commercial-grade (not radiation-hardened) 250 nm CMOS technologies. Radiation hardness is achieved by the combination of the natural TID tolerance of the 5 nm gate oxide coupled to the systematic use of HBD (Hardness-By-Design) techniques [3], [4]. For upgraded systems, it is clearly appealing to move to more advanced CMOS nodes in order to increase the integrated functionality and reduce the power consumption. At the same time, the thinner gate oxide accompanying the down-scaling of the transistors (at least until the 65 nm node) promises an even larger tolerance to TID effects. Before starting design work in these technologies, it is however necessary to characterize the radiation response of the individual MOSFETs to measure the degradation and understand its basic mechanisms. This knowledge only can enable designers to develop ASICs capable of surviving to the required levels of radiation, and detector groups to envisage the appropriate qualification techniques ensuring, with safety margins, that the production circuits will not compromise the optimum functionality of the detectors. In this paper, we explore the TID effects in candidate 65 nm technologies from three different manufactures (Man. A, B and C) for the ASIC development for HL-LHC detector systems. In particular, we study the impact of MOSFET geometry on their radiation tolerance and how the applied bias and temperature during or after irradiation influence their radiation response. II. EXPERIMENTAL DETAILS FOR this study we used custom-designed test structures containing nMOS and pMOS transistors of different sizes. Other than transistors arrays where either the gate width (W) or length (L) was varied, the structures also included Enclosed Layout Transistors (ELT) and groups of identical matched transistors allowing to better evaluate the influence of the applied bias on the radiation-induced damage. ELTs are designed with an inner diffusion entirely surrounded by the polysilicon gate that is itself surrounded by an outer diffusion [3], [4]. These devices are widely used in the design of ASICs for the detectors of the LHC as their concentric structure prevents any contact between the Shallow Trench Isolation (STI) oxide and the channel, eliminating the effects due to the presence of STI and improving the overall radiation hardness. This feature also makes them ideal for studying the Page 1 of 9 Transactions on Nuclear Science - Copy for Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 2 impact of radiation-induced charge trapped in other oxides, such as the gate oxide and the spacers. We used two different setups in our study, one dedicated to the irradiation and the other to the subsequent annealing (both taking place under bias). The two almost identical setups are composed by a wafer prober station with a probe card, a thermal chuck, a Switching Matrix and a Semiconductor Parameter Analyzer. With this equipment, it was possible to measure bare chips where terminals were contacted with needles to the measurement system. The irradiation setup also includes an X-ray generator with a tungsten anode target, similar to the system described in [5], calibrated with a dedicated PIN diode and radiochromic films, capable of delivering up to 10 Mrad(SiO2)/hto the Device Under Test (DUT). The thermal chuck in this setup can control the DUT temperature between −50 and 200 ◦C, the wafer prober being enclosed in a cabinet where an over-pressure of dry air is constantly maintained. A picture of the irradiation system can be found in [6]. The other setup, or annealing setup, is used for the postirradiation annealing and can only warm up the samples up to 100 ◦C. Both setups are controlled with an ad-hoc software custom developed in LabVIEW. Transistors were measured before irradiation, then after the accumulation of pre-determined TID levels, then periodically during post-irradiation annealing. Standard measurements included IDS =f(VGS )in both linear and saturation regimes, and IDS =f(VDS )at different inversion levels. To observe possible radiation-induced asymmetry in the characteristics, every measurement was repeated by swapping the role of the source and drain diffusions (henceforth we will refer to nominal configuration and reverse configuration). Measurement data were then processed with custom-developed MATLAB routines to extract all the main parameters of interest: Isat ON (drain current for |VGS |=|VDS |= 1.2 V), IOF F (drain current for |VGS |= 0 V and |VDS |= 1.2 V), the maximum transconductance in the linear regime (gmlin MAX ) and the threshold voltage (Vsat T H ) extracted with a linear fit on the pIDS (VGS )in saturation region. In order to study the effect of the applied bias on the radiation response, we used four different polarizations (positive sign for nMOS, negative for pMOS): •diode: VGS =VDS =±1.2 V •onlyVDS:VGS = 0 V, VDS =±1.2 V •onlyVGS:VGS =±1.2 V, VDS = 0 V •allGND: VGS =VDS = 0 V Where not explicitly specified otherwise, both during the irradiation and during annealing the devices were constantly biased in diode configuration, the bias that led to the major degradation in previous studies [7]. III. RESULTS AND DISCUSSION THIS section is divided in STI- and spacers-related effects. These two auxiliary oxides have been proved to be the major threat for the ionizing-radiation hardness of modern CMOS technologies [8], [7]. Figure 1a shows a schematic representation of a MOSFET whit STI and spacers oxides. STI POLY SPACER Si3N4 SiO2 GATE OXIDE D S xy z (a) STI STI LEAKAGE LDD LDD POLY n+ xy z SPACER Si3N4 SiO2 D S (b) POLY STI + ++ + + + + + + + + + + + + + ++ ++ ++ ++ ++ + + + xz y (c) SOURCE DRAIN n+ n+ p+ STI + +++ ++ +++++ + ++++++ + ++ +++ L W -z y x (d) Fig. 1. 1a) Schematic representation of an nMOS transistor. STI and spacer oxides are indicated. 1b) Cross section of the device along the xy plane at the beginning of the active area. Leakage current flows from drain to source in the ydirection. 1c) Cross section of Fig. 1b along the xz plane in the middle of the channel. Since the gate extends above the STI, the applied gate bias strongly influences the spatial distribution of the positive charge trapped in the trench oxide. 1d) Top view of the device where polysilicon gate, gate oxide and spacers have been removed. The channel length of parasitic transistors is the same as that of the main channel. On the other hand, Whas a negligible relation with the lateral transistors, since the minimum channel width of this technology (120 nm) is much higher than the parasitic inversion layers. A. STI-related effects Charge trapped in the STI and at its interface with the channel is known to provoke two different effects: an increase in the drain-to-source leakage current (IOF F ) [9], [10], [11] and, more evidently at high doses, an apparent threshold voltage (VT H ) shift together with a variation in the transconductance (gm). Since the main feature of the latter effect is its dependence on the channel width, with narrow devices showing a larger sensitivity to TID, Faccio and co-workers named this phenomenon Radiation-Induced Narrow Channel Effect (RINCE) [12]. In previous works, the radiation-induced variation in the IOF F and the phenomenology of RINCE have either not been studied in detail at ultra-high doses, or data only referred to samples from one single manufacturer [12], [13], [7]. It is instead interesting to extend the study to samples produced in very different manufacturing plants, from different suppliers, in order to understand whether the effects are linked to specific manufacturing details, or if they can be generally extended to a specific CMOS technology node. For this reason, we will present in this section the detailed results from samples in 65 nm CMOS technologies produced by three different manufacturers. 1) Leakage current: The radiation-induced IOF F (RIFF) is provoked by positive charge trapped in the STI [9], [10], [14], as schematically indicated in Figures 1b, 1c and 1d. In Page 2 of 9Transactions on Nuclear Science - Copy for Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 3 Fig. 2. Evolution of the IOF F as a function of TID for nMOS devices in 65 nm from Man. A. During exposure, transistors were biased with VGS = VDS = 1.2 V and kept at T= 25 ◦C. At high TID, the level of leakage is almost independent on the Wof the transistor ad increases for lower L. nMOS devices, this charge attracts electrons from the substrate in the silicon region adjacent to the STI. The accumulation of positive charge at increasing TID levels eventually leads to the inversion of the silicon at the side of the channel, effectively creating a conduction path for drain-source leakage currents. Since the current flowing through these parasitic paths is only slightly or not at all influenced by the gate voltage [15], [16], [11], a VDS >0 V induces a current even when VGS = 0 V. The lack of control in turning off nMOS transistors clearly causes an increase in dissipated power to levels that may compromise the correct functionality of an ASIC. Note that the positive charge trapped in STI repels holes, therefore RIFF is not of concern for p-channel MOS. Since the parasitic current flows from drain to source, the length of the lateral channels is comparable to the length of the main transistor. As a consequence, radiation-induced IOF F roughly follows a 1/L trend. While the channel length of parasitic transistors is easily determined, the identification of their channel width is not straightforward. It is related to the distribution of positive oxide-trapped charge along the wall of the STI, in a direction perpendicular to the gate (xdirection in Figure 1c). This distribution is certainly influenced by the voltage applied at the gate, which, if positive, tends to push holes far from the gate in a deeper region of the STI [17]. Moreover, since lowdoped substrates are more easily inverted, also the local doping profile of the substrate has an impact in the evolution of the leakage current [18]. All these factors determine the amount of leakage current induced by TID. In any case, the intensity of the parasitic current is only slightly dependent on the W of the main transistor. Figure 2 shows the IOF F (TID) for transistors in 65 nm technology from manufacturer A (Man. A), exposed to a TID of 1 Grad(SiO2). During irradiation, the temperature was 25 ◦C and the transistors were kept in diode configuration. The pre-irradiation level of leakage current in saturation region is Fig. 3. ID(VG)characteristic of 3different devices from Man. A, measured before irradiation (solid lines) and after 1 Grad(SiO2)(dashed lines). The dotted vertical line indicates the VG= 0 V point, where the IOF F is measured. dependent on the W/L ratio of the device and on the intensity of the drain-induced barrier lowering (DIBL) effect, which increases the current in the subthreshold region of short channel transistors. However, for TID >200 Mrad (SiO2), the IOF F is not dependent anymore on the Wof the main channel; it is comparable for devices with the same channel length and decreases with L. This proves that, at such ultra-high levels of TID, the current flowing in the parasitic transistors overcomes the drain-to-source current of the main channel, i.e. the prerad level of IOF F . It is clear that the impact of the radiationinduced leakage current starts to become evident at higher TID in devices with a higher initial IOF F , because more charge is needed to induce enough parasitic current to overcome the preirradiation level of IOF F flowing in the main transistor. An important practical consequence is that, for a given channel length, transistors with larger Whave a smaller difference between pre- and post-rad IOF F , as can be seen in Figure 2 comparing the radiation-response of the 0.12 µm×0.06 µm and the 1µm×0.06 µmnMOS devices. A similar behavior has also been measured in a 28 nm technology by Zhang and co-workers [19]. Figure 3 shows the ID(VG)currents measured in the saturation region (VDS = 1.2 V) before (solid lines) and after (dashed lines) exposure for three different devices, namely 0.12 µm×0.06 µm,1µm×0.06 µmand 1µm×1µm. The flat region at low VGS in the characteristics measured at 1 Grad(SiO2)is the clear manifestation of the current flowing in the parasitic transistors independently on the applied gate voltage. Note that devices with the same channel length have very similar post-rad IOF F levels despite their different behavior in the strong inversion region. Figure 4 reports the IOF F (TID) for 65 nm devices produced by manufacturer B (solid lines) and C (dashed lines). As for transistors from Man. A, also in this case the intensity of the radiation-induced leakage current is, at ultra-high doses, only dependent on the channel length. However, while the IOF F Page 3 of 9 Transactions on Nuclear Science - Copy for Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 4 Fig. 4. IOF F (TID) for nMOS devices from Man. B and Man. C for different W/L ratios. Man. B has a strong non-monotonic response, with a first peak around ∼5 Mrad(SiO2)and a second increase after ∼100 Mrad(SiO2). of devices from Man. A monotonically increases with TID, transistors from both Man. B and C show a peak of leakage around 10 Mrad(SiO2), followed by a decrease and a further increase at ultra-high doses. This behavior is more evident in Man. C, with a first increase of almost 4orders of magnitude for the minimum size device. While the first decrease can be related to the formation, in the STI, of negatively-charged interface traps that counterbalance the effect of the positive charge trapped in the oxide [12], the second increase is not easy to explain. It could be related to a saturation in the formation of interface traps or can be the manifestation of the opening of further parasitic paths. This and other effects related to radiation-induced leakage current will be studied in a future work. A not-monotonic trend has already been measured in [7] for MOSFETs in 130 nm technology, but in that case devices did not show any increase after the first peak. Figure 5 shows the ID(VG)characteristics in saturation region (VDS = 1.2 V) of the 1µm×0.06 µmtransistor from Man. C measured before irradiation, at 6 Mrad(SiO2), i.e. the first peak of the IOF F (TID), at the lowest level after the peak (TID = 100 Mrad(SiO2)) and at the end of the exposure. In all the post-rad measurements the increase in the IOF F is caused by the current flowing in parasitic paths, not controlled by the gate voltage. RIFF is known to be sensitive on the bias applied during irradiation. In particular, the gate voltage is believed to have an impact on the distribution of the oxide-trapped charge along the STI [17], [11]. However, RIFF in Man. A seems to be negligibly influenced by the voltage applied during exposure on the gate terminal. Figure 6 reports the ID(VG) of two minimum size devices biased during exposure with VDS =VGS = 1.2 V (diode) and VDS = 1.2 V,VGS = 0 V (onlyVDS). While the radiation response in the VG&0 V region of the curve is strongly dependent on the applied bias, at VG.0 V the post-irradiation ID(VG)characteristic of both devices is dominated by a very similar parasitic current. The same insensitivity of RIFF to the gate voltage applied during Fig. 5. ID(VG)characteristic of a 1µm×0.06 µmfrom Man. C, measured before irradiation (solid lines) and after 6,100 and 1 Grad(SiO2). The dotted vertical line indicates the VG= 0 V point, where the IOF F is measured. Fig. 6. ID(VG)characteristic of 2devices from Man. A biased in diode (VDS =VGS = 1.2 V) and onlyVDS (VDS = 1.2 V,VGS = 0 V) configuration. The effect of the applied bias is evident for VG&0 V but is negligible in the VG.0 V region of the curve. irradiation has been measured also in devices from Man. B (not shown), which have a monotonic IOF F (TID) as those from Man. A. Man. C could not be measured with different biases. In addition to bias, also temperature can influence the RIFF response. The left plot in Figure 7 reports the ID(VG)characteristics of the 1µm×0.06 µmnMOSFET from Man. A already shown in Figure 2. After irradiation, it has been annealed for 10 h at 25 ◦C and, after that, for 20 h at 100 ◦C, with VGS =VDS = 1.2 V. All the curves reported in Figure 7 have been measured at T= 25 ◦C. High temperature strongly accelerates the post-irradiation evolution, provoking the removal of the positive charge trapped in the oxide and, as a consequence, decreasing the leakage current. A similar behaviour can also be found in samples from Man. C, as shown in the right plot of Figure 7. In this case, all the ID(VG)characteristics have been Page 4 of 9Transactions on Nuclear Science - Copy for Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 5 Fig. 7. Effect of the annealing on an ID(VG)characteristic of a 1µm× 0.06 µmnMOSFET from Man. A (left) and Man. C (right). High temperature removes in few hours the radiation-induced leakage current. All measurements in the device from Man. A have been taken at T= 25 ◦Cwhile those from Man. C have been taken at T= 100 ◦C. Fig. 8. Influence of temperature in RIFF. While Man. C has larger IOF F increase at T=−30 ◦C, RIFF in Man. A does not show a significant dependence on temperature in the studied range. measured at T= 100 ◦C. During high-temperature annealing, the leakage current decreases significantly already in the first 10 h after the end of the exposure. While high temperature helps to remove the positive trapped charge causing RIFF, low temperatures can increase the leakage current induced by TID. Figure 8 shows the variation in the order of magnitude of IOF F for 0.12 µm×0.06 µmdevices from Man. A and Man. C. When irradiated at T=−30 ◦C (dashed lines), the peak reached by the IOF F of the nMOS transistor from Man. C is more than an order of magnitude higher that the IOF F peak reached at T= 25 ◦C. Note also that the second increase in IOF F is only present at T= 25 ◦C. On the other hand, RIFF in Man. A is almost the same at T= 25 ◦Cand T=−30 ◦C. STI current DRAIN SOURCE n+ n+ + ++ ++ ++ + ++ + + + + + ++ ++ ++ + ++ + + + + W L CHANNEL DRAIN SOURCE STI DRAIN SOURCE STI + ++ ++ ++ + ++ + + + + + ++ ++ ++ + ++ + + + + W L CHANNEL STI current DRAIN SOURCE n+ n+ p+ p+ ------------ ------------ ------------ ------------ Fig. 9. Schematic representation of the Radiation Induced Narrow Channel effects (RINCE). In narrow transistors (bottom row), the electric field generated by the charge trapped in the STI influences a larger percentage of the channel (right column) [12], [7], [20]. 2) Radiation-Induced Narrow Channel Effects (RINCE): As for RIFF, also RINCE is related to build up of charge in the STI and at its interface. In RINCE, the electric field generated by the trapped charge influences the electric field in the channel, also affecting threshold voltage and transconductance. Figure 9 shows a schematic representation of RINCE: the amount of charge trapped in the STI is roughly independent from the size of the device, but narrower devices have a larger percentage of the channel influenced by the lateral electric field generated by the oxide- and interface-trapped charge. As a consequence, narrow transistors are more sensitive to TID. In the rest of the discussion we will mainly show results from Man. A and Man. B since the available test structures from Man. C are not ideal to study RINCE. However, clear indication of radiation-induced narrow channel effects have been found also in Man. C, suggesting that RINCE is a common feature of nanoscale CMOS technologies that needs to be taken into account when designing rad-hard circuits. Figure 10 shows the radiation response of the Isat ON , i.e. the drain current measured at VGS =VDS = 1.2 V (−1.2 V for pMOS), of nMOS (top) and pMOS (bottom) devices from Man. A (left) Man. B (right), exposed to 100 Mrad(SiO2). The samples have been irradiated at 25 ◦C with both nMOS and pMOS transistors biased with VGS =VDS =±1.2 V.W ranges from 0.12 to 1µmwhile L= 10 µm. The choice of this gate length is dictated by the need to reduce radiation-induced short channel effects (RISCE). As the name suggests, the latter are more evident in short channels and become negligible when Lis sufficiently large. In other words, the radiation response of the devices reported in Figure 10 is dominated by the charge trapped in the STI. For both nMOS and pMOS transistors, narrower devices have a more evident evolution with TID. In particular, nchannels show a similar radiation response with a peak in the percentage variation of Isat ON of ∼10 % between ∼1and Page 5 of 9 Transactions on Nuclear Science - Copy for Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 6 Fig. 10. Isat ON (TID) evolution of long-channel MOS transistors from Man. A (left) and Man. B (right), irradiated to 100 Mrad(SiO2). Narrower devices have a more pronounced evolution (RINCE). The different sign of trapped charge in nMOS produces the non-monotonic behavior visible in the plots on top. On the other hand, in pMOS devices both oxide- and interface-trapped charge are positive, leading to a monotonic degradation of the current. ∼5 Mrad(SiO2)for Man. A and ∼20 % at ∼10 Mrad(SiO2) for Man. B. This non-monotonic behavior has been explained by a fast built-up of positive oxide charge, which lowers the threshold voltage and increases the drain current, slowly compensated by the formation of negative interface-trapped charge [12], [7]. Note that a similar explanation has been used for the non-monotonic behavior of the RIFF measured in transistors from manufacturers B and C (Figure 4). However, RIFF in samples from Man. A shows a monotonic response (Figure 2), indicating that the build-up of positive charge constantly increases with TID and the impact of interface traps is not sufficient to reduce the parasitic paths. Therefore, although they are both caused by charge trapped in the STI, RINCE and RIFF have different build-up/annealing mechanisms. The reasons for this discrepancy have never been properly understood and will be addressed in future work. In pMOS both oxide- and interface-trapped charge is positive [21], leading to a monotonic radiation response and overall degradation that is comparable between Man. A and Man. B. The variation in the ION is caused by shifts in both threshold voltage (VT H ) and transconductance (gm), as indicated in Figure 11 for a 0.12 µm×10 µmdevice. In this plot, the solid lines with circular markers show the evolution of Man. A while Man. B is represented by the dashed lines with triangular markers. In nMOS, reported on the left column, the variation in both Vsat T H (top) and gmlin MAX (bottom) is more evident in the device from Man. B, as expected by the larger Isat ON increase shown in Figure 10. The difference between Man. A and Man. B is smaller in pMOS and mainly visible in transconductance, with Man. B showing slightly less degradation. The evolution of RINCE with TID is consistent between Man. A and Man. B even when the devices are polarized with different voltages during exposure. Figure 12 shows the Isat ON (TID) response at TID ≥10 Mrad(SiO2)of 0.12 µm×10 µm Fig. 11. Top row: Vsat T H shift of a 0.12 µm×10 µmnMOS (left) and pMOS(right) device from Man. A and Man. B. The evolution of the Man. A is reported in solid lines, while dashed line are used for Man. B. While in pMOS the Vsat T H evolves in a very similar way for both processes, nMOS from Man. B have a larger negative threshold voltage shift. Bottom row: the percentage variation of the peak of the transconductance measured in linear region (gmlin MAX ) is more evident in Man. B for nMOS and Man. A for pMOS. Fig. 12. Impact of bias on RINCE. For TID <10 Mrad(SiO2), RINCE is only slightly influenced by the bias applied during exposure, while at higher doses both VGS and VDS can affect the radiation response of narrow transistors. In nMOS, low VGS and high VDS tend to further increase the current after the first peak. In pMOS, the application a VGS <0 V induces a larger Isat ON degradation. nMOS and pMOS devices to which four different polarizations have been applied during irradiation. The ION evolution after the peak in the radiation response of nMOS is influenced by both VGS and VDS . The presence of a VGS >0 V tends to reduce the current, while a VDS >0 V can provoke a further increase in Isat ON . Therefore, in the onlyVDS configuration the drain current can shift towards higher values after the first peak. This phenomenon was identified and briefly studied in [20] and is called Ultra-high-dose Drain Current Increase (UDCI). The physical mechanisms underlying this effect have not yet been fully understood and will be discussed in a future Page 6 of 9Transactions on Nuclear Science - Copy for Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 7 TABLE I TEMPERATURE EFFECT ON RINCE. %Isat ON Mrad(SiO2) 0.12 µm×10 µmT◦C 1 10 100 500 nMOS Man. A 25 8.23 8.96 4.96 1.90 −30 10.08 10.95 7.21 3.54 Man. B 25 11.34 21.26 20.03 15.59a −30 12.19 22.99 21.99 15.70 pMOS Man. A 25 −5.84 −11.65 −21.53 −36.21 −30 −7.80 −14.59 −22.86 −31.30 Man. B 25 −7.72 −11.27 −19.18 −47.88 −30 −8.34 −10.78 −18.15 −29.34 aMeasured at TID = 400 Mrad(SiO2) paper. Also pMOS from both Man. A and Man. B are influenced by VGS , with more negative values provoking a larger degradation. RINCE is only marginally influenced by temperature variations in the range −30 ◦C≤T≤25 ◦C. Table I reports the percentage shift of Isat ON for nMOS and pMOS 0.12 µm×10 µm devices from Man. A and Man. B, measured at 25 and −30 ◦C. For TID ≤100 Mrad(SiO2), the degradation is comparable at both temperatures, while at higher doses pMOS transistors irradiated at 25 ◦C shows a slightly larger decrease in the maximum drain current. The results shown in this section prove that both RIFF and RINCE are phenomena related to the presence of the STI, with similar trends in different 65 nm CMOS processes. The detailed study of these two effects has also revealed that, although total dose sensitivity of STI is a well known issue, exposure to very high doses leads to new and not yet fully understood phenomena, as the rebound of the leakage current at very high doses (Figure 4), the UDCI effect (Figure 12) or the differences in the build-up/annealing rate of RIFF and RINCE in the same device. B. Spacers-related effects Recent works [7], [22], [23] revealed that spacers are an important element in the radiation response of nanoscale CMOS technologies exposed to ultra-high doses. Spacers are a pair of auxiliary oxides located on both sides of the polysilicon gate, consisting of a thick layer of SiO2surmounted by a even thicker layer of Si3N4[24], [25], as shown by the TEM image reported in Figure 13. The radiation-induced effects related to the presence of the spacers can be divided in two main phenomena [22]: 1) Build-up of charge in the spacers and consequent increase in series resistance and decrease in ION 2) Temperature-activated transport of H+from the spacers into the gate oxide, provoking the depassivation of interface traps and: •a significant VT H shift Fig. 13. TEM image of a transistor in 65 nm CMOS technology [22]. Fig. 14. RISCE in the 3processes. To remove the influence of the STI, all the reported devices are either ELT (Man. A and Man. B) or have a W large enough to neglect RINCE (W= 2 µmin Man. C). Top: influence of the channel length on the radiation response. In all the processes, a TID = 100 Mrad(SiO2)provokes a larger degradation in shorter devices. Bottom: when exposed to high temperature (HT), short/wide channel transistors (or ELT) from the 3processes have a similar post-irradiation evolution, with a large VT H shift and an evident asymmetry. •if transistors are irradiated in diode configurations, they become asymmetrical, meaning that the ID(VG) characteristics change if the role of the source and the drain is reversed Since both these effects are dependent on the channel length, whit shorter devices having a higher sensitivity, they have been described as Radiation-Induced Short Channel Effects (RISCE s) [7], [22]. As for RIFF and RINCE, also RISCE is a phenomenon with similar characteristics in all the three studied processes. The top plot in Figure 14 shows the percentage degradation of ION for short (L= 60 nm) and long (L= 4 µmtransistors for Man. A and Man. B and L= 2 µmfor Man. C) pMOS devices exposed to a TID of 100 Mrad(SiO2). In the samples from Man. A and Man. B, enclosed layout transistors (ELTs) have been used to remove the influence of the STI, while in the devices from Man. C the channel is large enough (W= 2 µm) to neglect RINCE. Short channel devices show a Page 7 of 9 Transactions on Nuclear Science - Copy for Review 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, XXXX 2020 8 larger degradation in all the three processes, a clear indication of RISCE. The bottom plot of Figure 14 demonstrates that the performance degradation is caused by similar mechanisms. This plot reports the Vsat T H shift for short/wide devices, measured in nominal (NOM) and reverse (REV) configuration (i.e. switching the role of source and drain), irradiated to 100 Mrad(SiO2)and then annealed at T= 100 ◦C. The trend of the threshold voltage is comparable in all the processes and follows what described in [22]: after irradiation the Vsat T H has a relative small variation, but when the temperature of the sample is raised, the threshold voltage shifts of hundreds of mV and the transistor becomes strongly asymmetric, with a significant larger variation in the nominal configuration. The very distinctive behaviour of VT H in the post-irradiation evolution proves that the degradation mechanisms are the same in all processes. The radiation-induced effects related to the presence of the spacers must therefore be taken into account when exposing a nanoscale planar CMOS technology to ultrahigh doses. IV. CONCLUSION WHEN exposed to high and ultra-high doses, the performance variation of all the studied processes shows similar trends. STI and spacers dominate the radiation response, provoking RIFF, RINCE and RISCE. Thanks to these similarities and to the numerous data gathered, we can propose some guidelines to properly qualify to ultra-high doses a circuit designed with a 65 nm CMOS technology. •Total dose: both RINCE and RIFF can be highly nonmonotonic. It is not sufficient to verify if the circuit works after the maximum expected total dose, but its behavior must be constantly checked throughout the exposure. •Bias: when performing a qualification test the device under test must be biased in a configuration as close as possible to the real application. Bias can significantly influence the radiation response, affecting both RINCE and RISCE. •Temperature: all the studied effects strongly depend on temperature. The qualification should therefore be performed at the same temperature of the real application. •Time: since temperature accelerates processes that occur also at lower temperatures, a common procedure to asses the long-term evolution of radiation effects is to anneal the device at high temperature after irradiation [26], [27]. However, the post-irradiation annealing could lead to a significant overestimate of the total performance degradation in devices intended for use in low-temperature environments. For instance, the results presented in [22], [20] show a large difference in the post-irradiation VT H shift in short-channel transistors. While this shift takes place in a few hours at T= 100 ◦C, hundred of years are needed for the same effect to occur at T=−30 ◦C. In addition to the steps outlined above, the qualification of circuits to be used in ultra-high TID environments should also take into account dose-rate effects. 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