LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies

1 LC-VCO Design Optimization Methodology Based on the gm/IDRatio for Nanometer CMOS Technologies Rafaella Fiorelli, Eduardo Peral´ ıas and Fernando Silveira, Abstract In this paper, an LC-VCO design optimization methodology based on the gm/IDtechnique and on the exploration of all inversion regions of the MOS transistor is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semi-empirical models of MOS transistors and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design trade-offs are easily identified. Four LC-VCO designs in different inversion regions in a 90 nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4 GHz VCO operating in moderate inversion. The designed VCO draws 440 µA from a 1.2V power supply and presents a phase noise of −106.2dBc/Hz at 400 kHz from the carrier. I. INTRODUCTION The increasing demand of wireless applications with special emphasis on low power requirements forces radio-frequency designers to work at the limits of the technology. To achieve these challenging specifications, best performance is mandatory in each block of the circuit, especially in terms of power consumption, noise and linearity. In addition, since a few years ago, the extended use of CMOS technologies enables RF designers to reduce costs as well as reaching good performance. Rafaella Fiorelli and Eduardo Peral´ ıas are with the Instituto de Microelectr´ onica de Sevilla, CNM-CSIC, Seville, 41092, Spain (e-mail:[email protected], [email protected]). Fernando Silveira is with the Instituto de Ingenier´ ıa Elctrica, Universidad de la Rep´ ublica, Montevideo, 11300, Uruguay (e-mail:[email protected]). October 29, 2013 DRAFT 2 Fig. 1. (a) gm/IDand (b) gds/IDvs. i=ID/(W/L)for four nMOS transistors and a VDS = 600 mV . Typical limits of strong (SI), moderate (MI) and weak (WI) inversion regions are shown. The requirements of an RF block, such as gain, noise or power consumption, strongly depend on the RF application. For example, an application that is very demanding in terms of noise would need to accept high power consumption, whereas a very low power design would cope with just enough non-very-low noise values. As these two characteristics are directly related, their trade-off has to be achieved optimizing the design of RF blocks. This work explores those compromises in order to optimize inductor-capacitortank voltage controlled oscillators (LC-VCOs). This study is relevant as VCOs, due to their phase noise, are responsible for most part of the error in the processed signal in an RF receiver [1], as well as for a non-negligible percentage of the system current consumption. The mentioned optimization is done by exploiting the consumption-spectral purity trade-off of the VCOs in order to use just the needed current to fulfill the application requirements. This is achieved by using the ratio of transconductance to drain current gm/IDmethodology presented in [2], [3] and taking advantage of operation in all the inversion regions (weak, moderate and strong) of the MOS transistor (MOST) [4]. The gm/IDratio of a saturated MOST is directly related to its inversion level. The inversion level is directly associated with the normalized current or current density, defined as i=ID/(W/L)and dependent on the gate, source and drain voltages [5]–[7]. The relationship between gm/IDand i-and hence IDfor a certain MOST aspect ratio W/Lis biunivocal; a typical form of this curve can be October 29, 2013 DRAFT 3 appreciated in Fig. 1(a). Several factors make the gm/IDratio a very useful parameter for describing the state of operation and performance of a MOST and exploring its design space. Firstly, the ease to write circuit design expressions as a function of this parameter, since generally the transconductance or the current are part of them. Secondly, its value gives a direct indication of the inversion region and of the efficiency of the transistor in translating current consumption into transconductance. Finally, its variation is constrained to a very small range, efficiently covered with a grid of some tens of values of gm/ID (e.g. from 3 V−1to 28 V−1for a nanometer bulk nMOS). Utilizing this variable on the expressions of the VCO characteristics and sweeping gm/IDallows to obtain a set of design space maps of phase noise, gain, power consumption, among others, as it will be shown in Section V. This graphical representation helps the designer to study the evolution and trade-offs of some of these characteristics when working in any of the three inversion regions. The MOST channel length reduction, as it is shown below, permits the design of RF blocks in weak and moderate inversion (WI/MI) with less power consumption than when they are biased in the traditional way, in the strong inversion (SI) region. Several RF blocks designed in CMOS technologies and working in MI or WI have been reported in the last decade. Porret et al. [8] and Melly et al. [9] present, respectively, the design of a receiver and a transmitter working at 433 MHz in MI. Ramos et al. [10] showed a 950 MHz LNA in MI-WI. The authors have presented an RF amplifier for 900 MHz [11] and a 2.4 GHz VCO [12] both designed in MI regions. Lee and Mohammadi [13] presented a 2.4 GHz VCO design in WI whereas Hsieh and Lu [14] designed a 5 GHz receiver front-end in MI and WI. Finally, Perumana et al. [15] designed a subthreshold 2.4 GHz receiver. Although the mentioned works successfully take advantage of working in these MOS regions of operation, they do not present a systematic methodology for choosing the operating point. This issue is covered in this paper for LC-VCOs. The effect of moving from SI through WI implies a considerable current reduction, but as a counterpart, parasitic capacitances are higher as the transistor dimensions increase. That is why, with sub-micrometer technologies, high frequency design in MI is limited to around one gigahertz [11]. Nowadays, the advent of nanometer CMOS technologies prepared for radio-frequency designs enable to design in MI with working frequencies of several gigahertz. This idea considers the conservative limit where the MOS transistor frequency is below the quasistatic-limit frequency of one tenth of fT[4], with fTthe MOST transition frequency. To visualize these facts, fTand gm/IDversus IDare depicted in Fig. 2 for a pMOS transistor in 90 nm technology. These results show that increasing ID(i.e. moving to SI) leads to a rise in fTand a reduction in the gm/IDratio. It is also appreciated in Fig. 3, where the relation between fT and gm/IDand the overdrive voltage VOD =VGS −VT, a parameter classically utilized in RF designs October 29, 2013 DRAFT 4 Fig. 2. gm/IDand fTversus IDof a pMOS transistor with an aspect ratio of 360 µm/100 nm. Fig. 3. fTversus gm/IDand versus the overdrive voltage VOD for nMOS transistors. to indicate the bias point, are depicted. These plots also show that, in spite of the considerable fall in fT when working in MI, the resulting value is enough to work in the RF range of some gigahertz. The proposed optimization methodology follows four steps. First of all, the DC and low frequency, small signal behaviour of the MOS transistor has to be reflected in suitable expressions or curves of gm/ID,gds/IDand intrinsic capacitances versus i, as it will be discussed in Section II. In second place comes the extraction of the models for passive components, presented in Section III. In third place is the modeling of the LC-VCO, where the expressions of phase noise (L), output voltage Vout and VCO flicker corner frequency fc,1/f3are reordered to make them function of gm/IDand i. This step is presented in Section IV. Finally, a design flow is provided; it organizes the necessary computations based on the third step and the decisions constrained by the VCO specifications, while it uses the technological data October 29, 2013 DRAFT 5 collected in the first two steps. This fourth phase is developed in Section V. Sections VI and VII validate this design methodology, contrasting four VCO designs with their correspondent electrical simulations as well as presents measurement results of a specific implementation. Section VIII summarizes the main contributions of this work. II. MOS TRANSISTOR ANALYSIS The first step of the methodology, in order to generate a database with its three most important characteristic data, is the correct modeling of the MOST in DC behaviour and in small signal, low frequency of operation. Firstly, the transconductance to current ratio gm/IDversus iis used to give an indication of the transistor operation region as well as for calculating MOST dimensions. Secondly, the output conductance gds is also considered because in nanometer technologies this value is considerably increased, and especially for LC-VCOs it affects the final transconductance value. The ratio gds/ID versus iis also applied here [3]. In third place, the MOST intrinsic capacitances are included because, in RF, they substantially modify the circuit behaviour. Considering the quasistatic limit frequency, only Cij, with ij={gs, gd, gb, bs, bd}, are included. In order to simplify the modeling, the capacitances are considered to be proportional to the MOST gate area, WL. Hence, each normalized MOST capacitance C0 ij =Cij/(W L)is considered equal for all transistors for a specific width range. Because C0 ij are also dependent on the inversion zone, the curve C0 ij versus iis used. Finally the noise constants have to be known. In this work we have considered these two constants: a) the excess noise factor λof the white noise [5], and b) the flicker noise constant KF(or K0 f, if it is divided by the MOS normalized oxide capacitance C0 ox). The gm/ID,gds/IDand C0 ij versus icurves vary only slightly with MOST width and length [3]; this change is only non-negligible in very narrow devices. Fig. 1(b) shows, for a 100 nm nMOS transistor, and four widths W={360 nm, 3.6µm, 36 µm, 360 µm}, the simulated results of the curves of gm/ID and gds/IDversus i. For this technology, the spread of the curves is almost imperceptible. Because of the slight variation in the curves for such a large width range, the methodology presented here succeeds. In this paper, a semi-empirical MOS model is utilized to describe the MOST because it considers the second and higher order effects of nanometer technologies, and it is easily obtained by extracting MOS characteristics via DC simulation. The use of analytical compact models, such as EKV [5], ACM [6] or PSP [16], have been discarded because the fitting of parameters is very time consuming; however, if properly set, these models can also be used. To acquire the required characteristics curves for this semi-empirical model, a very simple scheme is utilized: transistor gate and drain nodes are connected to October 29, 2013 DRAFT 6 a DC voltage source, while source and bulk nodes are connected either to ground (nMOS transistor) or to the supply voltage (pMOS transistor). Then, the gate voltage VGis swept extracting ID,gm,gds and C0 ij. The drain voltage is set around its expected DC value in the target circuit. To get a very complete dataset the same simulation should be run for a set of widths (for example, the set chosen for Fig. 1), when a fixed transistor length value is used. Otherwise, following the same idea, a small set of lengths should be chosen. Finally, λand KFvalues should be obtained from handling MOST noise data provided by the foundry or estimated from simulations or measurements [17]. III. ANALYSIS OF PASSIVE COMPONENTS The second step in the methodology is the characterization of passive components. LC-VCOs performance is very much dependent on their non-idealities. Their characterization can be done either by semi-empirical models of library cells provided by the foundry or by electromagnetic solvers such as ASITIC [18] or ADSTMMomentum. Electromagnetic solver has major drawbacks: 1) the need to have the technological data provided by the foundry to obtain accurate descriptions, and 2) the high computational time spent to obtain the solutions. In this paper, for the sake of efficiency, we utilize passive element cells supplied by the foundry. By means of S-parameter analysis, we obtain their equivalent complex admittance at the working frequency, f0. A. Inductor modeling In this work, the differential tank inductor is modeled at the oscillation frequency as a network of an equivalent inductor Lind and a parallel parasitic resistor Rind. S-parameter analysis is applied to extract the parameters of the model with the inductor in a differential configuration. In order to obtain a complete database, the analysis has to be done for a large set of inductors. In this work, the best inductor is considered the one with the highest parallel resistance, since it will lead to the lowest required transconductance and hence consumption, as it will be shown in Section IV. Looking for biunivocal relationships between Lind and Rind, computational routines are implemented to find, for a particular inductance value, the nearest best inductor. Figure 4 displays the resulting Rind of sweeping coil conductor width for our standard 90 nm CMOS process and highlights the inductors dataset with the maximum resistances. The data in this plot show that the highest resistances come with the largest inductance values. October 29, 2013 DRAFT 7 Fig. 4. Parallel resistance versus inductance value Lind for four inductor widths wwith a common external diameter of 300 µm, at f0=2.4 GHz. The black line represents the inductors with the highest resistance. B. Varactor modeling Varactor parasitic resistance has been usually neglected, especially due to its high value compared with inductor parasitic resistance. However, on-chip coils have improved and it is possible to have a varactor conductance comparable with inductor conductance. Therefore, varactor parasitic resistance extraction by simulations is now necessary, in order to check whether it must be considered in the design. For the accumulation nMOS varactors used in the design presented in Section VI, the maximum value of gvar over the varactor control voltage range is approximately 70 µS; so varactor conductance can be ignored compared to the conductances of the other VCO components. IV. VCO MODELING The LC-VCO topology used in this work is depicted in Fig. 5. It shows a cross-coupled complementary VCO with its LC tank, biased with a pMOS current mirror, which drives the Ibias current to the LCVCO. This pMOS structure is used for its better flicker noise performance with respect to an nMOS one with the same size. Cross-coupled transistors provide the needed negative feedback and a pMOS-nMOS complementary structure increases VCO transconductance while consuming the same quiescent drain current, ID, with Ibias = 2 ·ID. A small-signal model of the LC-VCO of Fig. 5 is displayed in Fig. 6(a) jointly with its simplified model in Fig. 6(b). It comprises the equivalent inductance of the differential inductor Lind and the equivalent capacitance of the varactors Cvar, both calculated at the oscillation frequency f0; the equivalent parasitic capacitances of the nMOS and pMOS transistors CnMOS and CpMOS; and the load capacitance October 29, 2013 DRAFT 8 Fig. 5. Cross coupled complementary LC-VCO. Cload represents the differential capacitive load at the output of the VCO. Cload. In this paper, the nMOS and pMOS sizing is done in order to match the pMOS and nMOS transconductances, gm,p and gm,n, i.e gm,n =gm,p =gm. Considering, respectively, Ctank and gtank as the equivalent capacitance and conductance of the VCO tank, the well-known oscillation frequency and oscillation condition expressions are, respectively f0=1 2π√LindCtank (1) and gtank ≤gm,p 2+gm,n 2=gm(2) where Ctank =Cvar +CpMOS +CnMOS 2+Cload (3) and gtank =gind +gvar +gds,p 2+gds,n 2(4) where gds,n and gds,p are the output conductances of the nMOS and pMOS transistors; gind = 1/Rind and gvar are the parasitic conductances of the inductor and varactor, respectively. October 29, 2013 DRAFT 9 Fig. 6. Small signal LC-VCO model: (a) a complete model and (b) a reduced model. Ctank and gtank are, respectively, the VCO equivalent capacitance and conductance. Considering the five capacitance model of the MOS transistor, the equivalent cross-coupled transistor capacitance CMOS, valid both for the nMOS and pMOS transistors, is CMOS = 4Cgd + (Cgs +Cgb +Cdb +Cds).(5) Due to the expected technology parameter variations, a safety margin factor kosc -usually called oscillation factoris utilized in (2) to transform the inequality to gm=kosc gtank (6) where kosc is generally in the range of 1.5 to 3. The MOST intrinsic gain Ai, defined as the gain of a common source transistor amplifier loaded by an ideal current source [2], is Ai=gm/gds = (gm/ID)/(gds/ID). Since gvar is considered negligible with respect to gind and gds, (4) is transformed into gtank ∼ =gind +1 2gm,p Ai,p +gm,n Ai,n  =gind +gm 21 Ai,p +1 Ai,n .(7) October 29, 2013 DRAFT 16 VII. EXPERIMENTAL RESULTS The characteristics of the VCO were measured on die using a microprobe station. To measure its spectrum and phase noise the Agilent Spectrum Analyzer E4440A was employed. A set of phase noise measurements has been done to the fabricated chip. Unfortunately, the buffer does not work properly and interferes with the VCO behaviour, so necessary the measurements were done with the output buffer switched off. Figure 13 displays the variation of f0with control voltage Vcontrol. In the inset of Fig. 13, it is shown the VCO spectrum for a Vcontrol = 0V. The minimum bias current where a clean spectrum without interferers is obtained was ID=220 µA. For this current, the phase noise versus the offset frequency, with the carrier at 2.16 GHz (Vcontrol = 0V) is shown in Fig. 14. The phase noise at 400 kHz from the carrier is -106.2 dBc/Hz. The measured flicker corner frequency fc,1/f3is 203 kHz, whereas the simulated flicker corner frequency, shown in Table I, is 72 kHz. This rise in fc,1/f3 respect to the simulated data of P4, happens because Vout is distorted when the buffer is turned off. Γav rises to approximately 0.4, and the computed fc,1/f3is 257 kHz, very near the measured data. The current IDwas also swept to 310 µA and a set of phase noise measurements at 400 kHz from the carrier were performed (forty measurements of Lwere taken for each current value), as depicted in Fig. 15, considering again a carrier frequency around 2.16 GHz. The theoretical curve of (11) is superimposed with experimental data, considering α= 0.65,kosc = 3 and γ= 0.55. The fitted model is extended up to the nominal IDcurrent of 165 µA, obtaining an extrapolated phase noise value of -104.6 dBc/Hz. Good agreement exists between model, simulations and measurements. The minimum measured IDwhere the VCO works, for three samples’ average, is 62.5 µA; 13.5% higher than the expected value of 52 µA obtained from the design flow. The output voltage when the buffer is switched on, for Ibias=440 µA is 630 mV, a bit lower than expected. Table II compares the performance of the designed LC-VCO in moderate inversion with that of some prior works, where the well known figure-of-merit (FoM) of the VCO defined in [22] is used. Our VCO is well positioned considering other similar designs, as only the second one has a better FoM. However the later occupies more area than our design because it uses two on-chip inductors, which increases the tank quality factor and reduces the phase noise. VIII. CONCLUSIONS In this paper, an RF LC-VCO design methodology for nanometer technologies based on the gm/ID technique has been presented. The methodology proposed enables a considerable design time reduction October 29, 2013 DRAFT 17 TABLE II PERFORMANCE COMPARISON OF RECENTLY PUBLISHED LC-VCOS. VCO Tech. f0∆fPower LFoM (nm) (GHz) (MHz) (mW) (dBc/Hz) (dB) [23] 180 2.2 1 5.17 -119 179 [13] 180 2.645 0.4 0.63 -106.4 184.8 [15] 180 2.5 1 1.2 -103.7 171 [22] 180 1.57 1 3.06 -120 180 This work 90 2.16 0.4 0.53 -106.2 183.6 as little re-design is needed. It also shows the VCO trade-offs, providing beforehand a global view of the VCO behaviour when adjusting certain component parameters during the design. MOST, inductor and varactor data were extracted from SpectreRF simulations to accurately and quickly model these components and include that data in the design flow. VCO modeling equations were modified to introduce IDand the MOS variable gm/ID, in order to easily see the compromises of working in different MOS inversion regions. Specially, Hajimiri phase noise model equations were re-ordered to express them in terms of gm/ID. Plots of several variables involved in the VCO design were shown and compromises with the inversion region or the selection of the inductor were highlighted. It has been shown that designing in moderate and weak inversion leads to reduced current while phase noise is increased; on the other hand an increment of the inductor value (and hence a increment in its equivalent parallel resistance) contributes to an improvement in the VCO spectral purity. Four designs were simulated to validate the method. Finally, an application example was implemented to show the usefulness of the method, as well as to prove the validity of the phase noise model. Phase noise results from the calculations of our design routines, electrical simulations and measurements are in agreement. APPENDIX DEDUCTION OF PHASE NOISE EXPRESSIONS A. Expression of phase noise of a LC-VCO in the 1/f2spectrum region. The expression of phase noise for an arbitrary oscillator in the 1/f2region of the phase noise spectrum expressed by Hajimiri in [20] is L1/f2(∆f) = 10 log Γ2 rms q2 max i2 n/∆f 2∆f2!(16) October 29, 2013 DRAFT 18 where Γrms is the rms value of the impulse sensitivity function ISF defined in [20], qmax is the maximum charge displacement across the capacitor in the output nodes, ∆fis the frequency offset respect to the oscillation frequency f0, and i2 n/∆fis the power spectral density of the noise source considered at the output nodes. To evaluate the phase noise expression for our LC-VCO, let’s obtain the expressions of each term in (16). Firstly we calculate the most important VCO white noise sources. For simplicity we will consider that no correlation exists between them. Superposition will be applied when substituting their expressions in (16). The general expression of MOS white noise is [4] i2 w,MOS ∆f= 4kBTγgdo = 4kBTγ αgm.(17) The equivalent power spectral density of the two nMOS and two pMOS is [24] i2 w,MOSeq ∆f=1 2(i2 w,n ∆f+i2 w,p ∆f)(18) Substituting (17) in (18) i2 w,MOSeq ∆f∼ =4kBTγgm 1 21 αn +1 αp = 4kBTγ αeq .(19) The white noise of each cross-coupled transistor block due to its equivalent drain-source conductance is [4] [25]: i2 w,gds ∆f= 4kBTgds 2= 4kBTgm 2Ai .(20) Considering both nMOS and pMOS equivalent conductances, i2 w,geq ds ∆f= 4kBTgm 21 Ai,n +1 Ai,p .(21) The white noise of the inductor parallel resistance Rind = 1/gind is, applying (9), i2 w,Lind ∆f= 4kBTgind = 4kBTgm k0 osc .(22) The white noise power spectral density of the varactor has been neglected for this deduction as generally gvar gind. October 29, 2013 DRAFT 19 The equivalent white noise power spectral density of the LC-VCO is, from equations, (8), (19), (21) and (22): i2 w,V CO ∆f= 4kBTgmγ αeq +1 k0 osc +1 2Ai,n +1 2Ai,p  = 4kBTgmγ αeq +1 kosc = 4kBTgmλ. (23) Besides, qmax =CtankVout, where Ctank is the equivalent capacitance at the output nodes, expressed as: Ctank =1 4π2f2 0Lind =Q 2πf0Rtank (24) Then, from (10) and (24), qmax is qmax =8 π IDQ (2πf0)=2IDRtank (π3)f2 0Lind .(25) Finally, substituting (23) and (25) in (16), considering Γrms ≈0.5due to the symmetry characteristics of this VCO, and reordering the terms, we obtain L1/f2(∆f) = 10 log kBTπ2 82λ1 Q2 gm ID 1 ID f2 0 ∆f2!(26) B. Expression of phase noise of a LC-VCO in the 1/f3spectrum region. From [20], the following is the general expression of the phase nose in the 1/f3portion of the phase noise spectrum L(∆f)1/f3= 10 log Γ2 av 8q2 max i21/f /∆f ∆f2!(27) Considering that only the MOS transistors injects flicker noise, the total power spectral density of the flicker noise sources is i2 1/f ∆f=1 2 i2 1/f,n ∆f+i2 1/f,p ∆f! =1 2K0 F,ng2 m WnL+K0 F,pg2 m WpL1 f(28) Equations (27) together with (25) and (28) results in the following expression for phase noise in the 1/f3 zone in terms of gm/ID: L1/f3(∆f) = 10 log Γ2 av 8 π2 82 1 L K0 F,n Wn +K0 F,p Wp! 1 Q2 gm ID!2f2 0 ∆f3!(29) October 29, 2013 DRAFT 20 C. Corner frequency of MOST expressed as a function of gm/IDand i. The corner frequency of a MOST fcis obtained equaling the expressions of white noise and flicker noise, resulting in: fc=K0 F 4kBT α γ gm ID ID W/L 1 L2=K0 F 4kBT α γ gm ID i1 L2(30) D. Flicker corner frequency of the VCO phase noise expressed as a function of gm/IDand i. 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Luong, “A 1 V 9.7 mW CMOS frequency synthesizer for IEEE 802.11a transceivers,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 1, pp. 39–48, Jan. 2008. [24] A. Hajimiri, Trade-offs in Analog Circuit Design. Kluwer Academic Publishers, 2002, ch. Trade offs in oscillator phase noise, pp. 551–585. [25] BSIM Research Group, “BSIM3v3 and BSIM4 MOS Model,” 2008, www-device.eecs.berkeley.edu/ bsim3/bsim4.html. Rafaella Fiorelli Rafaella Fiorelli (S’05) was born in Montevideo, Uruguay in 1978. She received her B.Sc. and M.Sc. degrees in Electrical Engineering from the Universidad de la Rep´ ublica, Montevideo, Uruguay, in 2002 and 2005 respectively. She is currently working towards the doctoral degree in electrical engineering. In 2003 she joined the Electrical Engineering Institute of the Universidad de la Rep´ ublica, Uruguay. From 2009 she is working in the IMSE-CNM of Seville, Spain, with a MAE-AECIC Spanish government grant. Her current research includes the implementation of design methodologies of low power RF blocks and BIST test in RF. October 29, 2013 DRAFT 22 Eduardo Peralas Eduardo J. Peral´ ıas received the Ph.D. degree from the University of Seville, (Spain) in 1999. Since 2001, he has been with the Instituto de Microelectr´ onica de Sevilla (IMSE-CNM-CSIC), where he is currently a Tenured Scientist. His main research interests have been in the areas of Mixed Design with emphasis on Analog-to-Digital converters, Test and Design for Testability of Analog and Mixed-Signal Circuits, and Statistical Behavioral Modeling. Fernando Silveira Fernando Silveira (S’89M’90SM’03) received the Electrical Engineering degree from Universidad de la Rep´ ublica, Uruguay in 1990 and the MSc. and PhD degree in Microelectronics from Universit` e catholique de Louvain, Belgium in, respectively, 1995 and 2002. He is currently Professor at the Electrical Engineering Department of the School of Engineering of Universidad de la Rep´ ublica, Uruguay. His research interests are in design of ultra low-power analog and RF integrated circuits and systems, in particular with biomedical application. In this field, he is co-author of one book and many technical articles. He has had multiple industrial activities with CCC Medical Devices and NanoWattICs, including leading the design of an ASIC for implantable pacemakers and designing analog circuit modules for implantable devices for various companies worldwide. October 29, 2013 DRAFT 23 Fig. 10. L1/f2in dBc/Hz mapped versus gm/IDand Lind. The text-box displays the characteristics and parameters of the LC-VCO associated with the picked point (P4 in this example). Fig. 11. Phase noise SpectreRF simulations for designs P1,P2,P3 and P4. October 29, 2013 DRAFT 24 Fig. 12. Layout and microphotograph of the fabricated VCO. Fig. 13. Carrier frequency f0versus Vcontrol and output spectrum (inset) at Vcontrol = 0 with the buffer switched off. October 29, 2013 DRAFT 25 Fig. 14. Lwith the VCO biased with Ibias = 2 ·ID= 440µA and f0= 2.1639GHz (buffer switched off). 1/f2and 1/f3 slopes are shown as well as the estimated flicker corner fc,1/f3. Fig. 15. Phase noise measured and estimated by (11) sweeping only ID. October 29, 2013 DRAFT