LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies

1 LC-VCO Design Op imiza ion Me hodology Based on he gm/IDRa io o Nanome e CMOS Technologies Ra aella Fio elli, Edua do Pe al´ ıas and Fe nando Sil ei a, Abs ac In his pape , an LC-VCO design op imiza ion me hodology based on he gm/ID echnique and on he explo a ion o all in e sion egions o he MOS ansis o is p esen ed. An in-dep h s udy o he comp omises be ween phase noise and cu en consump ion pe mi s op imiza ion o he design o gi en speci ica ions. Semi-empi ical models o MOS ansis o s and induc o s, ob ained by simula ion, join ly wi h analy ical phase noise models, allow o ge a design space map whe e he design ade-o s a e easily iden i ied. Fou LC-VCO designs in di e en in e sion egions in a 90 nm CMOS p ocess a e ob ained wi h he p oposed me hodology and e i ied wi h elec ical simula ions. Finally, he implemen a ion and measu emen s a e p esen ed o a 2.4 GHz VCO ope a ing in mode a e in e sion. The designed VCO d aws 440 µA om a 1.2V powe supply and p esen s a phase noise o −106.2dBc/Hz a 400 kHz om he ca ie . I. INTRODUCTION The inc easing demand o wi eless applica ions wi h special emphasis on low powe equi emen s o ces adio- equency designe s o wo k a he limi s o he echnology. To achie e hese challeng- ing speci ica ions, bes pe o mance is manda o y in each block o he ci cui , especially in e ms o powe consump ion, noise and linea i y. In addi ion, since a ew yea s ago, he ex ended use o CMOS echnologies enables RF designe s o educe cos s as well as eaching good pe o mance. Ra aella Fio elli and Edua do Pe al´ ıas a e wi h he Ins i u o de Mic oelec ´ onica de Se illa, CNM-CSIC, Se ille, 41092, Spain (e-mail:[email p o ec ed], [email p o ec ed]). Fe nando Sil ei a is wi h he Ins i u o de Ingenie ´ ıa Elc ica, Uni e sidad de la Rep´ ublica, Mon e ideo, 11300, U uguay (e-mail:[email p o ec ed]). Oc obe 29, 2013 DRAFT 2 Fig. 1. (a) gm/IDand (b) gds/ID s. i=ID/(W/L) o ou nMOS ansis o s and a VDS = 600 mV . Typical limi s o s ong (SI), mode a e (MI) and weak (WI) in e sion egions a e shown. The equi emen s o an RF block, such as gain, noise o powe consump ion, s ongly depend on he RF applica ion. Fo example, an applica ion ha is e y demanding in e ms o noise would need o accep high powe consump ion, whe eas a e y low powe design would cope wi h jus enough non- e y-low noise alues. As hese wo cha ac e is ics a e di ec ly ela ed, hei ade-o has o be achie ed op imizing he design o RF blocks. This wo k explo es hose comp omises in o de o op imize induc o -capaci o - ank ol age con olled oscilla o s (LC-VCOs). This s udy is ele an as VCOs, due o hei phase noise, a e esponsible o mos pa o he e o in he p ocessed signal in an RF ecei e [1], as well as o a non-negligible pe cen age o he sys em cu en consump ion. The men ioned op imiza ion is done by exploi ing he consump ion-spec al pu i y ade-o o he VCOs in o de o use jus he needed cu en o ul ill he applica ion equi emen s. This is achie ed by using he a io o ansconduc ance o d ain cu en gm/IDme hodology p esen ed in [2], [3] and aking ad an age o ope a ion in all he in e sion egions (weak, mode a e and s ong) o he MOS ansis o (MOST) [4]. The gm/ID a io o a sa u a ed MOST is di ec ly ela ed o i s in e sion le el. The in e sion le el is di ec ly associa ed wi h he no malized cu en o cu en densi y, de ined as i=ID/(W/L)and dependen on he ga e, sou ce and d ain ol ages [5]–[7]. The ela ionship be ween gm/IDand i-and hence ID o a ce ain MOST aspec a io W/L- is biuni ocal; a ypical o m o his cu e can be Oc obe 29, 2013 DRAFT 3 app ecia ed in Fig. 1(a). Se e al ac o s make he gm/ID a io a e y use ul pa ame e o desc ibing he s a e o ope a ion and pe o mance o a MOST and explo ing i s design space. Fi s ly, he ease o w i e ci cui design exp essions as a unc ion o his pa ame e , since gene ally he ansconduc ance o he cu en a e pa o hem. Secondly, i s alue gi es a di ec indica ion o he in e sion egion and o he e iciency o he ansis o in ansla ing cu en consump ion in o ansconduc ance. Finally, i s a ia ion is cons ained o a e y small ange, e icien ly co e ed wi h a g id o some ens o alues o gm/ID (e.g. om 3 V−1 o 28 V−1 o a nanome e bulk nMOS). U ilizing his a iable on he exp essions o he VCO cha ac e is ics and sweeping gm/IDallows o ob ain a se o design space maps o phase noise, gain, powe consump ion, among o he s, as i will be shown in Sec ion V. This g aphical ep esen a ion helps he designe o s udy he e olu ion and ade-o s o some o hese cha ac e is ics when wo king in any o he h ee in e sion egions. The MOST channel leng h educ ion, as i is shown below, pe mi s he design o RF blocks in weak and mode a e in e sion (WI/MI) wi h less powe consump ion han when hey a e biased in he adi ional way, in he s ong in e sion (SI) egion. Se e al RF blocks designed in CMOS echnologies and wo king in MI o WI ha e been epo ed in he las decade. Po e e al. [8] and Melly e al. [9] p esen , espec i ely, he design o a ecei e and a ansmi e wo king a 433 MHz in MI. Ramos e al. [10] showed a 950 MHz LNA in MI-WI. The au ho s ha e p esen ed an RF ampli ie o 900 MHz [11] and a 2.4 GHz VCO [12] bo h designed in MI egions. Lee and Mohammadi [13] p esen ed a 2.4 GHz VCO design in WI whe eas Hsieh and Lu [14] designed a 5 GHz ecei e on -end in MI and WI. Finally, Pe umana e al. [15] designed a sub h eshold 2.4 GHz ecei e . Al hough he men ioned wo ks success ully ake ad an age o wo king in hese MOS egions o ope a ion, hey do no p esen a sys ema ic me hodology o choosing he ope a ing poin . This issue is co e ed in his pape o LC-VCOs. The e ec o mo ing om SI h ough WI implies a conside able cu en educ ion, bu as a coun e pa , pa asi ic capaci ances a e highe as he ansis o dimensions inc ease. Tha is why, wi h sub-mic ome e echnologies, high equency design in MI is limi ed o a ound one gigahe z [11]. Nowadays, he ad en o nanome e CMOS echnologies p epa ed o adio- equency designs enable o design in MI wi h wo king equencies o se e al gigahe z. This idea conside s he conse a i e limi whe e he MOS ansis o equency is below he quasis a ic-limi equency o one en h o T[4], wi h T he MOST ansi ion equency. To isualize hese ac s, Tand gm/ID e sus IDa e depic ed in Fig. 2 o a pMOS ansis o in 90 nm echnology. These esul s show ha inc easing ID(i.e. mo ing o SI) leads o a ise in Tand a educ ion in he gm/ID a io. I is also app ecia ed in Fig. 3, whe e he ela ion be ween T and gm/IDand he o e d i e ol age VOD =VGS −VT, a pa ame e classically u ilized in RF designs Oc obe 29, 2013 DRAFT 4 Fig. 2. gm/IDand T e sus IDo a pMOS ansis o wi h an aspec a io o 360 µm/100 nm. Fig. 3. T e sus gm/IDand e sus he o e d i e ol age VOD o nMOS ansis o s. o indica e he bias poin , a e depic ed. These plo s also show ha , in spi e o he conside able all in T when wo king in MI, he esul ing alue is enough o wo k in he RF ange o some gigahe z. The p oposed op imiza ion me hodology ollows ou s eps. Fi s o all, he DC and low equency, small signal beha iou o he MOS ansis o has o be e lec ed in sui able exp essions o cu es o gm/ID,gds/IDand in insic capaci ances e sus i, as i will be discussed in Sec ion II. In second place comes he ex ac ion o he models o passi e componen s, p esen ed in Sec ion III. In hi d place is he modeling o he LC-VCO, whe e he exp essions o phase noise (L), ou pu ol age Vou and VCO licke co ne equency c,1/ 3a e eo de ed o make hem unc ion o gm/IDand i. This s ep is p esen ed in Sec ion IV. Finally, a design low is p o ided; i o ganizes he necessa y compu a ions based on he hi d s ep and he decisions cons ained by he VCO speci ica ions, while i uses he echnological da a Oc obe 29, 2013 DRAFT 5 collec ed in he i s wo s eps. This ou h phase is de eloped in Sec ion V. Sec ions VI and VII alida e his design me hodology, con as ing ou VCO designs wi h hei co esponden elec ical simula ions as well as p esen s measu emen esul s o a speci ic implemen a ion. Sec ion VIII summa izes he main con ibu ions o his wo k. II. MOS TRANSISTOR ANALYSIS The i s s ep o he me hodology, in o de o gene a e a da abase wi h i s h ee mos impo an cha ac e is ic da a, is he co ec modeling o he MOST in DC beha iou and in small signal, low equency o ope a ion. Fi s ly, he ansconduc ance o cu en a io gm/ID e sus iis used o gi e an indica ion o he ansis o ope a ion egion as well as o calcula ing MOST dimensions. Secondly, he ou pu conduc ance gds is also conside ed because in nanome e echnologies his alue is conside ably inc eased, and especially o LC-VCOs i a ec s he inal ansconduc ance alue. The a io gds/ID e sus iis also applied he e [3]. In hi d place, he MOST in insic capaci ances a e included because, in RF, hey subs an ially modi y he ci cui beha iou . Conside ing he quasis a ic limi equency, only Cij, wi h ij={gs, gd, gb, bs, bd}, a e included. In o de o simpli y he modeling, he capaci ances a e conside ed o be p opo ional o he MOST ga e a ea, WL. Hence, each no malized MOST capaci ance C0 ij =Cij/(W L)is conside ed equal o all ansis o s o a speci ic wid h ange. Because C0 ij a e also dependen on he in e sion zone, he cu e C0 ij e sus iis used. Finally he noise cons an s ha e o be known. In his wo k we ha e conside ed hese wo cons an s: a) he excess noise ac o λo he whi e noise [5], and b) he licke noise cons an KF(o K0 , i i is di ided by he MOS no malized oxide capaci ance C0 ox). The gm/ID,gds/IDand C0 ij e sus icu es a y only sligh ly wi h MOST wid h and leng h [3]; his change is only non-negligible in e y na ow de ices. Fig. 1(b) shows, o a 100 nm nMOS ansis o , and ou wid hs W={360 nm, 3.6µm, 36 µm, 360 µm}, he simula ed esul s o he cu es o gm/ID and gds/ID e sus i. Fo his echnology, he sp ead o he cu es is almos impe cep ible. Because o he sligh a ia ion in he cu es o such a la ge wid h ange, he me hodology p esen ed he e succeeds. In his pape , a semi-empi ical MOS model is u ilized o desc ibe he MOST because i conside s he second and highe o de e ec s o nanome e echnologies, and i is easily ob ained by ex ac ing MOS cha ac e is ics ia DC simula ion. The use o analy ical compac models, such as EKV [5], ACM [6] o PSP [16], ha e been disca ded because he i ing o pa ame e s is e y ime consuming; howe e , i p ope ly se , hese models can also be used. To acqui e he equi ed cha ac e is ics cu es o his semi-empi ical model, a e y simple scheme is u ilized: ansis o ga e and d ain nodes a e connec ed o Oc obe 29, 2013 DRAFT 6 a DC ol age sou ce, while sou ce and bulk nodes a e connec ed ei he o g ound (nMOS ansis o ) o o he supply ol age (pMOS ansis o ). Then, he ga e ol age VGis swep ex ac ing ID,gm,gds and C0 ij. The d ain ol age is se a ound i s expec ed DC alue in he a ge ci cui . To ge a e y comple e da ase he same simula ion should be un o a se o wid hs ( o example, he se chosen o Fig. 1), when a ixed ansis o leng h alue is used. O he wise, ollowing he same idea, a small se o leng hs should be chosen. Finally, λand KF alues should be ob ained om handling MOST noise da a p o ided by he ound y o es ima ed om simula ions o measu emen s [17]. III. ANALYSIS OF PASSIVE COMPONENTS The second s ep in he me hodology is he cha ac e iza ion o passi e componen s. LC-VCOs pe - o mance is e y much dependen on hei non-ideali ies. Thei cha ac e iza ion can be done ei he by semi-empi ical models o lib a y cells p o ided by he ound y o by elec omagne ic sol e s such as ASITIC [18] o ADSTMMomen um. Elec omagne ic sol e has majo d awbacks: 1) he need o ha e he echnological da a p o ided by he ound y o ob ain accu a e desc ip ions, and 2) he high compu a ional ime spen o ob ain he solu ions. In his pape , o he sake o e iciency, we u ilize passi e elemen cells supplied by he ound y. By means o S-pa ame e analysis, we ob ain hei equi alen complex admi ance a he wo king equency, 0. A. Induc o modeling In his wo k, he di e en ial ank induc o is modeled a he oscilla ion equency as a ne wo k o an equi alen induc o Lind and a pa allel pa asi ic esis o Rind. S-pa ame e analysis is applied o ex ac he pa ame e s o he model wi h he induc o in a di e en ial con igu a ion. In o de o ob ain a comple e da abase, he analysis has o be done o a la ge se o induc o s. In his wo k, he bes induc o is conside ed he one wi h he highes pa allel esis ance, since i will lead o he lowes equi ed ansconduc ance and hence consump ion, as i will be shown in Sec ion IV. Looking o biuni ocal ela ionships be ween Lind and Rind, compu a ional ou ines a e implemen ed o ind, o a pa icula induc ance alue, he nea es bes induc o . Figu e 4 displays he esul ing Rind o sweeping coil conduc o wid h o ou s anda d 90 nm CMOS p ocess and highligh s he induc o s da ase wi h he maximum esis ances. The da a in his plo show ha he highes esis ances come wi h he la ges induc ance alues. Oc obe 29, 2013 DRAFT 7 Fig. 4. Pa allel esis ance e sus induc ance alue Lind o ou induc o wid hs wwi h a common ex e nal diame e o 300 µm, a 0=2.4 GHz. The black line ep esen s he induc o s wi h he highes esis ance. B. Va ac o modeling Va ac o pa asi ic esis ance has been usually neglec ed, especially due o i s high alue compa ed wi h induc o pa asi ic esis ance. Howe e , on-chip coils ha e imp o ed and i is possible o ha e a a ac o conduc ance compa able wi h induc o conduc ance. The e o e, a ac o pa asi ic esis ance ex ac ion by simula ions is now necessa y, in o de o check whe he i mus be conside ed in he design. Fo he accumula ion nMOS a ac o s used in he design p esen ed in Sec ion VI, he maximum alue o g a o e he a ac o con ol ol age ange is app oxima ely 70 µS; so a ac o conduc ance can be igno ed compa ed o he conduc ances o he o he VCO componen s. IV. VCO MODELING The LC-VCO opology used in his wo k is depic ed in Fig. 5. I shows a c oss-coupled complemen a y VCO wi h i s LC ank, biased wi h a pMOS cu en mi o , which d i es he Ibias cu en o he LC- VCO. This pMOS s uc u e is used o i s be e licke noise pe o mance wi h espec o an nMOS one wi h he same size. C oss-coupled ansis o s p o ide he needed nega i e eedback and a pMOS-nMOS complemen a y s uc u e inc eases VCO ansconduc ance while consuming he same quiescen d ain cu en , ID, wi h Ibias = 2 ·ID. A small-signal model o he LC-VCO o Fig. 5 is displayed in Fig. 6(a) join ly wi h i s simpli ied model in Fig. 6(b). I comp ises he equi alen induc ance o he di e en ial induc o Lind and he equi alen capaci ance o he a ac o s C a , bo h calcula ed a he oscilla ion equency 0; he equi alen pa asi ic capaci ances o he nMOS and pMOS ansis o s CnMOS and CpMOS; and he load capaci ance Oc obe 29, 2013 DRAFT 8 Fig. 5. C oss coupled complemen a y LC-VCO. Cload ep esen s he di e en ial capaci i e load a he ou pu o he VCO. Cload. In his pape , he nMOS and pMOS sizing is done in o de o ma ch he pMOS and nMOS ansconduc ances, gm,p and gm,n, i.e gm,n =gm,p =gm. Conside ing, espec i ely, C ank and g ank as he equi alen capaci ance and conduc ance o he VCO ank, he well-known oscilla ion equency and oscilla ion condi ion exp essions a e, espec i ely 0=1 2π√LindC ank (1) and g ank ≤gm,p 2+gm,n 2=gm(2) whe e C ank =C a +CpMOS +CnMOS 2+Cload (3) and g ank =gind +g a +gds,p 2+gds,n 2(4) whe e gds,n and gds,p a e he ou pu conduc ances o he nMOS and pMOS ansis o s; gind = 1/Rind and g a a e he pa asi ic conduc ances o he induc o and a ac o , espec i ely. Oc obe 29, 2013 DRAFT 9 Fig. 6. Small signal LC-VCO model: (a) a comple e model and (b) a educed model. C ank and g ank a e, espec i ely, he VCO equi alen capaci ance and conduc ance. Conside ing he i e capaci ance model o he MOS ansis o , he equi alen c oss-coupled ansis o capaci ance CMOS, alid bo h o he nMOS and pMOS ansis o s, is CMOS = 4Cgd + (Cgs +Cgb +Cdb +Cds).(5) Due o he expec ed echnology pa ame e a ia ions, a sa e y ma gin ac o kosc -usually called oscilla ion ac o - is u ilized in (2) o ans o m he inequali y o gm=kosc g ank (6) whe e kosc is gene ally in he ange o 1.5 o 3. The MOST in insic gain Ai, de ined as he gain o a common sou ce ansis o ampli ie loaded by an ideal cu en sou ce [2], is Ai=gm/gds = (gm/ID)/(gds/ID). Since g a is conside ed negligible wi h espec o gind and gds, (4) is ans o med in o g ank ∼ =gind +1 2gm,p Ai,p +gm,n Ai,n  =gind +gm 21 Ai,p +1 Ai,n .(7) Oc obe 29, 2013 DRAFT 16 VII. EXPERIMENTAL RESULTS The cha ac e is ics o he VCO we e measu ed on die using a mic op obe s a ion. To measu e i s spec um and phase noise he Agilen Spec um Analyze E4440A was employed. A se o phase noise measu emen s has been done o he ab ica ed chip. Un o una ely, he bu e does no wo k p ope ly and in e e es wi h he VCO beha iou , so necessa y he measu emen s we e done wi h he ou pu bu e swi ched o . Figu e 13 displays he a ia ion o 0wi h con ol ol age Vcon ol. In he inse o Fig. 13, i is shown he VCO spec um o a Vcon ol = 0V. The minimum bias cu en whe e a clean spec um wi hou in e e e s is ob ained was ID=220 µA. Fo his cu en , he phase noise e sus he o se equency, wi h he ca ie a 2.16 GHz (Vcon ol = 0V) is shown in Fig. 14. The phase noise a 400 kHz om he ca ie is -106.2 dBc/Hz. The measu ed licke co ne equency c,1/ 3is 203 kHz, whe eas he simula ed licke co ne equency, shown in Table I, is 72 kHz. This ise in c,1/ 3 espec o he simula ed da a o P4, happens because Vou is dis o ed when he bu e is u ned o . Γa ises o app oxima ely 0.4, and he compu ed c,1/ 3is 257 kHz, e y nea he measu ed da a. The cu en IDwas also swep o 310 µA and a se o phase noise measu emen s a 400 kHz om he ca ie we e pe o med ( o y measu emen s o Lwe e aken o each cu en alue), as depic ed in Fig. 15, conside ing again a ca ie equency a ound 2.16 GHz. The heo e ical cu e o (11) is supe imposed wi h expe imen al da a, conside ing α= 0.65,kosc = 3 and γ= 0.55. The i ed model is ex ended up o he nominal IDcu en o 165 µA, ob aining an ex apola ed phase noise alue o -104.6 dBc/Hz. Good ag eemen exis s be ween model, simula ions and measu emen s. The minimum measu ed IDwhe e he VCO wo ks, o h ee samples’ a e age, is 62.5 µA; 13.5% highe han he expec ed alue o 52 µA ob ained om he design low. The ou pu ol age when he bu e is swi ched on, o Ibias=440 µA is 630 mV, a bi lowe han expec ed. Table II compa es he pe o mance o he designed LC-VCO in mode a e in e sion wi h ha o some p io wo ks, whe e he well known igu e-o -me i (FoM) o he VCO de ined in [22] is used. Ou VCO is well posi ioned conside ing o he simila designs, as only he second one has a be e FoM. Howe e he la e occupies mo e a ea han ou design because i uses wo on-chip induc o s, which inc eases he ank quali y ac o and educes he phase noise. VIII. CONCLUSIONS In his pape , an RF LC-VCO design me hodology o nanome e echnologies based on he gm/ID echnique has been p esen ed. The me hodology p oposed enables a conside able design ime educ ion Oc obe 29, 2013 DRAFT 17 TABLE II PERFORMANCE COMPARISON OF RECENTLY PUBLISHED LC-VCOS. VCO Tech. 0∆ Powe LFoM (nm) (GHz) (MHz) (mW) (dBc/Hz) (dB) [23] 180 2.2 1 5.17 -119 179 [13] 180 2.645 0.4 0.63 -106.4 184.8 [15] 180 2.5 1 1.2 -103.7 171 [22] 180 1.57 1 3.06 -120 180 This wo k 90 2.16 0.4 0.53 -106.2 183.6 as li le e-design is needed. I also shows he VCO ade-o s, p o iding be o ehand a global iew o he VCO beha iou when adjus ing ce ain componen pa ame e s du ing he design. MOST, induc o and a ac o da a we e ex ac ed om Spec eRF simula ions o accu a ely and quickly model hese componen s and include ha da a in he design low. VCO modeling equa ions we e modi ied o in oduce IDand he MOS a iable gm/ID, in o de o easily see he comp omises o wo king in di e en MOS in e sion egions. Specially, Hajimi i phase noise model equa ions we e e-o de ed o exp ess hem in e ms o gm/ID. Plo s o se e al a iables in ol ed in he VCO design we e shown and comp omises wi h he in e sion egion o he selec ion o he induc o we e highligh ed. I has been shown ha designing in mode a e and weak in e sion leads o educed cu en while phase noise is inc eased; on he o he hand an inc emen o he induc o alue (and hence a inc emen in i s equi alen pa allel esis ance) con ibu es o an imp o emen in he VCO spec al pu i y. Fou designs we e simula ed o alida e he me hod. Finally, an applica ion example was implemen ed o show he use ulness o he me hod, as well as o p o e he alidi y o he phase noise model. Phase noise esul s om he calcula ions o ou design ou ines, elec ical simula ions and measu emen s a e in ag eemen . APPENDIX DEDUCTION OF PHASE NOISE EXPRESSIONS A. Exp ession o phase noise o a LC-VCO in he 1/ 2spec um egion. The exp ession o phase noise o an a bi a y oscilla o in he 1/ 2 egion o he phase noise spec um exp essed by Hajimi i in [20] is L1/ 2(∆ ) = 10 log Γ2 ms q2 max i2 n/∆ 2∆ 2!(16) Oc obe 29, 2013 DRAFT 18 whe e Γ ms is he ms alue o he impulse sensi i i y unc ion ISF de ined in [20], qmax is he maximum cha ge displacemen ac oss he capaci o in he ou pu nodes, ∆ is he equency o se espec o he oscilla ion equency 0, and i2 n/∆ is he powe spec al densi y o he noise sou ce conside ed a he ou pu nodes. To e alua e he phase noise exp ession o ou LC-VCO, le ’s ob ain he exp essions o each e m in (16). Fi s ly we calcula e he mos impo an VCO whi e noise sou ces. Fo simplici y we will conside ha no co ela ion exis s be ween hem. Supe posi ion will be applied when subs i u ing hei exp essions in (16). The gene al exp ession o MOS whi e noise is [4] i2 w,MOS ∆ = 4kBTγgdo = 4kBTγ αgm.(17) The equi alen powe spec al densi y o he wo nMOS and wo pMOS is [24] i2 w,MOSeq ∆ =1 2(i2 w,n ∆ +i2 w,p ∆ )(18) Subs i u ing (17) in (18) i2 w,MOSeq ∆ ∼ =4kBTγgm 1 21 αn +1 αp = 4kBTγ αeq .(19) The whi e noise o each c oss-coupled ansis o block due o i s equi alen d ain-sou ce conduc ance is [4] [25]: i2 w,gds ∆ = 4kBTgds 2= 4kBTgm 2Ai .(20) Conside ing bo h nMOS and pMOS equi alen conduc ances, i2 w,geq ds ∆ = 4kBTgm 21 Ai,n +1 Ai,p .(21) The whi e noise o he induc o pa allel esis ance Rind = 1/gind is, applying (9), i2 w,Lind ∆ = 4kBTgind = 4kBTgm k0 osc .(22) The whi e noise powe spec al densi y o he a ac o has been neglec ed o his deduc ion as gene ally g a gind. Oc obe 29, 2013 DRAFT 19 The equi alen whi e noise powe spec al densi y o he LC-VCO is, om equa ions, (8), (19), (21) and (22): i2 w,V CO ∆ = 4kBTgmγ αeq +1 k0 osc +1 2Ai,n +1 2Ai,p  = 4kBTgmγ αeq +1 kosc = 4kBTgmλ. (23) Besides, qmax =C ankVou , whe e C ank is he equi alen capaci ance a he ou pu nodes, exp essed as: C ank =1 4π2 2 0Lind =Q 2π 0R ank (24) Then, om (10) and (24), qmax is qmax =8 π IDQ (2π 0)=2IDR ank (π3) 2 0Lind .(25) Finally, subs i u ing (23) and (25) in (16), conside ing Γ ms ≈0.5due o he symme y cha ac e is ics o his VCO, and eo de ing he e ms, we ob ain L1/ 2(∆ ) = 10 log kBTπ2 82λ1 Q2 gm ID 1 ID 2 0 ∆ 2!(26) B. Exp ession o phase noise o a LC-VCO in he 1/ 3spec um egion. F om [20], he ollowing is he gene al exp ession o he phase nose in he 1/ 3po ion o he phase noise spec um L(∆ )1/ 3= 10 log Γ2 a 8q2 max i21/ /∆ ∆ 2!(27) Conside ing ha only he MOS ansis o s injec s licke noise, he o al powe spec al densi y o he licke noise sou ces is i2 1/ ∆ =1 2 i2 1/ ,n ∆ +i2 1/ ,p ∆ ! =1 2K0 F,ng2 m WnL+K0 F,pg2 m WpL1 (28) Equa ions (27) oge he wi h (25) and (28) esul s in he ollowing exp ession o phase noise in he 1/ 3 zone in e ms o gm/ID: L1/ 3(∆ ) = 10 log Γ2 a 8 π2 82 1 L K0 F,n Wn +K0 F,p Wp! 1 Q2 gm ID!2 2 0 ∆ 3!(29) Oc obe 29, 2013 DRAFT 20 C. Co ne equency o MOST exp essed as a unc ion o gm/IDand i. The co ne equency o a MOST cis ob ained equaling he exp essions o whi e noise and licke noise, esul ing in: c=K0 F 4kBT α γ gm ID ID W/L 1 L2=K0 F 4kBT α γ gm ID i1 L2(30) D. Flicke co ne equency o he VCO phase noise exp essed as a unc ion o gm/IDand i. The licke co ne equency o he VCO phase noise, ob ained when making equal he phase noise exp essions a whi e noise and licke zones -(26) and (29), espec i ely-, esul s c,1/ 3=k0i2 w,n c,n +i2 w,p c,p i2 w,n +i2 w,p =k0 c,eq.(31) whe e k0=Γa 2Γ ms 2 . REFERENCES [1] D. Leenae s, J. an de Tang, and C. S. Vauche , Ci cui Design o RF T anscei e s, 1s ed. Sp inge , 2001. [2] F. Sil ei a, D. Fland e, and P. G. A. Jespe s, “A gm/IDbased me hodology o he design o CMOS analog ci cui s and i s applica ions o he syn hesis o a silicon-on-insula o mic opowe OTA,” IEEE Jou nal o Solid-S a e Ci cui s, ol. 31, no. 9, pp. 1314–1319, Sep. 1996. [3] P. G. Jespe s, The gm/IDMe hodology, a sizing ool o low- ol age analog CMOS Ci cui s. Sp inge , 2010. [4] Y. Tsi idis, Ope a ion and Modelling o he MOS T ansis o , 2nd ed. Ox o d Uni e si y P ess, 2000. [5] C. Enz and E. Vi oz, Cha ge-based MOS ansis o modeling. John Wiley and Sons, 2006. [6] A.Cunha, M. C. Schneide , and C. Galup-Mon o o, “An MOS ansis o model o analog ci cui design,” IEEE Jou nal o Solid-S a e Ci cui s, ol. 33, no. 10, pp. 1510–1519, Oc . 1998. [7] C. Galup-Mon o o, M. C. Schneide , and A. A. Cunha, “A cu en -based MOSFET model o in eg a ed ci cui design,” in Low Vol age/Low Powe In eg a ed Ci cui s and Sys ems, E. Snchez-Sinencio and A. And eou, Eds. Pisca away, NJ: IEEE P ess, 1999, ch. 2, pp. 7–55. [8] A.-S. Po e , T. Melly, D. Py hon, C. C. Enz, and E. A. Vi oz, “An ul alow -powe UHF anscei e in eg a ed in a s anda d digi al CMOS p ocess: A chi ec u e and ecei e ,” IEEE Jou nal o Solid-S a e Ci cui s, ol. 36, no. 3, pp. 452–464, Ma . 2001. [9] T. Melly, A.-S. Po e , C. C. Enz, and E. A. Vi oz, “An ul alow -powe UHF anscei e in eg a ed in a s anda d digi al CMOS p ocess: T ansmi e ,” IEEE Jou nal o Solid-S a e Ci cui s, ol. 36, no. 3, pp. 467–472, Ma . 2001. [10] J. Ramos and e al, “90nm RF CMOS echnology o low-powe 900MHz applica ions,” P oceeding o he 34 h Eu opean Solid-S a e De ice Resea ch con e ence ESSDERC 2004, pp. 329–332, Sep. 2004. [11] L. Ba boni, R. Fio elli, and F. Sil ei a, “A ool o design explo a ion and powe op imiza ion o CMOS RF ci cui blocks,” IEEE In e na ional Symposium on Ci cui s and Sys ems ISCAS’06, May 2006. [12] R. Fio elli, E. Pe al´ ıas, and F. Sil ei a, “Phase noise - consump ion ade-o in low powe RF-LC-VCO design in mic o and nanome ic echnologies,” in P oceedings o he 22 h Symposium on In eg a ed Ci cui s and Sys ems Design (SBCCI). Na al, B azil: ACM, Se 2009. Oc obe 29, 2013 DRAFT 21 [13] H. Lee and S. Mohammadi, “A sub h eshold low phase noise CMOS LC VCO o ul a low powe applica ions,” IEEE Mic owa e and Wi eless Componen Le e s, ol. 17, no. 11, pp. 796–799, No . 2007. [14] H.-H. Hsieh and L.-H. Lu, “Design o ul a-low- ol age RF on ends wi h complemen a y cu en - eused a chi ec u es,” IEEE T ansac ions on Mic owa e Theo y and Techniques, ol. 55, no. 7, pp. 1445–1458, Jul. 2007. [15] B. Pe umana, S. Chak abo y, C.-H. Lee, and J. Laska , “A low-powe ully monoli hic sub h eshold CMOS ecei e wi h in eg a ed LO gene a ion o 2.4 GHz wi eless PAN applica ions,” IEEE Jou nal o Solid-S a e Ci cui s, ol. 43, no. 10, pp. 2229–2238, Oc 2008. [16] G. Gildenbla , X. Li, W.Wu, H. Wang, A. Jha, R. an Lange elde, G. Smi , A. Schol en, and D. Klaassen, “PSP: An ad anced su ace-po en ial-based MOSFET model o ci cui simula ion,” IEEE T ansac ions on Elec on De ices, ol. 53, no. 9, pp. 1979–1993, Sep. 2006. [17] M. Manghisoni, L. Ra i, V. Re, V. Speziali, and G. T a e si, “Noise cha ac e iza ion o 130 nm and 90 nm CMOS echnologies o analog on -end elec onics,” in 2006 IEEE Nuclea Science Symposium Con e ence Reco d., 2006, pp. 214–218. [18] A. M. Niknejad, “Analysis o Si induc o s and ans o me s o IC’s (ASITIC),” 2000, h p:// ic.eecs.be keley.edu/ nikne- jad/asi ic.h ml. [19] A. Hajimi i and T. H. Lee, “Design issues in CMOS di e en ial LC oscilla o s,” IEEE Jou nal o Solid-S a e Ci cui s, ol. 34, no. 5, pp. 717–724, 1999. [20] A. Hajimi i and T. Lee, “A gene al heo y o phase noise in elec ical oscilla o s,” IEEE Jou nal o Solid-S a e Ci cui s, ol. 33, no. 2, pp. 179–194, Feb. 1998. [21] D. Leeson, “A simple model o eedback oscilla o noise spec um,” P oceedings o he IEEE, ol. 54, pp. 329–330, Feb. 1966. [22] K.-G. Pa k, C.-Y. Jeong, J.-W. Pa k, J.-W. Lee, J.-G. Jo, , and C. Yoo, “Cu en eusing VCO and di ide-by- wo equency di ide o quad a u e LO gene a ion,” IEEE Mic owa e and Wi eless Componen s Le e s, ol. 18, no. 6, pp. 413–415, Jun. 2008. [23] L. L. K. Leung and H. C. Luong, “A 1 V 9.7 mW CMOS equency syn hesize o IEEE 802.11a anscei e s,” IEEE T ansac ions on Mic owa e Theo y and Techniques, ol. 56, no. 1, pp. 39–48, Jan. 2008. [24] A. Hajimi i, T ade-o s in Analog Ci cui Design. Kluwe Academic Publishe s, 2002, ch. T ade o s in oscilla o phase noise, pp. 551–585. [25] BSIM Resea ch G oup, “BSIM3 3 and BSIM4 MOS Model,” 2008, www-de ice.eecs.be keley.edu/ bsim3/bsim4.h ml. Ra aella Fio elli Ra aella Fio elli (S’05) was bo n in Mon e ideo, U uguay in 1978. She ecei ed he B.Sc. and M.Sc. deg ees in Elec ical Enginee ing om he Uni e sidad de la Rep´ ublica, Mon e ideo, U uguay, in 2002 and 2005 espec i ely. She is cu en ly wo king owa ds he doc o al deg ee in elec ical enginee ing. In 2003 she joined he Elec ical Enginee ing Ins i u e o he Uni e sidad de la Rep´ ublica, U uguay. F om 2009 she is wo king in he IMSE-CNM o Se ille, Spain, wi h a MAE-AECIC Spanish go e nmen g an . He cu en esea ch includes he implemen a ion o design me hodologies o low powe RF blocks and BIST es in RF. Oc obe 29, 2013 DRAFT 22 Edua do Pe alas Edua do J. Pe al´ ıas ecei ed he Ph.D. deg ee om he Uni e si y o Se ille, (Spain) in 1999. Since 2001, he has been wi h he Ins i u o de Mic oelec ´ onica de Se illa (IMSE-CNM-CSIC), whe e he is cu en ly a Tenu ed Scien is . His main esea ch in e es s ha e been in he a eas o Mixed Design wi h emphasis on Analog- o-Digi al con e e s, Tes and Design o Tes abili y o Analog and Mixed-Signal Ci cui s, and S a is ical Beha io al Modeling. Fe nando Sil ei a Fe nando Sil ei a (S’89- M’90- SM’03) ecei ed he Elec ical Enginee ing deg ee om Uni e sidad de la Rep´ ublica, U uguay in 1990 and he MSc. and PhD deg ee in Mic oelec onics om Uni e si ` e ca holique de Lou ain, Belgium in, espec i ely, 1995 and 2002. He is cu en ly P o esso a he Elec ical Enginee ing Depa men o he School o Enginee ing o Uni e sidad de la Rep´ ublica, U uguay. His esea ch in e es s a e in design o ul a low-powe analog and RF in eg a ed ci cui s and sys ems, in pa icula wi h biomedical applica ion. In his ield, he is co-au ho o one book and many echnical a icles. He has had mul iple indus ial ac i i ies wi h CCC Medical De ices and NanoWa ICs, including leading he design o an ASIC o implan able pacemake s and designing analog ci cui modules o implan able de ices o a ious companies wo ldwide. Oc obe 29, 2013 DRAFT 23 Fig. 10. L1/ 2in dBc/Hz mapped e sus gm/IDand Lind. The ex -box displays he cha ac e is ics and pa ame e s o he LC-VCO associa ed wi h he picked poin (P4 in his example). Fig. 11. Phase noise Spec eRF simula ions o designs P1,P2,P3 and P4. Oc obe 29, 2013 DRAFT 24 Fig. 12. Layou and mic opho og aph o he ab ica ed VCO. Fig. 13. Ca ie equency 0 e sus Vcon ol and ou pu spec um (inse ) a Vcon ol = 0 wi h he bu e swi ched o . Oc obe 29, 2013 DRAFT 25 Fig. 14. Lwi h he VCO biased wi h Ibias = 2 ·ID= 440µA and 0= 2.1639GHz (bu e swi ched o ). 1/ 2and 1/ 3 slopes a e shown as well as he es ima ed licke co ne c,1/ 3. Fig. 15. Phase noise measu ed and es ima ed by (11) sweeping only ID. Oc obe 29, 2013 DRAFT