In e ne o Things 23 (2023) 100874
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IRIS: An embedded secu e boo o IoT de ices
G. Cano-Qui eu∗, P. Ruiz-de-Cla ijo-Vazquez, M.J. Bellido, J. Juan-Chico,
J. Viejo-Co es
Depa amen o de Tecnologia Elec onica, Uni e sidad de Se illa, A . Reina Me cedes s/n Se illa, 41012, Andalucia, Spain
ARTICLE INFO
Da ase link:h ps://gi hub.com/ge mancq/EL
UKS/ ee/main/examples/boo loade
Keywo ds:
Field p og ammable ga e a ay
Secu e boo
In e ne o Things (IoT)
Boo loade
Ha dwa e
Embedded de ice
ABSTRACT
This s udy p oposes a ha dwa e secu e boo solu ion, an ins an e ie al in o ma ion sys em
(IRIS) ha is sui able o in eg a ing In e ne o Things (IoT) de ices. IRIS can boo a
Linux ke nel image p e-s o es in emo able media and comp ises a da a e i ie secu ing he
au hen ici y, in eg i y, and con iden iali y o he boo p ocess. IRIS is ully de eloped as a
ha dwa e module and he esul s e eal sho boo -up imes and a small ha dwa e oo p in
when implemen ed on ield p og ammable ga e a ay chips. In addi ion, IRIS is an open-sou ce
gene ic solu ion ha can be adap ed o mul iple a chi ec u es and includes a c yp o-co e called
E-LUKS ha can be used ou side he boo -loading p ocess o add con iden iali y, in eg i y, and
au hen ici y o da a s o ed on o -chip s o age like a lash de ice.
IRIS shows a educ ion in lookup ables oo p in when compa ed o o he IoT solu ions
consuming om 90% o 750% less esou ces and only sligh ly g ea e , a ound 30%, wi h
solu ions ha only co e au hen ica ion and in eg i y.
1. In oduc ion
The signi ican g ow h in connec ed In e ne o Things (IoT) de ices in ecen yea s inc eased a acks on hese ypes o de ices.
Secu i y is a p io i y in en i onmen s whe e hese de ices a e pa o c i ical sys ems o deal wi h p i a e da a. Secu i y mus be
add essed a all le els, om he ha dwa e o he ull so wa e s ack. The link be ween ha dwa e and so wa e is he boo loade
which is he i s piece o so wa e execu ed on he de ice. The e o e, o secu e a de ice, he boo loade is a c i ical pa o be
secu ed in he so wa e s ack.
The e is a wide ange o IoT de ices ha can be b oadly classi ied in o wo ypes depending on he unde lying ha dwa e: a
mic ocon olle uni o a sys em on chip (SoC). Bo h include a boo loade , bu he so wa e execu ed in each case di e s because
he o me usually execu es s andalone so wa e, while he la e s a s an ope a ing sys em (OS). In he las scena io, he a ge
o he boo loade is o launch he OS ke nel; howe e , i is o en impossible o e ch i in a single s age because o i s size. The
solu ion adop ed in his case is o spli he boo loading p ocess in o mul iple so wa e s ages, c ea ing a boo loade chain. The i s
s age is commonly called p eloade and is launched a e he SoC ini ializes a minimal ha dwa e se such as pe iphe als, on-chip
memo ies, debug in e aces, e c [1].
Cu en SoCs s o e he ull boo loade chain in o -chip lash memo y (on-boa d lash chip o emo able media). Hence, i can
be ampe ed wi h o al e ed wi h app op ia e ools. In his si ua ion, a acks ypically in ol e al e ing he lash con en s o change
pa s o he boo loade chain, inducing he mal unc ioning de ice o execu e malicious code. To a oid hese ypes o a acks, a
p ocedu e called secu e boo [2] aims a p o ec ing he da a and/o code in ol ed in he boo loade chain.
∗Co esponding au ho .
E-mail add ess: [email p o ec ed] (G. Cano-Qui eu).
h ps://doi.o g/10.1016/j.io .2023.100874
Recei ed 22 Decembe 2022; Recei ed in e ised o m 6 June 2023; Accep ed 6 July 2023
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Fig. 1. Gene al o e iew o he secu e boo p ocess.
The secu e boo p ocess comp ises a chain o s ages whe e he p e ious s age e i ies he nex s age be o e launching i . A
gene al o e iew is shown in Fig. 1. The componen called he oo o us (RoT) is conside ed us ed by de aul and is usually an
immu able p eloade s o ed in an on-chip ROM. Each s age a aches a diges o i s da a o be used in a e i ica ion p ocedu e un
be o e s a ing.
This e i ica ion ensu es he s age in eg i y o he boo loade chain using a hash-based message au hen ica ion code (HMAC), and
is called chain o us (CoT). In addi ion o in eg i y, au hen ica ion is achie ed by enc yp ing he diges . In addi ion, secu e boo
can also suppo con iden iali y by enc yp ing he da a o he s ages and p e en ing hem om being ead by unau ho ized use s.
In cu en IoT scena ios, mos de ices a e small and limi ed in a ailable esou ces; hence, complex boo solu ions like he
uni ied ex ensible i mwa e(UEFI) [3] canno be applied, making secu e boo on IoT de ices equi e speci ic solu ions in mos cases.
This, oge he wi h he ac ha i is p ac ical o place he RoT in immu able on-chip ha dwa e, makes cus om ha dwa e solu ions
specially sui able o secu e boo in IoT de ices.
Secu e boo implemen a ions such as hose p oposed in UEFI suppo only in eg i y and au hen ica ion, bu using he Linux
uni ied key sys em (LUKS) [4], i is possible o add con iden iali y o he boo p ocess when he Linux ke nel is used [5].
This con ibu ion p oposes a cus om secu e boo ha dwa e called an ins an e ie al in o ma ion sys em (IRIS). I is ocused
on SoC de ices wi h low oo p in s, allowing hem o boo a Linux OS secu ely. IRIS gua an ees con iden iali y, in eg i y, and
au hen ica ion when boo ing a Linux ke nel image s o ed in o -chip memo y.
The pape is o ganized as ollows. The nex sec ion summa izes he mos ele an ela ed wo k. Sec ion 3de ails he IRIS
solu ion. Sec ion 4shows he esul s o he implemen a ion on ield p og ammable ga e a ays (FPGAs), he execu ion me ics, and
compa isons wi h ela ed solu ions. Finally, he main conclusions a e summa ized in Sec ion 5.
2. Rela ed wo k
Cu en ly, mul iple secu e boo designs ha e been p oposed wi h ea u es such as au hen ica ion, con iden iali y, and in eg i y [6–
8].
These h ee ea u es a e aluable agains di e en ypes o a acks. Fo example, au hen ici y and in eg i y a e needed o alida e
he o igin o he da a and ensu e ha he da a ha e no been modi ied by a hi d pa y. These wo p ope ies can p e en a acks
agains i mwa e modi ica ions such as hose p esen ed in [9]. Rega ding con iden iali y, i is common o cus omize he boo da a
o he ke nel image o include pe sonal da a o p i a e modi ica ions ha mus be p o ec ed. Enc yp ing he da a can a oid e e se
enginee ing a acks on he i mwa e ex ac ed om he de ice [10].
In [6], a ull-ha dwa e secu e boo is p oposed o un in a p og ammable sys em-on-chip (PSoC) o suppo au hen ici y,
con iden iali y, and in eg i y. This design is di ided in o wo pa s: he p og ammable logic egion (PL Region) ha has an FPGA
and he p ocessing sys em egion (PS Region) ha has an ARM p ocesso . Secu e boo is implemen ed in he PL egion, which g an s
au hen ica ion based on he ac o y’s unique IDs om he non- ola ile memo y (NVM) and he FPGA. Con iden iali y is achie ed by
using a symme ic ciphe ha enc yp s he image, and o achie e in eg i y, i uses a hash unc ion o p ocess all he da a. Howe e ,
he c yp og aphic algo i hms included, such as AES, a e no he op imal solu ion o mid- and low- ange de ices, as is e lec ed in
he FPGA esou ces u iliza ion esul s, which a e e y high.
Ano he solu ion ele an o his pape is called ITUS; i is p esen ed in [8] and is a comple e secu e solu ion wi h mul iple
modules. One o hem is a module implemen ing a secu e boo CoT whe e each s age is signed and e i ied by a ha dwa e co e. ITUS
is es ed o e a high- ange o FPGA chips because he design has a mid- oo p in and is mainly ocused on secu i y agains quan um
compu a ion a acks. Hence, i makes an e o o enhance in eg i y using algo i hms such as he ellip ic cu e digi al signa u e o
he ex ended Me kle signa u e scheme, bu hese algo i hms a e no good app oaches o esou ce-cons ain de ices as ypically ound
in he IoT domain.
Ano he solu ion in oduced in [7] called CARE mixes ha dwa e and so wa e. The CARE design p o ides au hen ici y and
in eg i y, adding a eco e y engine ha can boo a p e-s o ed secu e image. The ha dwa e module comp ises a da a e i ie secu ing
he au hen ici y and in eg i y o an image s o ed in lash memo y. The e i ica ion p ocedu e di ides he image in o chunks wi h an
a ached signed diges . Then, he module checks he lash image chunk by chunk. Fu he mo e, he CARE design does no achie e
con iden iali y and is no a ull-ha dwa e design because only he HMAC module is implemen ed on ha dwa e.
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Fig. 2. Schema ic o he IRIS subsys em.
3. IRIS secu e boo
3.1. IRIS o e iew
IRIS is a ha dwa e subsys em ha a emp s o add secu e boo unc ionali y o IoT de ices. I can be in eg a ed in o a de ice o
p o ide con iden iali y, in eg i y, and au hen ici y o he boo p ocess. The main ea u es o IRIS a e summa ized as ollows.
•I has a low ha dwa e oo p in o esou ce-cons ained de ices.
•I is a gene ic secu e boo solu ion o embedded de ices, and i is easy o adap o di e en p ocesso s and buses.
•The design has an open-sou ce license o easie in eg a ion and e-usabili y in o he p ojec s.
When he IRIS subsys em is in eg a ed in o an SoC, only a ew pa s mus be adap ed o he speci ic sys em: mainly he pa s
connec ing o he in e nal p ocesso bus. Once in eg a ed, he IRIS subsys em will ake con ol o he i s s eps o he boo p ocess
and e ie e a Linux ke nel image om a s o age de ice, dec yp and e i y i , and load i in o RAM such ha he p ocesso can
un i only i he e i ica ion s ep has succeeded. The enc yp ed Linux ke nel image may be s o ed in o -chip lash memo y o
emo able media.
IRIS has a modula design wi h mul iple componen s. Fig. 2 depic s a ypical SoC con igu a ion wi h he IRIS componen adap ed
o he p ocesso ’s in e nal bus and an SD ca d ac ing as emo able s o age media.
The main pa s o IRIS a e he Boo Module and he E-LUKS Module. Bo h a e eusable. Depending on he sys em bus he SoC
uses, he in e ace o he E-LUKS Module o he bus ( he E-LUKS B idge) may ha e o be adap ed as he in e nal in e ace o he bus
in he Boo Module. Rew i ing his connec ion o he sys em bus in each module (E-LUKS and Boo Module) allows IRIS o boo a
Linux ke nel s o ed in he s o age de ice. The cu en implemen a ion o IRIS uses an SD ca d as s o age media accessed by an SD
hos eade module.
The Boo Module is he main co e go e ning he boo p ocess o he sys em by aking con ol o all componen s connec ed o
he p ocesso ’s in e nal bus. The E-LUKS Module [11] suppo s da a secu i y and e i ica ion. I p o ides con iden iali y, in eg i y,
and au hen ici y o he da a s o ed in he o -chip s o age media du ing he boo p ocess, as de ailed in Sec ion 3.4.
The con iden iali y is accomplished by enc yp ing he Linux ke nel image s o ed in he ex e nal memo y (SD ca d). These
enc yp ed da a ha e a ached he esul o an HMAC unc ion, which is enc yp ed wi h he same key used o he da a. This ensu es
da a in eg i y and au hen ici y, p o ec ing he boo -up p ocess agains da a ampe ing, gene a ion, o co up ion.
The nex subsec ions will be explain he boo -up p ocedu e execu ed by IRIS. Then he wo main co es o IRIS, Boo Module and
E-LUKS,will be de ailed.
3.2. IRIS p ocedu e
The IRIS secu e boo p ocedu e s a s a e an SoC powe -on o ha d- ese . I begins wi h he Boo Module asse ing he p ocesso ’s
ese signal o ake con ol o he in e nal bus un il he secu e boo is comple ed. The boo p ocedu e equi es sec e pa ame e s o
ini ialize he E-LUKS Module. They a e p eloaded in he Boo Module, which is in cha ge o ini ializing he E-LUKS Module. These
pa ame e s a e:
•PSW: use passwo d o dec yp and e i y he E-LUKS boo pa i ion wi h a maximum size o 80 bi s.
•START: a 32-bi numbe wi h he logical block o lash memo y om which he E-LUKS pa i ion s a s.
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Fig. 3. Schema ic o he Boo Module subsys em.
•INIT-BLOCK: he ela i e o se wi hin he E-LUKS pa i ion whe e he Linux ke nel image is s o ed.
•HMAC-ENABLE: a lag o ac i a e o deac i a e in eg i y and au hen ici y checks.
Once he E-LUKS Module is con igu ed, he Boo Module wai s o a esponse con aining he o al numbe o by es o he E-LUKS
pa i ion o an e o signal. An e o could occu in mul iple si ua ions:
•No alid E-LUKS heade is p esen in he pa i ion a o se START.
•The HMAC diges e i ica ion ails.
When all checks a e co ec , he E-LUKS Module eads a da a s eam om he SD ca d, dec yp s , and sends i o he Boo Module.
The Boo Module copies he da a ecei ed in o RAM and inally de-asse s he p ocesso ’s ese signal, lea ing in e nal bus con ol
o he p ocesso , which will execu e he i s s age o he boo -up p ocess.
3.3. Boo module
A ull ha dwa e module, he Boo Module, has been implemen ed o coo dina e he boo p ocess. This co e has been c ea ed
exp essly o his pu pose. This module is independen o he p ocesso and ac s as a cen al piece ha ac i a es o deac i a es he
di e en pa icipa ing modules in he boo p ocess.
A schema ic o he Boo Module is shown in Fig. 3. I has a con ol signal o ese he p ocesso (cpu_ ese ) and communica es
wi h he sys em bus o each he o he componen s. The co e o his module is i s ini e s a e machine (FSM), which, s ep by s ep,
de e mines he ac i a ion o de o he o he modules.
Fi s , he Boo Module wai s o a s a signal. Once he module has been ac i a ed, i hal s he main p ocesso ac i a ing i s ese ,
which emains ac i e un il he Boo Module inishes i s ac i i y. Once he Boo Module akes con ol, i begins o send he equi ed
pa ame e s o he E-LUKS Module: he passwo d o he enc yp ed pa i ion, he signal o enable o no he HMAC unc ion o E-LUKS
and inally in which logical block o he SD ca d begins he E-LUKS boo pa i ion. When all he da a ha e been ansmi ed h ough
he sys em bus, he Boo Module eques s chunks o da a om he boo pa i ion, which he E-LUKS Module sends back dec yp ed.
Once he da a eaches he Boo Module, i s o es i in he RAM. This eques p ocess con inues un il all da a has been copied o he
RAM. A his poin , he Boo Module deac i a es he ese o he p ocesso , inishing he boo p ocess. All his p ocess aken by he
FSM is shown in Fig. 4.
The design choice o pu he passwo d in o a sepa a e BRAM and send i o he Boo Module ins ead o s o ing i in he E-LUKS
Module is due o allowing he p ocesso o use he E-LUKS Module wi h ano he pa i ion on he same lash memo y using a di e en
passwo d, as men ioned ea lie . I makes he E-LUKS Module gene ic and i may emain a ailable o o he modules o use a e he
boo ing p ocess.
3.4. E-LUKS
E-LUKS is a ull-ha dwa e module ha suppo s he p ocess o secu e he da a in he IRIS secu e boo sys em. I has mainly
been de eloped o IoT de ices and wo ks simila ly o LUKS [4]. Howe e , while LUKS is a so wa e d i e , E-LUKS is a ha dwa e
implemen a ion.
E-LUKS p o ides con iden iali y, in eg i y, and au hen ici y o use da a s o ed in a pa i ion. This pa i ion has an unenc yp ed
space con aining he E-LUKS heade , which includes in o ma ion on he public c yp og aphic pa ame e s used. I also has slo s o
di e en use s, each wi h a unique passwo d de i ed om he mas e key used o enc yp and e i y he use da a. When a use
wan s o e ie e da a, hey mus p o ide i s use passwo d om which a candida e mas e key is gene a ed. The diges o his
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Fig. 4. Diag am o he ini e s a e machine o he Boo Module subsys em.
mas e key is compa ed o a diges o he o iginal mas e key s o ed in he pa i ion. I he candida e is co ec , he in eg i y and
au hen ici y o he use da a a e checked. I all he da a is co ec , he use can e ie e he da a.
E-LUKS is op imized o be easily in eg a ed as pa o an SoC and has some a ia ions wi h espec o he o iginal LUKS, he
mos ele an a e:
•E-LUKS includes c yp og aphic algo i hms speci ically designed o IoT de ices wi h limi ed esou ces: PRESENT [12],
SPONGENT [13] and a a ia ion o he key de i a ion unc ion (KDF) in oduced in [14].
•The KDF unc ion akes h ee pa ame e s; he pa ame e coun is used o hold he numbe o i e a ions ha mus be pe o med
be o e he KDF gene a es an ou pu . This coun pa ame e can be modi ied o add mo e secu i y agains b u e- o ce a acks.
I is assumed ha he secu i y achie ed in his way is equi alen o ha ing a key leng h o 80 + log2(𝑐𝑜𝑢𝑛𝑡).
•E-LUKS adds a new ope a ion o compu e he HMAC o he en i e enc yp ed use da a. This ope a ion ensu es da a in eg i y
and au hen ica ion , which a e essen ial o achie e a secu e boo .

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Table 1
IRIS s. egula boo loade . FPGA esou ces u iliza ion on he Xilinx A ix7 XC7A100T-1CSG324C.
Co e Slices Flip lops LUT’s
No. % No. % No. %
Regula Boo loade 215 1.35 428 0.34 584 0.92
SD hos 121 0.76 254 0.20 316 0.50
Boo Module 94 0.59 174 0.14 268 0.42
IRIS 1345 8.48 3301 2.60 3298 5.20
SD hos 108 0.68 199 0.16 306 0.48
Boo Module 90 0.57 168 0.13 243 0.38
E-LUKS 1147 7.23 2934 2.31 2749 4.34
•LUKS in e nal da a s uc u es a e op imized in E-LUKS by educing he numbe o in e nal ields and ma ching he logic block
size o he physical laye . In he cu en implemen a ion, he block size is 512 by es o ob ain a be e pe o mance on SD
ca ds.
The E-LUKS Module is no exclusi e o secu e boo ; i can also be used wi h so wa e d i e s in he OS o p o ec emo able
media pa i ions. In ac , E-LUKS was c ea ed o be able o s o e he boo da a in a sepa a e pa i ion o he i s boo ing s age, bu
i has ano he E-LUKS pa i ion on he same lash memo y wi h use da a ha he p ocesso can access o execu e a second s age
o he boo p ocess i necessa y.
4. Resul s
In his sec ion, wo ypes o esul s a e ob ained. Fi s , he u iliza ion o IRIS esou ces and boo ime pe o mance a e analyzed.
Second, he u iliza ion o IRIS co e esou ces is compa ed wi h o he solu ions in oduced in Sec ion 2. The en i e code used o
his sec ion can be accessed on he au ho ’s Gi Hub [15].
4.1. IRIS esou ces u iliza ion and boo ime pe o mance
To alida e he p oposed solu ion, IRIS has been es ed in an SoC deployed on he Digilen Nexys4-DDR p o o ype boa d, which
has a Xilinx A ix7 XC7A100T-1CSG324C FPGA chip [16]. The SoC a chi ec u e es ed co esponds o ha depic ed in Fig. 2 in
he p e ious sec ion. The SoC uses OpenRISC [17] as he p ocesso and Wishbone [18] as he sys em bus. The sys em includes a
emo able SD ca d as boo media, con aining an E-LUKS pa i ion wi h an enc yp ed embedded Linux image o 6.3 MB.
To e alua e he impac o he secu e boo ea u es on he ha dwa e esou ces needed and he boo ime pe o mance, ano he
SoC has been implemen ed wi h secu e boo unc ionali y emo ed (a egula ha dwa e boo sys em). Wi h bo h he secu e and
egula boo sys ems, he es in ol es loading he Linux image in o he RAM and launching i . Howe e , in he egula boo case,
he Boo Module e ches he Linux ke nel di ec ly om he SD hos module and loads i in o he RAM. This egula boo sys em
does no include an E-LUKS Module o any boo secu i y ea u es.
Table 1 shows he FPGA esou ces needed by egula and he secu e (IRIS) boo loade s. The o al numbe o FPGA slices,
lip- lops, and lookup- ables (LUT’s) a e included, oge he wi h he pe cen age o e e y esou ce wi h espec o he o al chip’s
a ailable esou ces. Numbe s a e also speci ied o he main componen s o he boo sys em: SD hos , Boo Module, and E-LUKS
Module (IRIS only).
The esou ces consumed by he SD hos and Boo Modules a e p ac ically he same in bo h implemen a ions. The small di e ence
is due o small a ia ions in he in e aces o he modules ha a e no exac ly he same when he E-LUKS Module is no used.
Mos esou ces in he IRIS sys em a e consumed by E-LUKS Module (be ween 80% and 90% o he o al esou ces consumed)
because o he inhe en complexi y o he c yp og aphic algo i hms implemen ed wi hin he module. Ne e heless, esou ce usage
is below 10% o he de ice’s a ailabili y, making he IRIS solu ion pe ec ly iable o he pla o m used in his SoC.
Table 2 shows he esou ces aken by he ull design. I also shows ha he o e cos o IRIS compa ed o Regula Boo loade is in
he o de o 25% mo e slices (27.14%), as is seen in he las ow o he able. This o e cos is na u al because o he implemen ed
E-LUKS Module which comp ises he c yp og aphic algo i hms. I can be conside ed ha he manu ac u ing cos s o e ASICs could
be inc eased by app oxima ely 25%. Conside ing ha he sys em is p o ided wi h sa e y du ing i s boo -up and subsequen ly he
E-LUKS Module can be used by he p ocesso , he o e cos associa ed wi h i s manu ac u e can be assumed.
Rega ding he impac o he secu e boo unc ionali y o IRIS on he boo -up ime, Table 3 summa izes he boo -up imes o he
egula boo loade , he IRIS module wi h HMAC disabled (no in eg i y o au hen ici y), and he ull IRIS module. The boo ime
o e head o he IRIS sys em compa ed o a egula boo loade is only 13% when in eg i y and au hen ici y a e disabled, e en i
he boo da a is s ill enc yp ed. The o e head is abo e 80% when he comple e IRIS unc ionali y is used and he boo p ocess is
ully secu ed.
As men ioned in he p e ious sec ion, he IRIS secu e boo suppo s di e en secu i y le els by changing he coun p e-
p og ammed pa ame e o he KDF in he E-LUKS Module. This le el o secu i y is no iced in he obus ness o bi s o he sys em,
which indica es on how much ime is equi ed agains b u e- o ce a acks. The e o e, he inc ease in bi s is only ele an i he
bes a ack agains he sys em is b u e- o ce a acks, which is he case wi h PRESENT, one o he algo i hms ecommended o
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G. Cano-Qui eu e al.
Table 2
IRIS s. egula boo loade . FPGA esou ces u iliza ion on he Xilinx A ix7 XC7A100T-1CSG324C, En i e SoC
implemen a ion.
Co e Slices Flip lops LUT’s
No. % No. % No. %
Regula Boo loade SoC 3282 20.71 6527 5.15 9293 14.66
OpenRISC 1411 8.90 2020 1.59 4233 6.68
DDR Con olle 1546 9.75 3714 2.93 4041 6.37
Regula Boo loade 215 1.35 428 0.34 584 0.92
IRIS SoC 4173 26.33 9378 7.40 11539 18.20
OpenRISC 1251 7.89 1938 1.53 3666 5.78
DDR Con olle 1526 9.63 3714 2.93 4064 6.41
IRIS 1345 8.48 3301 2.60 3298 5.20
Inc emen o IRIS 891 +27.14 2851 +43.7 2246 +24.15
Table 3
Boo -up ime on he Xilinx A ix7 XC7A100T-1CSG324C.
Co e Boo up ime (seconds) Pe cen (%)
Regula Boo loade 4.51 100
IRIS (HMAC disabled) 5.11 113
IRIS 8.19 181
Fig. 5. Execu ion esul s o IRIS o boo a Linux Image wi h di e en alues o he E-LUKS coun pa ame e .
Table 4
Robus ness o IRIS wi h di e en coun alues
agains b u e- o ce a acks.
log2(coun alue)Robus ness (bi s)
1 80
4 84
8 88
12 92
16 96
20 100
IoT applica ions [19]. Table 4 shows he obus ness o IRIS agains b u e- o ce a acks wi h di e en alues o coun . Howe e ,
inc easing he coun alue uns agains he pe o mance o IRIS, as shown in Fig. 5 which shows he boo -up ime o di e en
alues coun . I is app eciable ha he boo -up ime g ea ly inc eases o alues o coun equal o 220 and abo e. Hence, a g ea
balance o pe o mance and secu i y o he sys em is a obus ness o 96 bi s wi h a coun alue o 216. Rega ding s anda d alues
o he coun in he speci ica ions o LUKS, a minimum o 1000 is sugges ed o he alue coun [4].
4.2. Compa ison wi h o he solu ions
I is also in e es ing o compa e he u iliza ion o IRIS esou ces wi h he solu ions p esen ed in Sec ion 2: CARE [7], ITUS [8],
and S ei e al. [6].
Bo h S ei e al. and ITUS include au hen ici y and in eg i y, bu S ei e al. also add con iden iali y, jus as IRIS. In con as ,
CARE is a mixed ha dwa e-so wa e solu ion in which only he HMAC algo i hm (used o au hen ici y and in eg i y) is implemen ed
on ha dwa e.
In e ne o Things 23 (2023) 100874
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G. Cano-Qui eu e al.
Table 5
Resou ces u iliza ion o IoT secu e boo solu ions.
Wo k Flip lops LUT’s FPGA amily
No. % No. %
S ei e al. [6] 5934 16.9 6783 38.5 Zynq
IRIS 3269 9.29 3319 18.86 Zynq
ITUS [8] 6722 1.65 27170 13.33 Kin ex-7
IRIS 3299 0.81 3334 1.64 Kin ex-7
C y oCo e CARE [7] 1715 1.35 2591 4.08 A ix-7
IRIS 3365 2.65 3390 5.35 A ix-7
Table 5 con ains he compa ison o esou ce u iliza ion be ween he abo e-men ioned solu ions and IRIS on he pla o ms
epo ed by he au ho s: Zynq, Kin ex-7, and A ix-7 FPGA amilies o S ei e al., ITUS and CARE espec i ely. Compa ed o
S ei e al. and ITUS, IRIS equi es app oxima ely hal he esou ces and many ewe LUTs han ITUS e en i IRIS implemen s
au hen ici y, which is absen in ITUS. This shows he bene i s o using c yp og aphic algo i hms speci ic o IoT applica ions.
When compa ing IRIS wi h he CARE C yp oCo e, he esul s show ha he IRIS equi emen s a e only sligh ly la ge han hose
o CARE, which is no a su p ise because IRIS is a ully secu e boo loade ha includes a KDF, a block ciphe and an HMAC while
he CARE C yp oCo e only includes an HMAC.
5. Conclusions
The IRIS sys em in oduced he e is a ull ha dwa e secu e boo solu ion o IoT de ices on FPGA wi h a low oo p in . IRIS
p o ides con iden iali y, in eg i y, and au hen ici y o he boo p ocess. I emains a ailable a un ime a e he boo p ocess and can
be used o access secu ed da a on emo able media. IRIS is an open-sou ce design and can be adap ed o di e en SoC a chi ec u es
by ew i ing he glue logic o he in e nal bus.
The esul s show li le impac on he boo -up ime, especially i only da a con iden iali y is equi ed. Compa isons agains simila
solu ions e eal signi ican imp o emen s in ha dwa e esou ce equi emen s e en when compa ed o solu ions ha do no suppo
all aspec s o a secu e boo p ocess, making IRIS a aluable op ion o secu e boo in IoT de ices.
As u u e wo ks o his pape , some imp o emen s a e cu en ly being de eloped o issue p oblems ha may appea . One o
hese imp o emen s is o add mo e c yp og aphic algo i hms used in IRIS, which a e cu en ly being s udied, pa icula ly block
ciphe s men ioned in [19] alongside PRESENT: LEA and CLEFIA. In addi ion, a eco e y mode o he sys em in case o ampe ing
da a, such as implemen ing a cen al se e o communica e and upload a sa e ke nel image. Howe e , o c ea e his cen al se e ,
i is equi ed o implemen asymme ic c yp og aphy o ensu e secu e communica ion wi h he se e . Mo eo e , o inc ease he
sys em’s secu i y, i is impo an o ensu e some mechanism o p o ide each FPGA wi h i s passwo d.
Decla a ion o compe ing in e es
The au ho s decla e ha hey ha e no known compe ing inancial in e es s o pe sonal ela ionships ha could ha e appea ed
o in luence he wo k epo ed in his pape .
Da a a ailabili y
The code is p o ided in h ps://gi hub.com/ge mancq/ELUKS/ ee/main/examples/boo loade .
Acknowledgmen s
This wo k was pa ially suppo ed by he Minis e io de Indus ia 𝑦Compe i i idad o Spain unde p ojec TIN2017-89951-P
(Boo TimeIoT) and he Eu opean Regional De elopmen Fund (ERDF). The au ho , G. Cano-Qui eu, is inancially suppo ed by he
VI-PPITUS.
Re e ences
[1] C. Gu, Powe on and boo loade , in: Building Embedded Sys ems: P og ammable Ha dwa e, A P ess, Be keley, CA, 2016, pp. 5–25, h p://dx.doi.o g/10.
1007/978-1-4842-1919-5_2.
[2] K. Die ich, J. Win e , Secu e boo e isi ed, in: 2008 he 9 h In e na ional Con e ence o Young Compu e Scien is s, 2008, pp. 2360–2365, h p:
//dx.doi.o g/10.1109/ICYCS.2008.535.
[3] Speci ica ions |Uni ied ex ensible i mwa e in e ace o um, 2022, URL: h ps://ue i.o g/speci ica ions.
[4] C. F uhwi h, M. B oz, LUKS1 on-disk o ma speci ica ion, 2018, URL: h ps://mi o s.edge.ke nel.o g/pub/linux/u ils/c yp se up/LUKS_docs/on-disk-
o ma .pd .
[5] J. Hagl, O. Mann, M. Pi ke , Secu ing he linux boo p ocess: F om s a o inish, in: ICISSP, 2021, pp. 604–610.
[6] F.-J. S ei , F. F i z, A. Beche , S. Wilde mann, S. We ne , M. Schmid -Ko h, M. Pschyklenk, J. Teich, Secu e boo om non- ola ile memo y o
p og ammable soc a chi ec u es, in: 2020 IEEE In e na ional Symposium on Ha dwa e O ien ed Secu i y and T us , HOST, 2020, pp. 102–110, h p:
//dx.doi.o g/10.1109/HOST45689.2020.9300126.
In e ne o Things 23 (2023) 100874
9
G. Cano-Qui eu e al.
[7] A. Da e, N. Bane jee, C. Pa el, CARE: Ligh weigh a ack esilien secu e boo a chi ec u e wi h onboa d eco e y o RISC-V based SOC, in: 2021 22nd
In e na ional Symposium on Quali y Elec onic Design, ISQED, 2021, pp. 516–521, h p://dx.doi.o g/10.1109/ISQED51717.2021.9424322.
[8] V.B. Kuma , S. Deb, N. Gup a, S. Bhasin, J. Haj-Yahya, A. Cha opadhyay, A. Mendelson, Towa ds designing a secu e RISC-V sys em-on-chip: ITUS, J
Ha dw. Sys . Secu . 4 (4) (2020) 329–342.
[9] Z. Ling, J. Luo, Y. Xu, C. Gao, K. Wu, X. Fu, Secu i y ulne abili ies o in e ne o hings: A case s udy o he sma plug sys em, IEEE In e ne Things J.
4 (6) (2017) 1899–1909, h p://dx.doi.o g/10.1109/JIOT.2017.2707465.
[10] O. Shwa z, Y. Ma ho , M. Bohadana, Y. Elo ici, Y. O en, Re e se enginee ing IoT de ices: E ec i e echniques and me hods, IEEE In e ne Things J. 5
(6) (2018) 4965–4976, h p://dx.doi.o g/10.1109/JIOT.2018.2875240.
[11] G. Cano-Qui eu, P.R. de Cla ijo-Vazquez, M. Bellido-Diaz, J. Juan-Chico, J. Viejo-Co es, D. Gue e o-Ma os, E. Os ua-A anguena, Embedded LUKS
(E-LUKS): a ha dwa e solu ion o IoT secu i y, Elec onics 10 (23) (2021) 1–22, h p://dx.doi.o g/10.3390/elec onics10233036.
[12] A. Bogdano , L.R. Knudsen, G. Leande , C. Paa , A. Poschmann, M.J.B. Robshaw, Y. Seu in, C. Vikkelsoe, PRESENT: An ul a-ligh weigh block ciphe , in:
P. Paillie , I. Ve bauwhede (Eds.), C yp og aphic Ha dwa e and Embedded Sys ems - CHES 2007, Sp inge Be lin Heidelbe g, Be lin, Heidelbe g, 2007,
pp. 450–466.
[13] A. Bogdano , M. Kneže ić, G. Leande , D. Toz, K. Va ıcı, I. Ve bauwhede, spongen : A ligh weigh hash unc ion, in: B. P eneel, T. Takagi (Eds.),
C yp og aphic Ha dwa e and Embedded Sys ems – CHES 2011, Sp inge Be lin Heidelbe g, Be lin, Heidelbe g, 2011, pp. 312–325.
[14] F.F. Yao, Y.L. Yin, Design and analysis o passwo d-based key de i a ion unc ions, in: A. Menezes (Ed.), Topics in C yp ology – CT-RSA 2005, Sp inge
Be lin Heidelbe g, Be lin, Heidelbe g, 2005, pp. 245–261.
[15] Gi Hub - ge mancq/ELUKS/examples/boo loade , 2022, URL: h ps://gi hub.com/ge mancq/ELUKS/ ee/main/examples/boo loade .
[16] Xilinx, 7 Se ies FPGAs da a shee : O e iew (DS180), 180, 2010, pp. 1–18, URL: www.xilinx.com.
[17] OpenRISC - OpenRISC, 2022, URL: h ps://open isc.io/.
[18] WISHBONE sys em-on-chip (SoC) in e connec ion a chi ec u e o po able IP co es — WISHBONE B3, 2019, URL: h ps://wishbone-in e connec .
ead hedocs.io/en/la es /index.h ml.
[19] ISO/IEC 29192-2:2019 in o ma ion secu i y — Ligh weigh c yp og aphy — Pa 2: Block ciphe s, 2019, URL: h ps://www.iso.o g/s anda d/78477.h ml.