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Concurrent focal-plane generation of compressed samples fromtime-encoded pixel values

Abstract

Compressive sampling allows wrapping the relevant content of an image in a reduced set of data. It exploits the sparsity of natural images. This principle can be employed to deliver images over a network under a restricted data rate and still receive enough meaningful information. An efficient implementation of this principle lies in the generation of the compressed samples right at the imager. Otherwise, i. e. digitizing the complete image and then composing the compressed samples in the digital plane, the required memory and processing resources can seriously compromise the budget of an autonomous camera node. In this paper we present the design of a pixel architecture that encodes light intensity into time, followed by a global strategy to pseudo-randomly combine pixel values and generate, on-chip and on-line, the compressed samples.

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Concurrent focal-plane generation of compressed samples fromtime-encoded pixel values

Author: Trevisi, M.; Bandala, H.C.; Fernández Berni, Jorge; Carmona Galán, Ricardo; Rodríguez Vázquez, Ángel Benito
Publisher: IEEE
Year: 2018
DOI: 10.23919/DATE.2018.8342217
Source: https://idus.us.es/bitstreams/1350d9f1-faf8-42cd-855f-7727ffbe0cec/download
Concu en ocal-plane gene a ion o comp essed
samples om ime-encoded pixel alues
M. T e isi(1) , H. C. Bandala(2), J. Fe nández-Be ni(1), R. Ca mona-Galán(1), Á. Rod íguez-Vázquez (1)
(1) Ins i u o de Mic oelec ónica de Se illa (IMSE-CNM), CSIC-Uni e sidad de Se illa, Spain
(2) Ins i u o Nacional de As o ísica, Óp ica y Elec ónica (INAOE), Puebla, Mexico
e [email protected]
Abs ac — Comp essi e sampling allows w apping he
ele an con en o an image in a educed se o da a. I exploi s
he spa si y o na u al images. This p inciple can be employed o
deli e images o e a ne wo k unde a es ic ed da a a e and
s ill ecei e enough meaning ul in o ma ion. An e icien
implemen a ion o his p inciple lies in he gene a ion o he
comp essed samples igh a he image . O he wise, i. e.
digi izing he comple e image and hen composing he
comp essed samples in he digi al plane, he equi ed memo y
and p ocessing esou ces can se iously comp omise he budge o
an au onomous came a node. In his pape we p esen he design
o a pixel a chi ec u e ha encodes ligh in ensi y in o ime,
ollowed by a global s a egy o pseudo- andomly combine pixel
alues and gene a e, on-chip and on-line, he comp essed
samples.
Keywo ds— comp essi e sampling; cellula au oma on; ime-
encoded pixels;
I. INTRODUCTION
Spa si y in na u al images can be exploi ed o comp ess he
signal and hen eco e he con en om a numbe o samples
ha is below he limi de e mined by Nyquis ’s heo em [1] [2].
In o de o implemen his comp essing mechanism, a pai o
ma ices is applied o he coe icien s o he o iginal signal,
image pixel alues in ou case. These ma ices a e he
comp essi e s a egy, Φ, and he spa si ying dic iona y, Ψ.
Each comp essed sample is a linea combina ion o he
elemen s o he o iginal image. Then, om a se o comp essed
samples much smalle han he o iginal image, con ex
op imiza ion can lead o a unique solu ion. In o de o achie e
his, he p oduc o Φ and Ψ mus hold he es ic ed isome y
p ope y (RIP) [3].
Building a comp essi e s a egy on-chip is no i ial. The
mos common app oach is o ob ain he elemen s o Φ om a
andom dis ibu ion. I has been implemen ed by using op ical
elemen s [4] and also by employing dedica ed ci cui y [5]. The
simples implemen a ion consis s in using a sub-Gaussian
dis ibu ion, i. e. he elemen s o Φ a e ob ained om a no mal
dis ibu ion ha is h esholded so hey a e ei he one o ze o. In
his way each comp essed sample esul s di ec ly om he
addi ion o all he pixels selec ed by Φ. In p ac ice, he e a e
wo majo limi a ions o implemen hese echniques a senso
le el. Fi s o all, he comp essi e s a egy mus be known a
bo h ex emes o he communica ion channel. This is, no only
he senso mus know which he comp essi e s a egy is in
o de o gene a e he co esponding comp essed samples, bu i
mus be p esen also a he end o he channel, in o de o
econs uc he o iginal image. The e o e, ei he he
comp essi e s a egy is gene a ed a he senso and ansmi ed
o he image econs uc ion sys em o i needs o be s o ed a
bo h ends. This ep esen s an impo an bu den as hese op ions
will in oduce s ong equi emen s on he ansmission
bandwid h and/o he in-senso memo y. The second ques ion
is dynamic ange. The numbe o bi s equi ed o desc ibe he
linea combina ion o 𝑁 pixels is log2𝑁 in addi ion o he bi s
equi ed o desc ibe one single pixel. This is a majo limi a ion
o an implemen a ion o his addi ion in he analog plane, as
dynamic ange in analog ci cui s is limi ed by he a ailable
ou pu ange and noise le el.
These wo limi a ions can be alle ia ed wi h a widely
ex ended app oach: block-based comp essi e sampling [6] [7]
[8]. The pixels o he comple e image a e di ided in o mac o-
blocks o which he comp essi e s a egy is applied. This
ep esen s a conside able educ ion o Φ and he in as uc u e
equi ed o i s gene a ion, ansmission and/o s o age. A he
same ime, he equi ed dynamic ange o ep esen he
comp essed samples is no iceably educed. In exchange o
his, econs uc ion depa s om ideal and may equi e
addi ional samples o achie e a p esc ibed accu acy.
Ou app oach is he on-chip gene a ion o a ull- ame
comp essi e s a egy [9] by means o a 1D cellula au oma on
(CA) o he pseudo- andom selec ion o pixels [10]. This
solu ion a oids bo h ansmi ing and s o ing he comp essi e
s a egy as i can be e o - ee econs uc ed om he ini ial
seed wi h an analogous CA implemen a ion. In addi ion o his,
pixel alues need o be ep esen ed in a o m ha does no
exhaus he a ailable dynamic ange when being added up. In
o de o do his, we a e encoding pixel alues in ime. Addi ion
is ealized in he digi al domain by asynch onously agging
e en s in a pe -column basis. In his pape we a e displaying
he de ails o he design o he chip, s a ing wi h he indi idual
pixel, and ollowing wi h he pseudo- andom selec ion o
pixels, he ime o digi al con e sion o he pixel alue, he
column addi ion and he inal gene a ion o he comp essed
sample.
II. PIXEL ARCHITECTURE
The ou pu o a comp essi e sampling image is gi en in
he o m o linea combina ions o andomly selec ed pixel
con ibu ions. These linea combina ions a e he comp essed
samples [1]. As we ha e al eady e e ed, he gene a ion o he
andom pa e n o he selec ion o pixels has been le o a
one-dimensional cellula au oma on ha will be desc ibed la e
on. As o now, jus conside ha a se o de ices deli e ing
andom logic ze oes and ones a e employed o gene a e
selec ion signals o he ows and columns o he pixel a ay.
Apa om he gene a ion o andom selec ion signals, he
majo di icul y on implemen ing a ull- ame comp essi e
s a egy is p o iding enough dynamic ange o accommoda e
comp essed samples. Conside ha each pixel alue, ei he
o iginally a ol age o a cu en , is ep esen ed by 𝑁𝑏 bi s. Fo
an image o 𝑀 × 𝑁 pixels ha can be chosen a andom o
compose a comp essed sample, he numbe o bi s equi ed o
a oid any kind o clipping in he gene a ion o comp essed
samples is:
𝑁𝐵= 𝑁𝑏+ log2(𝑀𝑁) (1)
Fu he mo e, e en in block-based comp essi e sampling [11],
whe e images a e di ided in o small blocks o educe 𝑁𝐵,
comp essi e samples a e gene a ed using blocks ha ha e a
minimum p ac ical size o 8 × 8 pixels. Smalle blocks would
no be e y spa se and as such one o he undamen al p emises
behind comp essi e sampling would all. To p ese e
esolu ion, i each pixel alue is encoded in 8b, we would s ill
need 14b o esolu ion in o de o p ope ly encode comp essed
samples. Ou app oach o p o ide he numbe o bi s p esc ibed
by Eq. (1) is o ime-encode he pixel alues and employ ime-
o-digi al con e sion. The summa ion o pixels is hen ealized
in he digi al domain, a oiding he equi emen o a wide
dynamic ange in he analog domain.
A. Time-encoding o ligh in ensi y
The elemen a y pixel (Fig. 1) con ains an in eg a ing
pho odiode ha discha ges node 𝑉
𝑝𝑖𝑥 a a a e de e mined by
he pho ocu en . This is depic ed inside he ‘Time-encoding o
ligh in ensi y’ box in Fig. 1. When 𝑉
𝑝𝑖𝑥 c osses a e e ence
ol age 𝑉
𝑟𝑒𝑓, a ol age compa a o lips i s ou pu , 𝑉
1. I ime-
encodes he magni ude o he ligh in ensi y, wha is desc ibed
as pulse-modula ion imaging [12]. The pixel alue is hen
con ained in he pe iod o ime sepa a ing he ese o node 𝑉
𝑝𝑖𝑥
and he momen in which 𝑉
1 u ns om low o high. The lowe
(highe ) he ligh in ensi y on he diode is, he longe (sho e )
i akes o he compa a o o swi ch. In his chip, bo h 𝑉
𝑟𝑠𝑡 and
𝑉𝑟𝑒𝑓 can be adjus ed on-line in o de o adap o di e en
illumina ion condi ions in eal- ime.
B. Pixel selec ion ci cui
As p e iously men ioned, he con ibu ion o each pixel o a
pa icula comp essed sample is de e mined by a combina ion
o ow and column selec ion signals, 𝑆𝑖 and 𝑆
𝑗, ha a e
gene a ed wi h he help o a one-dimensional cellula
au oma on posi ioned a ound he senso a ay (Fig. 2). These
wo signals a e combined by a XOR ga e, implemen ed by 6
ansis o s in Fig. 1. The ol age 𝑉
2 is s uck a 𝑉
𝑑𝑑 i selec ion
signals 𝑆𝑖 and 𝑆𝑗 a e equal. I no , 𝑉
2 is he in e se logic alue
o 𝑉
1. Using a XOR ga e gua an ees ha he pixel con ibu es
o he linea combina ion ha cons i u es a comp essed sample
in jus hal o he possible combina ions o 𝑆𝑖 and 𝑆
𝑗. I is
impo an o no ice ha his pixel selec ion uni is alloca ed
igh a e he compa a o because his helps educing powe
consump ion. I a pixel is no con ibu ing o he comp essed
sample he e is no eason o le he pixel ac i a ion on
p opaga e, inducing changes in he subsequen nodes ha a e
going o be disca ded la e .
C. P opaga ion o he ac i a ion edge
Signal 𝑉
2 is ac i e in low, elici ing a ising edge in 𝑉
3 i his
signal has no been ac i a ed be o e. I i has, he eedback o
𝑉3
 locks 𝑉
3 o logic ‘1’ un il he pixel is ese again. Now
conside ha signal 𝑄′ is high. La e we will wha makes 𝑄′
changes o e ime. I 𝑄′ is in logic ‘1’, hen 𝑉
4 is he in e se o
𝑉3, i. e. i he pixel is ac i a ed and is selec ed o con ibu e o
he comp essed sample, 𝑉
3 goes om logic ‘0’ o ‘1’ and 𝑉
4
goes om ‘1’ o ‘0’. I signal 𝐶𝑖𝑛 is low, his alling edge in 𝑉
4
induces a ising edge in 𝑉
5 which is he signal con olling
d i ing ansis o M2. The column bus, whose ol age 𝑉
𝑜 is
pulled up o 𝑉
𝑑𝑑 by de aul , expe iences a pull down d i en by
M2. 𝑉
𝑜 will emain low i i was no o he e en e mina ion
ci cui .
D. E en e mina ion ci cui
The ising edge in 𝑉
5 is eedback o he e en e mina ion
ci cui , whe e i is in e ed as long as 𝑄, which is a global
signal, is high. This causes 𝑄′ o all o logic ‘0’, swi ching
Fig. 1 Schema ics o he elemen a y pixel
back 𝑉
4 o logic ‘1’ and hen 𝑉
5 o logic ‘0’, e mina ing he
pulse ha s a ed be o e a e a sho delay.
The mo i a ion o use a global pulse e mina ion signal o
es ablish he du a ion o he e en s ins ead o a local delay uni
is o p o ide global con ol wi hou in oducing a ea and/o
powe consuming elemen s in he pixel. In pa icula , 𝑄 is a
signal p o ided by a con ol uni in each column o he pixel
a ay. This uni senses he column bus and de ec s i i is being
pulled down. Once he alling edge is de ec ed, and a e a use -
con ollable delay, 𝑄 ises enabling he e mina ion o he pulse
only in he pixel ha has al eady u ned M2 on. This is e i ied
by he NAND ga e in he ‘E en e mina ion ci cui ’ box
(Fig. 1).
E. Pixel ou pu con ol
As depic ed in Fig. 1, all pixels in he same column o he
a ay sha e he same column bus o ansmi i s ou pu pulse.
As will be explained la e , he ime-encoding o he pixel alue
will be con e ed o digi al by means o a ime- o-digi al
con e e , which in his case will be buil wi h a clock and a
coun e . O cou se, he e is no a p io i knowledge on he
p oximi y o he alues o he pixels and, he e o e, how close
in ime will be he pulses emi ed by he pixels. Wha is clea is
ha each one o hem needs o be aken in o accoun i we do
no wan o in oduce addi ional e o s in he image
econs uc ion om i s comp essed samples. In o de no o
skip any o he pulses, a oken p o ocol is es ablished so pixels
ha a e being igge ed close in ime a e only allowed o emi
hei pulse one a e he o he . This blocking mechanism needs
o be pa allel o all pixels so ha he i s pixel ha deli e s i s
e en pu s all o he pixels on hold un il i s e en is o e . The
elease mechanism on he con a y has o be sequen ial so ha ,
i he e is mo e han one pixel in queue wai ing o deli e i s
pulse, i will be impossible o ha e mo e han one o hem
ac i e a he same ime. In o de o do so, each pixel ecei es a
signal 𝐶𝑖𝑛 om he pixel immedia ely abo e (Fig. 1), and sends
a signal 𝐶𝑜𝑢𝑡 o he pixel immedia ely below i . I he e is no
p eceding pixel wai ing o deli e a pulse h ough he column
bus, 𝐶𝑖𝑛 will be low. This enables he p opaga ion o a alling
edge in 𝑉
4 when i occu s in o a ising edge in 𝑉
5. I 𝐶𝑖𝑛 is high,
howe e , his p opaga ion is e ained.
One pixel’s 𝐶𝑖𝑛 co esponds o i s uppe neighbo 𝐶𝑜𝑢𝑡. In
o de o be ‘0’, h ee di e en condi ions mus hold, namely: i s
𝐶𝑖𝑛 is low, wha means ha he e is no pixel abo e i ha wan s
o deli e a pulse; 𝑉
4 is high, wha means ha ei he he pixel
has no been ac i a ed o i has al eady deli e ed a pulse; and
𝑉
𝑜 is high, wha means ha he column bus is a ailable. I any
o hese h ee condi ions is no ue 𝐶𝑜𝑢𝑡 will be s uck a he
logic ‘1’, hus p e en ing any o he pixels below i emi ing a
pulse h ough he column bus. A 3-inpu NAND ga e is
employed o combine he le el a 𝐶𝑖𝑛, he pixel eadiness o
pull down he column bus and he eedback on he ac ual s a e
o his column bus. This agg ega ed in o ma ion is hen sen as
𝐶𝑜𝑢𝑡 o he pixels below. Using his logic each pixel will know
ha i 𝑉
𝑜= 𝑉𝑑𝑑 and no pixel abo e is wai ing o pull i down i
is allowed o elease i s own e en . Since 𝑉
𝑜 is ed back o his
con ol block, when a pull down occu s, each pixel will
simul aneously block he pixel immedia ely below h ough
𝐶𝑜𝑢𝑡. The blocking mechanism is pa allel. On he con a y,
when an e en is o e , i s 𝐶𝑜𝑢𝑡 u ns o ‘0’, so he pixels will be
eleased sequen ially in a op down ashion.
III. SENSOR ARCHITECTURE
The pixel al eady desc ibed is pa o an image senso ha
implemen s a ull- ame comp essi e s a egy. The a chi ec u e
o he chip is depic ed in Fig. 2. The cen al elemen o he
a chi ec u e is an a ay o 64 ×64 pixels. The pe iphe al
ci cui needs o implemen he ollowing unc ionali ies:
pseudo- andom column and ow selec ion, ime- o-digi al
con e sion o he pixel alues, addi ion o he pixel alues o
he selec ed pixels. Le us desc ibe he ci cui s implemen ing
hese unc ionali ies one by one.
Fig. 2 Concep ual loo plan o he senso chip
A. Pseudo- andom gene a ion o selec ion signals
The gene a ion o pseudo- andom pa e ns s a ing om a
seed can be ealized using di e en me hods. Some o hem
ha e been employed be o e in he con ex o comp essi e
sampling, like Hadama d ec o s [13] o linea eedback shi
egis e s [14]. As al eady men ioned, ou app oach consis s in a
1-D cellula au oma on, which has he ad an age o being
easily implemen ed in CMOS echnology and i s scalabili y, as
he e olu ion o i s cells only depends on hei own s a e and
hose o hei closes neighbo s. Typically a linea CA wi h
adius-1 in e ac ions be ween i s cells is de ined by a u h able
de ined on he cell s a e (S) and he s a es o he le (L) and
igh neighbo (R). Table I shows he u h able o Rule 30,
which has been demons a ed o display ape iodic (class III)
beha io [10]. The ci cui employed o implemen a cell o his
cellula au oma on is depic ed in Fig. 3. The cell s a e is
p ecisely he selec ion signal ha is deli e ed o a ows o a
column, depending on he posi ion o he CA cell (Fig. 2).
Table I T u h able o Rule 30
L
S
R
NS
1
1
1
0
1
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
0
Fig. 3 Implemen a ion o a Rule 30 cell o a cellula au oma on
B. Column-wise ime- o-digi al con e sion
E en s gene a ed a he pixels and ansmi ed h ough he
column bus a i e o block ‘Sample & Add’ in (Fig. 2). These
pulses encode he pixel alue in he pe iod o ime ha has
passed be ween he pixels ese and he a i al o he ‘Sample
& Add’. A s aigh o wa d me hod o ansla e all his pulses
in o digi al codes is o use he pulses o ac i a e he sampling o
a global ime coun e (Fig. 2) ac i a ed by a clock signal and
s a ed wi h he global pixel ese —alloca ing some ini ial
delay o allow he pulses o each he bo om o he a ay. Each
ime a pixel ac i a ion pulse a i es, he 8b o he coun e a e
sampled and added o he al eady s o ed sum. A e 256 clock
pe iods, he pixel alues ha e been accumula ed a he ‘Sample
& Add’, which deli e s a 14b wo d con aining his sum, as i is
he esul o adding up o 64 pixel alues. A e ha , he 64
column sums a e added up in o a comp essed sample o 20b.
Comp essed samples need o be encoded in a much la ge
digi al wo d, he e o e he e is an amoun o comp essed
samples beyond which i is be e o jus deli e he
uncomp essed image. In ou case, as pixel alues a e encoded
by 8b and, and comp essed samples in 20b, he comp ession
a io (𝑅), i. e. he numbe o samples deli e ed di ided by he
o al numbe o pixels in he image, needs o be below 0.4. This
means ha o a 𝑀 × 𝑁-pixel image, we will be always
conside ing less han 0.4𝑀𝑁 comp essed samples.
In addi ion, as comp essed samples a e gene a ed
sequen ially, i is necessa y o ope a e he image a a ame
a e (𝑓
𝑐𝑠) —conside ing ha i is e e ed o he ime i akes o
deli e one single comp essed sampling— ha is a maximum
0.4𝑀𝑁 imes he o iginal ame a e (𝑓
𝑠)
𝑓
𝑐𝑠 = 𝑅 ∙ 𝑀𝑁𝑓
𝑠 (2)
Fo 𝑓
𝑠=30 ps, 𝑅 = 0.4 and an image o 64 ×64 pixels,
comp essed samples can be gene a ed a ≈50kHz a
maximum. This is 20s pe comp essed sample. I he du a ion
o e en s is, o ins ance, 5ns, and he 64 pixels in a column a e
selec ed, he e is a 6.25% chance ha wo e en s will andomly
o e lap. In o de o a oid missing any pulses, we a e deli e ing
hem one by one so ha , i he e is mo e han one pixel in
queue wai ing o deli e i s e en , i is impossible o ha e mo e
han one o hem ac i e a he same ime. As he ime- o-digi al
con e sion clock need o ick 256 imes in he 20s, i is
possible ha some pulses a e de ec ed in he ollowing clock
pe iod, wha will in oduce a 1LSB e o in he 20b
comp essed sample. Ve i ica ion on he negligible in luence o
his e o has been pe o med a sys em le el.
IV. CHIP PROTOTYPE
A p o o ype chip has been designed in a CMOS 0.18m
echnology ollowing he al eady desc ibed me hodology. The
die size including pads is 3.17 × 2.23 sq. mm (Fig. 4). I has
84 pads, o which one hi d is dedica ed o powe supply and
g ound connec ions. Table II con ains a summa y o he
ea u es o he p o o ype ha is al eady in ab ica ion.
Fig. 4 Layou o he p o o ype senso chip
Table II Summa y o chip ea u es
Technology
CMOS 0.18m 1P6M
Die size (w. pads)
3174μm × 2227μm
Pixel size
22μm × 22μm
Fill ac o
9.2%
Resolu ion
64 ×64
Pho odiode ype
n-well/p-subs a e
Powe supply
3.3V-1.8V
P edic ed powe consump ion
<100mW
F ame a e
30 ps
Max. comp essed sample a e
50kHz
Clock F eq.
24MHz
The cen al pa o he chip is he a ay o 64 ×64 pixels.
Fig. 5 depic s he layou o he elemen a y pixel. The blocks
desc ibed in Sec . II can be iden i ied. In o de o educe he
in luence o he o se o he compa a o , an au o-ze oing
scheme has been implemen ed using a MiM capaci o on he
op me al laye s (no showing in he pic u e). Fo mal
e i ica ion o he chip pe o mance has been ealized wi h
pos -layou simula ion.
Fig. 5 Layou o he elemen a y pixel
V. CONCLUSIONS
The design o comp essi e sampling image senso
p o o ype based on he on-chip gene a ion o a ull- ame
comp essi e s a egy has been comple ed. Majo design ade-
o s a e ela ed wi h accu acy o he econs uc ion and ame
a e, because o comp essed samples being oo ew o
inaccu a e. Time-encoding o he pixel alues and agging o
asynch onous pulses coming om a collec ion o pulses is he
me hodology employed o o e come dynamic ange limi a ions
in he cons uc ion o he comp essed samples. Expe imen al
cha ac e iza ion o he p o o ype will allow e i ying he
ad an ages o ull- ame comp essi e s a egies e sus block-
based comp essed sampling.
ACKNOWLEDGMENT
This wo k has been unded by he Spanish Go e nmen
h ough p ojec s TEC2015-66878-C3-1-R MINECO (Eu opean
Region De elopmen Fund, ERDF/FEDER), by Jun a de
Andalucía h ough p ojec TIC 2338-2013 CEICE and by he
O ice o Na al Resea ch (USA) h ough g an
N000141410355 and CONACYT (Mexico) h ough g an
MZO-2017-291062.
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