Abs ac
This communica ion p esen s HALOTIS, a no el high
accu acy logic iming simula ion ool, ha inco po a es a
new simula ion algo i hm based on di e en concep s o
ansi ions and e en s. This new simula ion algo i hm is
in ended o including he ine ial and deg ada ion delay
models. Simula ion esul s a e e y simila o hose
ob ained by elec ical simula o s, and show a highe
accu acy compa ed o con en ional delay models
implemen ed in cu en logic simula o s.
1. In oduc ion
As digi al ci cui s become la ge and as e , be e anal-
ysis ools a e equi ed. I means ha logic simula o s mus
be able o handle bigge ci cui y in a mo e accu a e way.
Simula ing la ge ci cui s is aided by he e olu ion o com-
pu e sys ems capabili ies, and accu acy is imp o ed by
p o iding mo e ealis ic delay models.
Cu en ly, he e exis accu a e delay models o CMOS
digi al ci cui s which ake accoun o mos mode n issues
[1, 2, 3, 4]: low ol age ope a ion, sub-mic on and deep
sub-mic on de ices, ansi ion wa e o ms, e c. Besides
hese e ec s, he e a e also dynamic si ua ions which
should be handled by he delay model. The mos impo an
dynamic e ec s a e he so-called inpu collisions [5]: he
ga e’s beha io when wo o mo e inpu ansi ions happen
close in ime may be qui e di e en om he esponse o an
isola e inpu ansi ion. O all hese inpu collisions, he e
is a special in e es in he gli ch collisions, which a e hose
ha migh cause an ou pu gli ch. Being able o handle
hese gli ch collisions is impo an since hey a e mo e and
mo e likely o happen in cu en as ci cui s, and i will
help us o de e mine ace condi ions and uly powe con-
This wo k has been sponso ed in pa by he MCYT unde
P ojec TIC 2000-1350
sump ion due o gli ches [6,7]. This is also s ongly ela ed
o he modeling o he ine ial e ec [8], which de e mines
when a gli ch is il e ed, and o he igge ing o me as able
beha io in la ches [9, 10, 11, 12]. O he au ho s ha e deal
wi h he p oblem o gli ches, ei he pa ially o no e y
accu a ely [5, 6, 7, 13].
In [14, 15, 16, 17] a new model denomina ed Ine ial
and Deg ada ion Delay Model (IDDM) has been in o-
duced. This model combines he deg ada ion e ec o
gli ches wi h a new algo i hm o handle he ine ial e ec .
When ying o inco po a e his model in he cu en logic-
iming simula o s, as VHDL s anda d simula o o VER-
ILOG, he e a e many p oblems di icul o sol e since he
new p oposed app oach dealing wi h deg ada ion and ine -
ial e ec s signi ican ly a ec s he simula ion algo i hm
i sel . The e o e i is necessa y o build a new logic- iming
simula ion ools based on he new algo i hm o include he
IDDM.
In his pape we p esen a new logic- iming simula o
called HALOTIS including he IDDM. The wo k is o ga-
nized as ollows. In he nex sec ion we esume he IDDM.
In he hi d sec ion we desc ibe he new simula ion algo-
i hm implemen ed in HALOTIS. As i will be shown, he
mos in e es ing aspec s o HALOTIS is he no el dealing
o s imuli in signals and he simula ion algo i hm. Resul s
o simula ion a e p esen ed in ou h sec ion, showing a
good ag eemen wi h elec ical simula ion, and CPU ime
e y simila o hose om o he logic simula o s. La ely,
we p esen he mos impo an conclusions o he wo k.
2. The IDDM model
Typical models o logic simula ion only conside he
ine ial e ec o deal wi h e y na ow pulses. These mod-
els show a discon inuous beha io o e y simila inpu
condi ions. This discon inui y is due o he ac ha
depending on i s wid h, an inpu pulse may be in a no mal
HALOTIS: High Accu acy LOgic TIming Simula o wi h ine ial and deg ada ion
delay model
Ruiz de Cla ijo Vazquez, P1. ; Juan-Chico, J1. ; Bellido, M.J1. ; Acos a, A2. and Valencia, M.1
Ins i u o de Mic oelec onica de Se illa. CNM
Edi icio CICA, A da/ Reina Me cedes s/n 41012-Se illa. Spain
{paulino,jjchico,bellido,acojim,manolo }@imse.cnm.es
1 also wi h Dp o. de Tecnologia Elec onica. Uni e sidad de Se illa
2 also wi h Dp o. de Elec onica y Elec omagne ismo. Uni e sidad de Se illa
Tl . +34-955056666 Fax. +34-955056686
p opaga ion o a il e ing (non-p opaga ion) egion. How-
e e , he change in he beha io o a ue ga e is no ab up ,
a he con inuous and g adual. In ac , wo limi cases
appea in eal beha io : one o wide pulses ha a e p opa-
ga ed no mally and ano he o e y na ow pulses ha a e
elimina ed, bu he e is a pulse-wid h ange be ween hem
in which pulses a e nei he elimina ed no p opaga ed no -
mally. Inside his ange, he ou pu pulse wid h is smalle
han he co esponding inpu pulse wid h. In such a case,
he pulse is conside ed o be deg aded.
We showed in [15,16,17] ha he delay dec eases expo-
nen ially as pulses a e sho ened. Full deg ada ion e ec
insigh s we e s udied o he case o CMOS ga es and a
delay model ha akes in o accoun he exponen ial beha -
io o he deg ada ion e ec was also p esen ed. The main
esul s o his model can be summa ized as ollows: only
wo pa ame e s o each ype o ansi ion, and , a e
needed o model he deg ada ion e ec , esul ing in he ol-
lowing o mula:
(eq. 1)
whe e is he no mal p opaga ion delay, ha can be
calcula ed using a con en ional delay model [1, 2], is he
ime elapsed since he las ou pu ansi ion in he ga e's
ou pu ook place, which measu es he in e nal s a e o he
ga e, and and a e he deg ada ion pa ame e s which
depend on he ou pu load ( ), he supply ol age ( ),
he inpu ansi ion ime ( ) and he posi ion o he inpu
ha is changing s a e ( ). I has been ob ained in [15] ha
his dependence can be exp essed as:
(eq. 2)
(eq. 3)
whe e “x” s ands o “ ”o “ ” depending on he sense o
he ou pu ansi ion ( ise o all espec i ely).
Gli ch deg ada ion should be combined wi h ine ial
e ec because, a e sucesi e deg ada ions, a un pulse will
be elimina ed. In [14] we ha e demos a ed ha he con en-
ional model o ine ial e ec , de ined as an ine ial delay,
may p oduce w ong esul s in a logic simula ion. This can
be obse ed in Figu e 1 and, as consequence, he accu acy
o he simula ion dec eases. In his wo k we p opose a new
ea men o he ine ial e ec , ha oge he wi h he DDM
model esul s in he IDDM model: Ine ial and Deg ada ion
Delay Model.
The basic di e ence be ween cu en models o he
ine ial e ec and he p oposed model, lies in he choice o
he exac place whe e pulses a e il e ed. In classical mod-
els, one pulse is ejec ed a he ou pu o a ga e i when
p opaga ing h ough he ga e, i does no each he middle
poin o he logic swing, meaning ha he pulse does no
exis o any ga e’s inpu connec ed o his ou pu signal.
Howe e , in ou p oposal, any ou pu pulse is aken in o
accoun , e en i i does no each he middle poin o he
logic swing. A he inpu s o he ga es connec ed o his ou -
pu , i is decided i his pulse is able o p oduce a ansi ion
in hose ga es o no . In his way is possible ha a small
pulse, can be p opaga ed h ough one o mo e ga es, while
canno be p opaga ed h ough o he di e en ga es con-
nec ed o he same signal.
Wi h his idea, in [14] i is p o ided he model wi h a
new pa ame e VT ha is he ol age h eshold associa ed o
he ga e inpu . A pulse in inpu is only p opaga ed i i
c osses he VT alue.
I is impo an o no ice ha , in o de o implemen his
model in a logic- iming simula o , i is necessa y o handle
signals wi h bo h iming and ol age pa ame e s. Fo his
eason i is no possible o include his model in cu en
logic simula ion ools. We ha e de eloped a simula o
adap ed o IDDM which con ains a new simula ion algo-
i hm as shows nex sec ion.
3. HALOTIS Simula o
As i was p e iously men ioned, we ha e de eloped a
new logic iming simula o named HALOTIS. Figu e 2
shows he class diag am o HALOTIS, whe e he ela ions
be ween he implemen ed da a s uc u es can be seen. The
main cha ac e is ics o his simula o a e he new way o
deal wi h s imuli and a no el simula ion algo i hm.
τT0
p p01e
TT
0
–
τ
----------------


–
–




=
p0T
τT0CLVDD
τin
i
τxVDD Axi BxiCL
+=
T0x1
2
---Cxi
VDD
-----------–


τin
=
in e e
ou 1
ou 2
ou 1c
ou 2c
012345
0
1
2
3
4
5
V
T2
V
T1
V
in
g1
g2
in
V
ou
g2
g1
g0
chain
in e e
chain
ou 0
0123
0
1
2
3
4
5
0123
0
1
2
3
4
5
in
ou 0
ou 1 ou 1c
ou 2
ou 2c
0123
V
T2
V
T1
in
ou 0
ou 1
ou 1c
ou 2
ou 2c
(a)
Figu e 1. Ine ial delay w ong esul s. a) Simula ed
ci cui and ans e cha ac e is ics o in e e s. b)
HSPICE simula ion esul s. c) Logic simula ion
esul s using he ine ial delay model.
(b) (c)
3.1 Dealing wi h s imulis.
To imp o e simula ion accu acy, we dis inguish
be ween “ ansi ion” and “e en ”. A ansi ion is a signal
changing om “0” o “1” o “1” o “0”. They a e app oxi-
ma ed by a linea cu e and de e mined by he ise o all
ime (τx) and he ins an when he ansi ion begins ( 0). As
ga e inpu s may ha e indi idual inpu h esholds (V ), a sin-
gle ansi ion may igge a ga e ac i a ion a di e en ol -
ages, which means di e en imes o a signal ha d i e s
a ious ga e’s inpu s (Figu e 3). Each ime a ansi ion
c osses an inpu h eshold, an e en is gene a ed. The simu-
la ion is pe o med in e ms o e en s, aking accoun o
indi idual inpu h esholds.
Bo h he ansi ions and he e en s a e s o ed in di e en
da a s uc u es. The ansi ions use a lis - ype s uc u e,
s o ing iming pa ame e s τxand 0whe e x indica es ise o
all ansi ion ype. The e en s a use queue- ype s uc u e,
s o ing only he ime ins an (E) when he e en akes place.
E e y e en is associa ed o a ga e inpu ha is included in
he da a s uc u e ha holds he ci cui ne lis , and also o
he ansi ion ha caused he e en
3.2 Simula ion Algo i hm
In Figu e 4, i can be seen he basic s eps o he p o-
posed simula ion algo i hm. E e y s ep pe o ms he asks
ha a e desc ibed below.
The ask o he i s s ep is o ge he i s e en om he
e en queue, and ge all associa ed da a om he class ela-
ions. These da a a e he ga e and he ga e inpu whe e e en
occu s and he ansi ion ha p oduces i .
In he second s ep, he ou pu ansi ion is calcula ed
using he DDM di ec ly.
When he ou pu ansi ion is calcula ed and gene a ed,
he algo i hm en e s a loop whe e wo asks mus be pe -
o med. Fi s , i mus gene a e all e en s associa ed o his
ansi ion and, second, i mus e alua e he p esence o ine -
ial e ec in e e y ga e inpu . This p ocess begins inding
ou he associa ed ga e inpu o he cu en ansi ion
h ough he ela ions be ween he ansi ion class and ga e
inpu class. Fo each ga e inpu , he Eje en is calcula ed
which will be he j- h e en associa ed o his ga e inpu .
Ne lis
LineT ansi ion
E en
Ga eInpu
Nex
P e
Nex
P e
{o de ed}
p oduces
Figu e 2. HALOTIS class diag am
E
1
V
T22
V
T31
V
H
V
L
E
2
E
3
V
T13
1
2
3
V
T13
1
2
3
V
T22
1
2
3
V
T31
1
2
3
Figu e 3. A ansi ion in signal “ou ” and i ’s
associa ed e en s
T ansi ion E en Ga e Ga e inpu Th eshold
τ , 0
E1 G2 2 VT22
E2 G3 1 VT31
E3 G1 3 VT13
τ
,
0
G
1
G
2
G
3
Ou
Ou
Ge i s e en om e en queue
Fo he associa ed ansi ion, calcula e
he ou pu ansi ion using DDM model
Ge nex associa ed ga e inpu
Calcula e Ej e en
Ej-1>EjDele e Ej-1 Inse Ej
Is he e ano he
ga e inpu ?
Yes No
Yes
Ge nex e en
No
Figu e 4. Simula ion algo i hm
F.A.
F.A. F.A. F.A. F.A.
F.A. F.A. F.A. F.A.
F.A. F.A. F.A. F.A. 0
0
0
a3a2a1a0
a3a2a1a0
a3a2a1a0
a3a2a1a0
b0
b1
b2
b3
0
s3s2s1s0
s4
s5
s6
s7
aibi
ci
ci+1
sici+1
ai
bi
ci
si
Figu e 5. 4x4 Mul iplie ci cui
This e en is compa ed wi h he p e ious e en in his same
inpu (Ej-1). I he new e en akes place a e he p e ious
one, i is inse ed in he e en queue, o he wise, he p e i-
ous e en is emo ed om he queue.
4. Simula ion Resul s
Figu e 5 shows a 4x4 bi mul iplie ci cui , whose simu-
la ion esul s will se e o e i y HALOTIS. The ci cui has
been designed in a 0.6µm CMOS echnology.
Figu e 6 includes he simula ion esul s o he inpu
sequence 0x0, 7x7, 5xA, Ex6, FxF ob ained wi h HSPICE,
HALOTIS-DDM and HALOTIS-CDM. HALOTIS-DDM
is he simula o HALOTIS inco po a ing DDM, while
HALOTIS-CDM inco po a es a con en ional delay model,
ha is, wi hou deg ada ion e ec . This is neccesa y o
compa e di e en ypes o simula ion esul s.
I is obse ed ha HALOTIS-DDM and HSPICE esul s
a e e y simila , while HALOTIS-CDM esul s shows
much mo e ou pu ansi ions han he o he s. This is due o
he exclusion o deg ada ion e ec , making he gli ches
gene a ed in he ci cui being p opaga ed o he ou pu . In
bo h HSPICE and HALOTIS-DDM, hese gli ches a e deg-
ada ed and, inally, ejec ed om he ou pu .
Figu e 7 shows he simula ion esul s o he 0x0, FxF,
0x0, FxF, 0x0 mul iplica ion sequence. F om he poin o
0 5 10 15 20 25
(ns)
s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
A
xB0x0 7x7 5xA Ex6 FxF
0 5 10 15 20 25
(ns)
s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
A
xB0x0 7x7 5xA Ex6 FxF
0 5 10 15 20 25
(ns)
s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
A
xB0x0 7x7 5xA Ex6 FxF
Figu e 6. Simula ion esul s o he 0x0, 7x7, 5xA,
Ex6, FxF mul iplica ion sequence wi h a) HSPICE,
b) HALOTIS-DDM, c) HALOTIS-CDM
a)
b)
c)
Figu e 7. Simula ion esul s o he 0x0, FxF, 0x0,
FxF mul iplica ion sequence wi h a) HSPICE, b)
HALOTIS-DDM, c) HALOTIS-CDM
0 5 10 15 20 25
s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
A
xB0x0 FxF 0x0 FxF 0x0
(ns)
0 5 10 15 20 25
s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
A
xB0x0 FxF 0x0 FxF 0x0
(ns)
0 5 10 15 20 25
s
7
s
6
s
5
s
4
s
3
s
2
s
1
s
0
AxB0x0 FxF 0x0 FxF 0x0
(ns)
a)
b)
c)
iew o he wa e o ms, he conclusions o he analysis a e
he same han hose explained in he p e ious case.
A e y in e es ing aspec o he esul s a e conce ning
he swi ching ac i i y. Table 1 includes he measu emen o
he swi ching ac i i y o HALOTIS-DDM and HALOTIS-
CDM. I is e y signi ica i e ha he use o con en ional
delay models can p oduce an o e es ima ion in swi ching
ac i i y up o he 40%.
On he o he hand, Table 2 includes he CPU imes o
di e en kinds o simula ion. As expec ed, HALOTIS is
be ween 2 o 3 o de s o magni ude as e han HSPICE.
Ano he in e es ing esul is ha HALOTIS-DDM is as e
han HALOTIS-CDM due o he educed swi ching ac i i y
o he o me .
5. Conclusions
Because o he ea u es o Ine ial and Deg ada ion
Delay Model (IDDM) o CMOS ga es, hei inclusion in
cu en logic- iming simula o s is a e y complex ask. Fo
his eason, we ha e de eloped HALOTIS, a new iming-
logic simula ion ool. The mos ele an aspec s o HALO-
TIS a e he no el way o deal wi h o s imuli and he simu-
la ion algo i hm, able o include he IDDM. Thus,
HALOTIS can p o ide high accu acy simula ion esul s,
e y simila o hose p o ided by elec ical simula o s as
HSPICE, educing up o h ee o de s o magni ude he CPU
simula ion ime. When compa ing o con en ionals e en -
d i en echniques, he esul s a e mo e accu a e when con-
side ing he p opaga ion and deg ada ion o gli ches and
na ow pulses, e en spending less simula ion ime, since
HALOTIS con empla es a educ ion in he swi ching ac i -
i y due o he inclusion o he ine ial and deg ada ion
e ec s.
6. Re e ences
[1] L. Bisdounis, S. Nikolaidis, O. Kou opa lou. “Analy ical
T ansien Response and P opaga ion Delay E alua ion
o he CMOS In e e o Sho -Channel De ices”. IEEE
J. o Solid-S a e Ci c. pp. 302-306. Vol. 33, no. 2, Feb.
1998.
[2] J.M. Daga, D. Au e gne. “A Comp ehensi e Delay Mac o
Modeling o Submic ome e CMOS Logics”. IEEE J. o
Solid S a e Ci cui s. Vol. 34, No. 1, Jan. 1999.
[3] A.I. Kayssi, K.A. Sakallah, T.N. Mudge. “The Impac o
Signal T ansi ion Time on Pa h Delay Compu a ion”.
IEEE T ans. on Ci cui s and Sys ems-II: Analog and
Digi al Signal P ocessing, Vol. 40, No. 5, pp. 302-309,
May 1993.
[4] D. Au e gne, N. Azema d, D. Deschach , M. Robe . “Inpu
Wa e o m Slope E ec s in CMOS Delays”. IEEE J. o
Solid-S a e Ci c., Vol. 25, No. 6, pp. 1588-1590. Dec.
1990
[5] E. Melche , W. Rö hig, M. Dana. “Mul iple Inpu T ansi ions
in CMOS Ga es”. Mic op ocessing and Mic o-
p og amming 35 (1992) pp. 683-690. No h Holland.
[6] C. Me a, M. Fa alli, B. Riccò. “Gli ch powe dissipa ion
model”. In P oc. PATMOS'95. pp. 175-189
[7] M. Eisele, J. Be hold. “Dynamic Ga e Delay Modeling o
Accu a e Es ima ion o Gli ch Powe a Logic Le el”. In
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[8] S. H. Unge . “The essence o logic ci cui s”. Ed. P en ice-
Hall In e na ional, Inc. 1989
[9] L.R. Ma ino. “Gene al Theo y o Me as able Ope a ion”.
IEEE T ans. on Compu e s, C-30 n.2, pp. 107-115, Feb.
1981.
[10] L. Kleeman, A. Can oni. “Me as able Beha io in Digi al
Sys ems”, IEEE Design and Tes o Compu e s, ol. 4.
Dec. 1987
[11] L.M. Reyne i, L.M. del Co so, B. Sacco. “Oscilla o y
Me as abili y in Homogeneous and Inhomogeneous
Flip- lops”. IEEE J. o Solid-S a e Ci c. Vol.25. n.1. Feb.
1990.
[12] J. Cal o, M. Valencia, J.L. Hue as. “Me as able Ope a ion in
RS Flip- lops”. In . J. Elec onics, Vol. 70 n.6. 1991.
[13] D. Rabe, B. Fiuczynski, L. K use, A. Welslau, W. Nebel.
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P oc. PATMOS'96. pp. 167-176.
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M. Valencia. “Ine ial and deg ada ion delay model o
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I-459-462, Gene a, May 2000.
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Table 1. HALOTIS simula ion esul s s a is ics
Sequence E en s Fil e ed e en s
HALOTIS-
DDM HALOTIS-
CDM O e s .CDM
(%) HALOTIS-
DDM HALOTIS-
CDM
0x0, 7x7, 5xA, Ex6, FxF 959 1411 47 27 1
0x0, FxF, 0x0, FxF, ... 1312 1992 52 66 6
Table 2. CPU ime in seconds o simula ions.
Sequence HSPICE HALOTIS-
DDM HALOTIS-
CDM
0x0, 7x7, 5xA, Ex6, FxF 112.9 0.39 0.55
0x0, FxF, 0x0, FxF, ... 123.0 0.48 0.76