A 64-Channel Induc i ely-Powe ed Neu al
Reco ding Senso A ay
Albe o Rod íguez-Pé ez, Jens Masuch, José A. Rod íguez-Rod íguez, Manuel Delgado-Res i u o and Ángel Rod íguez-Vázquez
Ins i u e o Mic oelec onics o Se illa and Uni e si y o Se illa
A da. Ame ico Vespucio s/n, 41092-Se ille, SPAIN
Email: {albe o, masuch, od iguez, mandel, angel}@imse-cnm.csic.es
Abs ac —This pape epo s a 64-channel induc i ely powe ed
neu al eco ding senso a ay. Neu al signals a e acqui ed,
fil e ed, digi ized and comp essed in he channels. Addi ionally,
each channel implemen s a local au o-calib a ion mechanism
which configu es he ans e cha ac e is ics o he eco ding si e.
The sys em has wo ope a ion modes; in one case he in o ma ion
cap u ed by he channels is sen as uncomp essed aw da a; in
he o he , ea u e ec o s ex ac ed om he de ec ed neu al
spikes a e ansmi ed. Da a s eams coming om he channels
a e se ialized by an embedded digi al p ocesso and ans e ed
o he ou side by means o he same induc i e link used o
powe ing he sys em. Simula ion esul s show ha he powe
consump ion o he comple e sys em is 377μW.
I. INTRODUCTION
In he las yea s, he e has been a g owing in e es on he
design o mul ichannel neu al eco ding in e aces wi h wi e-
less ansmission capabili ies o he un e he ed measu emen
o b ain ac i i y [1]–[3]. These in e aces a e expec ed o play
a significan ole bo h in clinical (as pa o he apeu ic p o-
cedu es in pa ien s wi h neu ological diseases), b ain-machine
in e aces and neu oscience applica ions. As hese eco ding
in e aces a e implan ed below he skull, he use o ul a-
low powe consump ion echniques is manda o y, no only o
p e en om ha m ul e ec s in he b ain, bu also o a oid
he need o ba e ies. Thus, by making he powe dissipa ion
low, i becomes easible o use ene gy ha es ing s a egies o
supplying he implan . This is illus a ed in Fig. 1 in which
he in ac anial de ice is powe ed ia a wi eless induc i e link
om an ex e nal uni placed on he head. The same link o a
dedica ed one could be also employed o da a ans e o such
ex e nal uni om whe e in o ma ion could be communica ed
o a specific hub o compiling and p ocessing he eco ded
b ain ac i i y.
This pape aims o con ibu e o his scena io and p esen s a
mul ichannel wi eless neu al senso a ay designed in a s an-
da d 0.13μm CMOS p ocess. I is composed o 64 channels
in which neu al signals a e acqui ed, fil e ed, digi ized and
op ionally comp essed [4]. The sys em has wo ansmission
modes; in one case he in o ma ion cap u ed om a selec ed
se o channels is ansmi ed as uncomp essed aw da a,
in he o he , ea u e ec o s a e ex ac ed om he de ec ed
neu al spikes a e e y channel and ansmi ed o he ex e nal
uni o u he p ocessing. A single wi eless induc i e link,
inspi ed in RFID echnologies, is used bo h o powe ing
skull
b ain
scalp
Ba e y- ee
mul ichannel
senso
Induc i e
link
Ex e nal Uni
Use In e ace
Da a S o age
Cen al P ocesso
Elec odes
Figu e 1. Implan ed solu ion o he wi eless neu al a ay.
he implan and o da a ans e o/ om he ex e nal uni .
This link uses a 40.68MHz ca ie signal and employs On-
O Keying (OOK) modula ion o da a ans e om he
ex e nal uni o he implan ( o wa d link) and Load-Shi
Keying (LSK) in he e e se di ec ion (backwa d link). A
4MHz clock is used o send in o ma ion h ough he backwa d
link. This is enough o he implan ope a ed in he ea u e
ex ac ion mode o cha ac e ize and se ialize he de ec ed
spikes e en in he unlikely case all he channels fi e a he
same ins an . Pos -layou simula ions show ha he o al powe
consump ion o he sys em, including he eco ding a ay and
he communica ion p o ocol, is only 377μW, i.e., abou one
o de o magni ude below p io a .
The pape is o ganized as ollows. The a chi ec u e o he
neu al senso is de ailed in Sec ion II. Sec ion III p esen s he
design o he RF on -end, while he simula ion esul s a e
gi en in Sec ion IV. Finally, Sec ion V ends he pape wi h
some conclusions.
II. NEURAL SENSOR ARCHITECTURE
Fig. 2 shows he a chi ec u e o he p oposed sys em.
I consis s o a 8x8 neu al eco ding a ay, each o hem
se ially connec ed o an E en -Based P ocesso Uni (EBPU),
which s o es he in o ma ion gene a ed by he channel. The
da a s o ed in hese EBPUs a e ead and classified by an
embedded digi al p ocesso , which also handles he iming
o he implan . A communica ion block implemen s he link
o/ om he ex e nal uni . Addi ionally, he sys em includes one
228
PGA
Vin
Band-limi ed
LNA
PGA + SC–based ADC
HPc l
LPc l
PGAc l
Di ec
Digi al
F equency
Syn hesize
(DDFS)
x8
Bina y
Sea ch
Calib a ion Th eshold
De ec o
Fea u e
Ex ac ion
Se ial Txon
Se ial Rxon
Cell
P ocesso
ADCen
x64
Se ial
Rxon
EBPU
Regis e
Coun e
EBPU
Con ig
x64
Clock
di ide
Da a Rxon Pie
Decode
CUP
Cell
P og am
Se ial Ou pu Regis e
Digi al P ocesso
Encode
Bandgap
Clock
Reco e y Backsca e
OOK Demodula o
Rec i ie
Digi al
Regula o
Analog
Regula o
Figu e 2. A chi ec u e o he mul ichannel neu al a ay.
unable Di ec Digi al F equency Syn hesize (DDFS) pe ow
o calib a ion pu poses [5].
Each channel embeds all he needed ci cui y o acqui e and
digi ize neu al wa e o ms including a Low Noise Amplifie
(LNA), a digi ally unable band-pass fil e , a P og ammable
Gain Amplifie (PGA), an Analog- o-Digi al Con e e (ADC)
and a local digi al p ocesso o de ec neu al spikes and ex ac
hei ea u es. The channel a chi ec u e is simila o ha in
[4] bu , in his e sion, spike de ec ion is accomplished in
digi al domain and he decision h eshold is adap i ely upda ed
acco ding o he noise floo o he cap u ed signal. Fu he , in
o de o inc ease he g anula i y o he calib a ion p ocess,
h ee con ol bi s a e used o adjus he high-pass pole o he
bandpass fil e .
A. Modes o ope a ion
Toge he wi h he wo al eady men ioned ansmission
modes, deno ed as signal acking and ea u e ex ac ion
modes, he sys em also o e s a o eg ound calib a ion mode.
They a e b iefly desc ibed nex .
Calib a ion: In his mode, he ans e cha ac e is ic and
gain o he eco ding channels a e indi idually adjus ed. This
is done by sequen ially adjus ing he pass-band o he fil e s
and he gain o he PGAs using he algo i hm in [5]. Fi s ,
he p og amming wo ds o he high-pass (3-bi ) and low-pass
(2-bi ) poles o he channel bandpass fil e a e uned so ha
i s passband anges om abou 200Hz o 7kHz, co esponding
o he spike spec al ange. This is done o e e y channel by
using he ou pu signals o he DDFSs as equency e e ences.
As he e is one DDFS pe ow, passband calib a ion is done
in a column-wise manne . A e wa d, e e y channel s a s
cap u ing neu al signals a a a e o 27kS/s and he gain o
each PGA is adjus ed so ha i s ou pu fi s in o he inpu
dynamic ange o he co esponding ADC. Digi ized signals
a e ansmi ed ou column by column so ha an ex e nal
obse e alida es he comple ion o he calib a ion p ocess.
This is done because neu al spiking is andom by na u e
and channels can be silen o long pe iods. A e alida ion,
he obse e can change o a di e en column o finish he
calib a ion p ocess by applying co esponding commands.
Signal T acking: In his mode, one column/ ow o he
a ay is a bi a ily selec ed o neu al signal moni o ing while
emaining channels a e disabled o powe sa ing. Neu al
signals a e acqui ed a a sampling a e o 27kS/s, 8-bi pe
sample, o gi e an o e all h oughpu a e o 1.92Mbps. No
da a comp ession is applied in his mode.
Fea u e Ex ac ion: In his case, he sys em is employed o
spike de ec ion asks. All he 64 channels a e enabled du ing
ea u e ex ac ion. E e y de ec ed spike is locally comp essed
a channel le el by means o a Piece-Wise Linea (PWL)
app oxima ion o i s wa e o m. This app oxima ion in ol es
ampli ude and ime in e al alues, an esul s in a 47-bi
ep esen a ion pe spike, enough o so ing and clus e ing
pu poses [4]. Du ing he cha ac e iza ion o he spike he
channel ope a es a a sampling a e o 90kS/s.
B. E en -Based Communica ion
EBPU uni s a e he esponsible o empo a ily s o ing he
in o ma ion p o ided by he channels. In he calib a ion and
signal acking modes, channels se ialize and ans e da a
o he EBPUs, whe e in o ma ion is e ained un il i is ead
ou by he sys em digi al p ocesso . In he ea u e ex ac ion
mode, EBPUs no only p o ide s o ing esou ces bu also
con ibu e on he calcula ion o he ime in e als in ol ed
in he PWL ep esen a ion o spikes. Peaking and h eshold
c ossing e en s along spikes a e ansmi ed o co esponding
EBPUs. Such uni s keep ack o he du a ion be ween he
e en s by means o coun e s. When spikes end, channels send
o he EBPUs he ampli ude ela ed in o ma ion o comple e
he associa ed PWL ea u e ec o s. Once ec o s a e ga he ed,
hey a e s o ed in he EBPUs eady o ead ou . I is wo h
obse ing his app oach educes he in o ma ion ans e om
he channels o he EBPUs by abou 50%, as single e en s
ins ead o comple e ime in e al measu emen s (coded in 8-
bi wo ds) a e ansmi ed.
The main digi al p ocesso cyclically eads he enabled
EBPUs. I i is ound he s o ed in o ma ion in he EBPU
is comple e, he digi al p ocesso e ie es da a a a 4MHz
a e, builds up he ansmission ame and sends his s eam
o he eleme y uni o wi eless ansmission.
C. Communica ion P o ocol
Simila o RFID echnologies, he sys em uses Pulse In e al
Encoding (PIE) o symbols in he o wa d link. Fig. 3(a)
shows he symbol ep esen a ions o da a-0 and da a-1, which
essen ially di e on he du a ion o he high-le el s a e.
Fig. 3(b) illus a es he s uc u e o da a ames in he
o wa d link, i.e. owa ds he senso a ay. They a e used o
configu e he neu al eco ding senso a ay. A o wa d ame
229
CRCP eamble
s ab RTCAL
Command Da a
5145
23
Tb0
PW
Tb1=2*Tb0
PW
‘0’ ‘1’
a)
b)
P eamble CRC
872 5
Da a
c)
op
1s cal O/M LP HP h_op
6 3
22 1
2nd cal O/M PGAcell_selec ion
8 32 1
signal
acking
O/M SP
4 721
TH
VTH
ea u e
ex ac ion
O/M S/T
2 7
23
o he _op
VADC1
HP
LP
PGA VTH
2
33749
8878
8
M
M
M
VADC2
8
VADC8
“01010101”
ID CELL
8
62
ID CELL
ID CELL VP1 VP2 VTH 123 ille
88 17
62
62
40
ille
signal
acking
ea u e
ex ac ion
calib a ion
Figu e 3. Communica ion p o ocol o he p oposed sys em: a) PIE o ma ,
b) o wa d ame, c) backwa d ame.
consis s o 24-bi , including p eamble (5 bi ), command (14
bi ) and cyclic edundancy check (CRC) wo d (5 bi ). As
shown in Fig. 3(b), he s uc u e and pa ame e s included in
he command wo d depends on he selec ed ope a ion mode.
Fig. 3(c) shows he s uc u e o da a ames in he backwa d
link, i.e. om he senso a ay o he ou side. The backwa d
ame is 85-bi long and includes a fixed 8-bi p eamble
“01010101”, ollowed by a 72-bi ou pu da a se , and com-
ple ed by a 5-bi CRC wo d. The fi s 8-bi o he ou pu da a
se in o m abou he ope a ion mode (2-bi ) and he channel
iden ifica ion (6-bi ). In he signal acking mode, he sys em
collec s he sampled da a in g oups o eigh (by column o
ow, depending on he selec ed op ion), and only he fi s
channel o he column/ ow has o be iden ified. In he ea u e
ex ac ion mode, he ou pu da a se is o med by h ee by es
o empo al in o ma ion, wo by es o ampli ude in o ma ion
and 7-bi ep esen ing he applied h eshold ol age. In he
calib a ion mode, he sys em gene a es 15-bi which in o m on
he se ings o he bandpass fil e , PGA and h eshold ol age.
III. TELEMETRY UNIT
Fig. 4 shows he schema ics o he powe and da a eleme y
uni . I is based on induc i e link echniques and ope a es in he
wo ldwide a ailable ISM band cen e ed a 40.68MHz. Da a e-
cep ion employs (OOK) modula ion whe eas da a ansmission
is accomplished by modula ing he ampli ude o he ca ie
by means o a swi chable an enna ma ching ne wo k d i en
by he digi al p ocesso . In his la e case, he modula ion
dep h is less han 50% and he ou pu da a is encoded using
a Manches e encode .
No shown in he figu e, he eleme y uni also includes
a iming eco e y ci cui which ex ac s he 4MHz clock o
Modula o Rec i ie
dou
demodula o
ec i ie
dem_en din
Demodula o
V ec
Manches e
Encode
Induc i e
Coupling
Ex e nal
Uni
Figu e 4. Schema ic o he eleme y on -end.
4.6mm
4mm
F C S G
400 m
DIGITAL
PROCESSOR
LNA,
Band-Pass
Fil e
PAD
PGA - ADC
400 m
Figu e 5. Layou o he mul ichannel neu al senso .
he sys em om he incoming RF signal, which is also used o
modula e he backwa d link. This is accomplished by means o
di ide by 2 ci cui s based on single- ansis o -clocked dynamic
la ches [6].
The eleme y uni also includes a powe managemen
ci cui y which ha es ene gy om he induc i e link using
a ec ifie . Analog and digi al supply lines o 1.2V a e ob-
ained om co esponding egula o s, while a bandgap ci cui
gene a es he analog ol age e e ences. The e ficiency o he
ec ifie is 60% a 1mW RF inpu powe .
IV. POST-LAYOUT RESULTS
Fig. 5 shows he layou o he p oposed sys em. I has
been designed in a 6M2P 0.13μm s anda d CMOS echnology.
Each channel includes an in e nal pad o flip-chip connec ion
o a mic oelec ode. Fo he sake o es abili y, he channel
inpu nodes can be also accessed om an ex e nal pad ing.
Clamp cells a e placed along he chip pe iphe y o p o ec
he mic oelec ode nodes om ESD damages. The sys em
occupies 18.4mm-sq.
Fig. 6 illus a es he ope a ion o he adap i e h eshold
algo i hm implemen ed in he local digi al p ocesso o he
channels. The signal- o-noise a io o he neu al signal has
been in en ionally a ied o be e app ecia e he e olu ion o
he h eshold de ec ion le el. As can be seen, he algo i hm
eac s in less han 0.5s o changes in he backg ound noise.
Fig. 7 illus a es he sys em ope a ion in he ea u e ex ac-
ion mode. Do s ep esen he spikes de ec ed by he neu al
230
0 5 10 15 20 25 30
0
50
100
150
200
250
ime (s)
Code
Figu e 6. Adap i e h eshold ol age algo i hm: Neu al signal (blue), ol age
h eshold ( ed), noise le el (yellow).
0 1 2
0
100
200
ime (ms)
200 202 204 206
0
10
20
30
40
50
60
0100 200 300 400
0
20
40
60
Cell numbe
ime (ms) ime (ms)
C11
C25
C39
C63
C33
C51
C1 C25 C39 C63 C33 C51
201 202 203 204 205 206
'2'3
'1
spike
Code
0 1 2
0
100
200
ime (ms)
'2'3
'1
spike
Code
11101011 00111001 0100000 00000110 00010000 00010100
00011011 11001000 0100000 00000111 00010001 00010111
Vp1 Vp2 V h '1'2'3
Vp1 Vp2 V h '1'2'3
199.5 201.5
200.5
204 206
205
ime (ms)
Figu e 7. Da a ou pu s eam unde ea u e ex ac ion mode.
a ay in a ime slo o 500ms. Once a spike is de ec ed in a
channel and i s PWL ep esen a ion de i ed (47-bi s, as figu e
7 illus a es), he ea u e ec o is s o ed in he associa ed
EBPU. The main digi al p ocesso cyclically eads he EBPUs
e e y 237μs. Conside ing he 85-bi leng h o he backwa d
ame de ailed in Sec ion II, he sys em equi es 21.25μs o
ansmi he in o ma ion o one spike a 4MHz. The e o e, we
can calcula e he maximum possible delay by summing up he
delay o he EBPU eading and he ansmission delay, which
esul s 258.25μs. This is much lowe han a ypical spike
du a ion (a ound 2ms) and, o cou se, much lowe han he
ime basis o fi ing occu ences. I means, ha no in o ma ion
is los no e en in he unlikely case all he channels fi e a he
same ins an (only a small delay no la ge han abou 10% he
du a ion o a spike could be obse ed in some o he eco ds).
The pe o mance o mos o he blocks comp ised in he
channels (LNA, fil e and ADC) we e measu ed and epo ed
in [4]. The new channel implemen a ion in his pape also
includes an addi ional digi al p ocesso which, oge he wi h
he needed bu e s o communica e along he a ay, ise
he powe consump ion pe channel o 4.54μW. F om he
simula ed powe consump ion i can be ex a ed ha mos o
he powe is consumed by he neu al channels (290.56μW).
The main digi al p ocesso and EBPUs, which make ex ensi e
use o clock ga ing and clock equency di ision echniques,
consumes 40μW(5μW o hem dissipa ed by leakage cu -
en s). Bandgap e e ences, egula o s and cu en con eyo s
Table I
PERFORMANCE SUMMARY AND COMPARISON
[1] [2] [3] This wo k
Technology (μm) 0.18 0.18 0.13 0.13
Supply ol age (V) 1.8 1.8/1 0.5 1.2
Numbe o channels 16 32 16 64
To al powe (μW) 680 325 18 377
Powe / channel (μW) 42.5 10.1 1.13 5.9
High pass eq. (Hz) 100 350 400 200
Low pass eq. (kHz) 9.2 12 7.5 6.9
Inpu e . noise (μV ms ) 5.4 5.4 5.32 3.8
NEF 4.9 4.4 3.09 2.16
ENOB (bi s) 7 7.65 7.32 7.65
Sampling eq. (kS/s) 30 31.25 30 27/90
Da a bi a e educ ion Yes No No Yes
consume 32μW. The clock eco e y block, he Manches e
encode and he demodula o equi e, espec i ely, 12.5μW,
1.5μW and 400nW. All in all, he o al powe consump ion o
he sys em sums 377μW.
Table I summa izes he pe o mance o he neu al eco ding
sys em and compa es i wi h some s a e-o - he-a wo ks. No e
ha he p esen ed wo k p esen s one o he lowes powe
dissipa ion pe channel, e en hough i is he only one ha
includes a wi eless communica ion ci cui y.
V. CONCLUSIONS
A 64-channel neu al a ay wi h embedded da a educ ion
echniques, ab ica ed in a s anda d CMOS 130nm p ocess,
has been p esen ed. Inspi ed by RFID sys ems, an induc i e
link is used o bo h powe ing he implan and ans e ing
in o ma ion o/ om an ex e nal uni placed on he head. A
dis ibu ed digi al signal p ocessing app oach, wi h asks a
channel- and a ay le els, has been ound an e ficien solu ion
o educing he powe consump ion o he SoC and sim-
pli ying communica ions h ough he a ay. The o al powe
consump ion o he sys em has been es ima ed in 377μW om
a nominal ol age supply o 1.2V, i.e., abou one o de o
magni ude below p io a .
ACKNOWLEDGMENTS
This wo k has been suppo ed by he Spanish Minis y o
Science & Inno a ion unde g an TEC2009-08447 and he
2007-2013 FEDER P og am.
REFERENCES
[1] B. Gosselin e al., “A mixed-signal mul ichip neu al eco ding in e ace
wi h bandwid h educ ion,” IEEE T ans. Biomed. Ci cui s, ol. 3, no. 3,
pp. 129–141, 2009.
[2] W. Wa anapani ch and R. Sa peshka , “A low-powe 32-channel digi ally
p og ammable neu al eco ding in eg a ed ci cui ,” Biomedical Ci cui s
and Sys ems, IEEE T ansac ions on, ol. 5, no. 6, pp. 592–602, 2011.
[3] L. Wen-Sin, Z. Xiaodan, and L. Yong, “A 0.5- 1.13uw/channel neu-
al eco ding in e ace wi h digi al mul iplexing scheme,” in ESSCIRC
(ESSCIRC), 2011 P oceedings o he, pp. 219–222.
[4] A. Rod iguez-Pe ez, J. Ruiz-Amaya, M. Delgado-Res i u o, and
A. Rod iguez-Vazquez, “A low-powe p og ammable neu al spike de ec-
ion channel wi h embedded calib a ion and da a comp ession,” IEEE
T ans. Biomed. Ci cui s, ol. 6, no. 2, pp. 87 –100, ap il 2012.
[5] A. Rod iguez-Pe ez e al., “A sel -calib a ion ci cui o a neu al spike
eco ding channel,” in P oc. IEEE Biomed. Ci c. and Sys ems Con .,no .
2011, pp. 464 –467.
[6] J. Yuan and C. S ensson, “New single-clock cmos la ches and flipflops
wi h imp o ed speed and powe sa ings,” IEEE J. Solid-S a e Ci c.,
ol. 32, no. 1, pp. 62–69, 1997.
231