Enhanced Sensitivity of CMOS Image Sensors by Stacked Diodes

8448 IEEE SENSORS JOURNAL, VOL. 16, NO. 23, DECEMBER 1, 2016
Enhanced Sensi i i y o CMOS Image
Senso s by S acked Diodes
Juan An onio Leñe o-Ba dallo, Manuel Delgado-Res i u o, Senio Membe , IEEE,
Rica do Ca mona-Galán, Senio Membe , IEEE, and Ángel Rod íguez-Vázquez, Fellow, IEEE
Abs ac —We ha e in es iga ed and compa ed he
pe o mance o pho odiodes buil wi h s acked p/n junc ions
ope a ing in pa allel e sus con en ional ones made wi h
single p/n junc ions. We p opose a me hod o cha ac e ize and
compa e pho odiodes sensi i i y. Fo his pu pose, a dedica ed
chip in he s anda d AMS 180-nm HV echnology has been
ab ica ed. Fou di e en senso s uc u es we e implemen ed
and compa ed. Expe imen al esul s a e p o ided. Measu emen s
show sensi i i y enhancemen anging om 55% o 70% wi hin
he 500–1100 nm spec al egion. The la ge inc emen is
happening in he nea in a ed band (up o 62%). Such
esul s make s acked pho odiodes sui able candida es o
he implemen a ion o pho osenso s in ision chips designed
o s anda d CMOS echnologies.
Index Te ms—S acked pho odiodes; spec al sensi i i y;
pho odiode cha ac e iza ion; e en -based ision senso s; NIR.
I. INTRODUCTION
STANDARD CMOS echnologies o e di e en al e na-
i es o he implemen a ion o embedded pho odiodes,
among which he n-well/p−subs a e junc ion is conside ed
a good choice owing o sensi i i y, SNR and a ea con-
side a ions [1]–[4]. Howe e , as a di e ence o specialized
CIS (CMOS Image Senso ) echnologies [5], whe e de ailed
cha ac e iza ion da a o pho o-senso s and pixels mac o-cells
a e a ailable o IC designe s, in s anda d CMOS pho odiode
cha ac e iza ion da a a e no a ailable. Hence, pe o ming such
cha ac e iza ion is usually a equi ed s age o he design o
sma image s and/o ision sys em-on-chips using s anda d
CMOS.
Al hough CIS echnologies ea u e be e pho o-senso s han
s anda d ones, he a ionale o using he la e include lowe
p oduc ion cos and la ge lexibili y o he inco po a ion
o complex logic ci cui y. Hence, hey may be a good
choice o applica ions whe e emphasis is on ision asks,
Manusc ip ecei ed May 23, 2016; accep ed Sep embe 14, 2016. Da e o
publica ion Sep embe 20, 2016; da e o cu en e sion No embe 4, 2016.
This wo k was suppo ed in pa by he Spanish Minis y o Economy and
Compe i i eness unde G an TEC2012-33634 and G an TEC2015-66878-
C3-1-R, Co-Funded by ERDF-FEDER, in pa by Jun a de Andaluca CEICE
unde G an TIC 2012-2338 (SMARTCIS-3D), and in pa by ONR unde
G an N000141410355 (HCELLVIS). The associa e edi o coo dina ing he
e iew o his pape and app o ing i o publica ion was D . Shoushun Chen.
J. A. Leñe o-Ba dallo is wi h he Uni e si y o Cádiz, Cádiz 11519, Spain
(e-mail: juanan onio.[email p o ec ed]).
M. Delgado-Res i u o, R. Ca mona-Galán, and Á Rod íguez-Vázquez
a e wi h he Ins i u e o Mic oelec onics o Se ille (IMSE-CNM),
CSIC-Uni e sidad de Se illa, Se ille 41092, Spain (e-mail: mandel@imse-
cnm.csic.es; ca [email protected]; [email protected]).
Digi al Objec Iden i ie 10.1109/JSEN.2016.2611759
i.e. on ex ac ing in o ma ion om he senso da a, ins ead o
image ep oduc ion [6]–[9]. Since la ges possible pho ode-
ec o s sensi i i y is equi ed o hese ision senso s we may
ake ad an age o he deep n-wells and/o p-wells a ailable in
mode n echnologies o build s acked pho odiodes.
As compa ed o non-s acked con en ional s uc u es,
s acked ones ha e he po en ial o inc eased sensi i i y
and spec al selec i i y. This la e ea u e e e s o de ec-
ion o pho ons o di e en equencies by using junc-
ions placed a di e en dep hs wi hin he semiconduc o ,
exploi ing he ac ha abso p ion dep hs depend on pho on
wa eleng hs [10], [11]. By placing p/n junc ions a di -
e en dep hs, he o e all spec al esponse o whi e ligh
is mo e balanced han using a single p/n junc ion. Each
s acked pho odiode will ha e a sensi i i y peak a a di e en
wa eleng h. Hence, he esul an spec al sensi i i y will be
la e . Fu he mo e, he o e all pho ocu en will be highe
because se e al pho odiodes will ope a e in pa allel. Since
he s acked pho odiodes sha e he same deep n-well, he a ea
consump ion is simila o he a ea equi ed o ab ica e a single
diode.
The use o s acked pho odiodes o ision senso s has
been explo ed by di e en au ho s [6]–[8], [12]. The ansien
esponse o hese di e en s acked pho odiodes ha e been ana-
lyzed o communica ions applica ions; o ins ance, [13], [14].
Image senso s wi h s acked diodes a e also comme cialized by
Fo eon [11]. Rega ding non-s acked spec al disc imina ion
o CMOS-compa ible pho odiodes, pho ode ec o s p ope ies
ha e been epo ed elsewhe e [1]–[3]. Howe e , o he bes o
ou knowledge, he e a e no esul s published ye on he com-
pa ison o di e en CMOS-compa ible s acked pho odiodes
op ions. Besides, while mos pape s desc ibe s acked junc ions
ope a ing indi idually as o p ese e colo in o ma ion, he e
a e no sys ema ic da a ega ding pa allel ope a ion aimed o
sensi i i y enhancemen .
This pape is aimed o compa e he pe o mance o ou
di e en CMOS-compa ible pho odiodes. Two o hem a e
buil by s acking di e en diodes in ol ing deep n-well and
deep p-well laye s. The o he wo a e classic pho odiodes
a ailable in s anda d CMOS echnologies, i.e. diodes ei he
made wi h n-well/subs a e junc ion o wi h a n+/p−sub-
s a e junc ion. The pape also desc ibes a me hod and an
associa ed, easy o implemen embedded ci cui y o compa e
pho odiodes’ e iciency by a a he simple, indi ec measu e-
men p ocedu e. Expe imen al esul s compa ing all o hem
1558-1748 © 2016 IEEE. Pe sonal use is pe mi ed, bu epublica ion/ edis ibu ion equi es IEEE pe mission.
See h p://www.ieee.o g/publica ions_s anda ds/publica ions/ igh s/index.h ml o mo e in o ma ion.
LEÑERO-BARDALLO e al.: ENHANCED SENSITIVITY OF CMOS IMAGE SENSORS BY STACKED DIODES 8449
a e p o ided. De ails o he expe imen s and he expe imen al
se up necessa y o un he expe imen s a e desc ibed.
The a icle is o ganized as ollows: Sec ion II desc ibes
he di e en p/n junc ions a ailable in he AMS 180nm
HV echnology and how hey ha e been in e connec ed o
c ea e ou di e en kinds o pho odiodes. The ci cui y used
o de e mine i s sensi i i y is shown oo. In Sec ion III,
he expe imen al se up is desc ibed. Mo eo e , expe imen al
esul s a e p esen ed. Finally, Sec ion IV discusses he expe -
imen al esul s and he pho odiodes design ade-o s.
II. CIRCUIT DESCRIPTION
Ou a ge is o compa e he sensi i i y —pixel pe o mance
in Vol s pe uni a ea and ime pe inciden ligh powe pe
uni a ea in (V.cm−2.sec−1/W.cm−2), o he ou di e en
s uc u es shown in Fig. 1. Colo ed a ows ha e been added
o illus a e he abso p ion dep h o di e en colo s [10].
The i s wo pho odiodes a e c ea ed combining di e en
p/n junc ions wi h a deep n-well. The wo o he s a e con en-
ional pho odiodes a ailable in s anda d CMOS echnologies,
i.e. a n-well/p−subs a e junc ion and a n+/subs a e junc ion.
Le us i s conside Fig. 1.a (le ) whe e h ee p/n junc ions
a e s acked. Since abso p ion dep h is lowe o smalle
equencies, junc ions a he bo om a e expec ed o be mo e
sensi i e o wa eleng hs in he nea in a ed band, close o
he ed colo . The op ones will be mo e sensi i e o sho e
wa eleng hs [10]. I we connec he diodes o ope a e in
pa allel as shown a he igh o Fig. 1.a (D1), we ob ain a
wo old bene i :
•Fi s he esul an spec al esponse will be mo e homo-
geneous han using an unique diode, i.e. he sensi i i y
cu e o he esul an pho odiode will be la e .
•Second, he sensi i i y o whi e ligh will be highe ,
because h ee pho odiodes will be ope a ing in pa allel
a di e en wa eleng hs.
These a e in e es ing ea u es o he design o ision
senso s de ised o ope a e in he whole isible spec um.
Fig. 1.b depic s a second s acked pho odiode (D2) ha
employs also deep n-well laye , bu whe e he n+di usion on
op has been emo ed o c ea e wo s acked pho odiodes. This
con igu a ion is expec ed o ha e highe sensi i i y ope a ing
wi h longe wa eleng hs han he one o Fig. 1.a. The layou
design is simple han he p e ious one and he minimum pi ch
ha can be achie ed is lowe .
Fig. 1.c displays a pho odiode c ea ed wi h a n-well/p−
subs a e junc ion (D3). This is usually he p e e ed choice
when implemen ing image senso s ope a ing in he isible
band. This pho odiode can be buil in any s anda d CMOS
echnology and ea u es good spec al sensi i i y [1]–[4].
Fig. 1.d displays he las pho odiode implemen ed o his
s udy (D4). I is c ea ed wi h he junc ion o a n+di usion
and a p−subs a e di usion. Al hough his choice adi ionally
o e s poo sensi i i y, i can be in e es ing o applica ions ha
equi e good sensi i i y in he blue.
As pho odiodes spec al sensi i i ies mus be cha ac e ized
p io o using hem wi h a non CIS echnology. Howe e ,
measu ing pho ocu en s o pho odiodes wi h a small pi ch is
Fig. 1. (a) T iple-junc ion s acked pho odiodes, in e connec ion be ween
hem, and ci cui model. (b) Double-junc ion s acked pho odiodes, in e con-
nec ion be ween hem, and ci cui model. (c) N-well/p−subs a e junc ion
pho odiode. (d) n+/p
−subs a e junc ion pho odiode.
Fig. 2. In eg a e-and- i e ci cui y. Each pho odiode (D∗) is connec ed o an
independen I&F ci cui ha pulses wi h a equency ha is p opo ional o
illumina ion. An analog bu e is connec ed o in eg a ion capaci ance node o
moni o he ansien ol age a his poin . T ansis o sizes a e (W/L, µm/µm):
Mp1=0.5/0.7, Mp2=10/1. C1=40 F.
challenging [15], and dedica ed equipmen mus be used. Also
since pads leakage a ec s he measu emen s, emo ing pads
p o ec ions is necessa y o p ecise measu emen s. Ano he
obs acle comes om he ac ha small a ia ions o ou pu
esis ances p oduce measu emen misma ch.
We p opose an al e na i e app oach ha employs simple
ci cui y ha can easily coexis wi h a pixel a ay in he
8450 IEEE SENSORS JOURNAL, VOL. 16, NO. 23, DECEMBER 1, 2016
same chip. I has low a ea equi emen s and only equi e
h ee pads o gauge he pho odiodes sensi i i ies. Each se
o pho odiodes is connec ed o an in eg a e-and- i e (I&F)
ci cui [16] as is depic ed in Fig. 2. This ci cui is an as able
oscilla o ha swi ches be ween wo s a es a he pace de ined
by he inpu pho ocu en . Ini ially, he ese signal is ac i a ed
o se he ol age a C1 oo VDD. Once he ese is eleased,
he ol age a C1dec eases wi h a s ep p opo ional o he
pho ocu en . Whene e he ol age in e sec s Vbo i, heOTA
swi ches o he ini ial s a e and a new cycle s a s. The digi al
bu e loca ed a e he opamp is needed o inc ease swi ching
speed and o s abilize he ope a ion. The oscilla ion pe iod is
gi en by his equa ion:
T=C·(VDD −Vbo )
Iph +Ida k −Ileakage
+Td+T ese (1)
Whe e Ida k is he pho odiodes’ da k cu en . Tdis he
digi al bu e delay, and T ese is he ime needed o ese
he in eg a ion capaci ance, C=Cph +C1. Acco ding o
Mulle and Kamins [17], Ida k can be exp essed as:
Ida k =Aj·q·ni·W
2·τ0(2)
I depends on he e ec i e li e ime o mino i y ca ie s, τ0,
ha has a s ong dependence wi h empe a u e; he wid h o
he deple ion egion, W; he doping, ni; and he e ec i e a ea
o in luence o he inciden ligh , Aj. None o hese pa ame e s
is disclosed by he ound y. Ileakage is he ansis o s leakage
in oduced by ansis o s Mp1and Mp2in Fig. 2. I can be
es ima ed wi h he BSIM model equa ion:
Ileakage =I0·e
Vgs−V h
nUT·1−e−Vds
UT,(3)
wi h
I0=WμoCoxU2
Te1.8
L
Pho odiodes dimensions we e 16µm×13µm. We con-
nec ed wo o hem in pa allel. Acco ding o he ansis-
o s models p o ided by he echnology, Ileakage ≈65pA.
Ida k depends on empe a u e, he e e se bias ol age, and
he pho odiode ype. Fo ins ance, acco ding o he diode
model p o ided o he n-well/p−sub diode, wi h a e e se
bias ol age equal o VDD =5V, and unde low illumi-
na ion condi ions wi h whi e ligh (0.8lux), Ida k =20pA,
Iph =50pA. Hence, he ci cui o Fig. 2 elici s oscilla ions
because Iph −Ida k >Ileakage. Unde a e age indoo illu-
mina ion condi ions, he chip illuminance is usually much
highe han 0.8lux. Thus, i can be neglec ed he impac o
he da k cu en , i. e. Iph Ileakage −Ida k.Fo he es
o pho odiodes, we do no ha e models. Howe e , o he
illumina ion alues selec ed o measu e he sensi i i y in he
pape , we obse ed a linea ela ionship be ween he chip
illuminance and he ou pu equency. The e o e, i can be
assumed ha Iph −Ida k >Ileakage oo.
Td≈20ns and T ese ≈1.3ns is he amoun o ime equi ed
o ese he in eg a ion capaci ance, C=C1+Cph. When he
oscilla ion pe iod is unde a e age illumina ion condi ions, i s
alue is in he o de o milliseconds, and can Tdand T ese
Fig. 3. Schema ics o he OTAs. T ansis o sizes a e (W/L, µm/µm):
Mp1=Mn2=5/1, Mn1=Mp2=7.5/1, Mn3=Mp3=5/1,
Mn4=Mn5=Mp4=Mp5=5/2, Mp6=Mp7=Mp8=Mp9=2.5/1,
Mn6=Mn7=Mn8=Mn9=3/1. VDD =5V. I s powe consump ion is
app oxima ely 90µA.
can be neglec ed. The e o e, Equa ion 1 can be simpli ied as
ollows:
T≈C1+Cph·(VDD −Vbo )
Iph
=C1+Cph·V
Iph (4)
Acco ding o Equa ion 4, he equency o he ou pu pulses
is p opo ional o he inpu pho ocu en . The sensi i i y o
each pho odiode is gi en by:
S=VDD −Vbo
T·P0
∝VDD −Vbo
T=V
T=Iph
C1+Cph (5)
Whe e P0is he inciden op ical powe . All he pho odiodes
ecei e he same powe . Since Vis always a cons an , he
sensi i i y will be p opo ional o he oscilla ion equency.
No e, ha he oscilla ion equency depends on he a io
Iph/Cph o each pho odiode, o a gi en inciden powe .
In ou implemen a ion, we made C1=40 F, ha is a alue
la ge enough o ha e a good ma ching be ween di e en
capaci ances. Thus, measu ing he oscilla ion equencies and
he inciden ligh powe , i is possible o gauge he pho odiodes
sensi i i ies. No e ha , acco ding o Equa ion 5, i is no
necessa y o measu e he inciden op ical powe i ou a ge is
only o de e mine wha pho odiode is mo e sensi i e o ligh .
Fig. 3 shows he implemen a ion o he OTAs in Fig. 2.
Thei design is an adap ed e sion o he o iginal a chi ec u e
p oposed by Lu [18]. I has wide dynamic ange ope a ion and
can d i e la ge ou pu loads. I does no equi e any ex a pad
o biasing. Ou a ge was o minimize he numbe o pads,
a oiding ex a chip pins o biasing. One OTA was con igu ed
as a simple compa a o . The o he one, ha is connec ed
o an ou pu analog pad, unc ions as an analog bu e o
scan he ou pu ol ages a he in eg a ion capaci ances. Fo
a ai compa ison o he pho odiodes spiking equencies,
V=VDD −Vbo in Equa ion 4, mus be exac ly he
same o ou he di e en I&F ci cui s. The compa a o s a e
expec ed o ha e DC o se a ia ions in he o de o mV.
To be su e ha he e is no a ia ion o Vbe ween he
LEÑERO-BARDALLO e al.: ENHANCED SENSITIVITY OF CMOS IMAGE SENSORS BY STACKED DIODES 8451
Fig. 4. Chip mic opho og aph. Chip dimensions a e 1050µm×850µm.
Pho odiodes dimensions we e 16µm×13µm. Fou pai s o pho odiodes we e
implemen ed. (a) En i e chip. (b) De ail o he ou pai s o pho odiodes.
I&F ci cui s, Vcan be measu ed wi h he sou ce ollowe
ou pu (Vscaniin Fig. 2) and uned acco dingly adjus ing Vbo i.
We implemen ed ou in eg a e-and- i e ci cui s in o al, co -
esponding o each pho odiode ype in Fig. 1.
III. EXPERIMENTAL RESULTS
A. Expe imen al Se up and Ci cui Ope a ion
Fig. 4.a shows a mic opho og aph o he chip. I s dimen-
sions a e 1050µm×850µm. All he pho odiodes ha e exac ly
he same sizes in o de o compa e hem. Since we expec ed
low sensi i i y a ce ain wa eleng hs, specially o he n+/p
−
subs a e junc ion pho odiode (D4) wi hin he NIR band,
we implemen ed pho odiodes wi h la ge pi ches o be able o
ope a e wi h ou expe imen al se up and ake measu emen s
in he isible band. Thei sizes a e 16µm×13µm. We ha e
implemen ed wo diodes o each ype (see Fig. 4.b). They a e
connec ed in pa allel o one I&F ci cui like he one depic ed in
Fig. 2. Each in eg a e-and- i e ci cui implemen a ion occupies
90µm×60µm and equi es only wo pads o i s implemen-
a ion (Vscani,andVbo isignals). The ese signal VRESET can
be sha ed by all he I&F ci cui s.
Fig. 5 displays he ypical ansien ol ages a he com-
pa a o ’s inpu o he I&F ci cui depic ed in Fig. 2 when he
pho odiodes a e exposed o indoo illumina ion o app oxi-
ma ely 400lux gene a ed wi h a whi e ligh sou ce. The analog
bu e depic ed in Fig. 3 was connec ed o C1 o scan he an-
sien ol age a ia ions. Small a ia ions o he compa a o s’
h esholds a e expec ed due o misma ch. Typically he e a e a
ew milli ol s o se be ween di e en compa a o s. To ensu e
be o e gauging he diodes’ sensi i i y, ha Viwas he same
o he ou in eg a e-and- i e ci cui s, he ol ages alues o
Vbo iwe e uned acco dingly o each compa a o .
Du ing he expe imen s, all he pho odiodes we e exposed
o he same ligh in ensi y a cons an empe a u e. Mea-
su emen s we e epea ed se e al imes and a e aged. Fig. 6
shows he expe imen al se up. A whi e ligh O iel/Newpo
66884 ungs en lamp was employed as con olled ligh sou ce.
I s ligh beam is spli in o wo ligh beams wi h he same
powe inside an in eg a ing sphe e. The i s one is di ec ed o
Fig. 5. Typical in eg a e-and- i e ansien ol ages a capaci o C1in he
oscilla o depic ed in Fig. 2. Pho odiodes we e exposed o indoo illumina ion.
Ou pu equencies a e p opo ional o hei pho ocu en s. Vican be
adjus ed independen ly o each oscilla o .
Fig. 6. Expe imen al se up o cha ac e ize he pho odiodes. An O iel/
Newpo 66884 sou ce was used as a whi e ligh sou ce o he expe imen s.
An in eg a ing sphe e was placed o spli he ligh beam in o wo independen s
beams. One o hem was sen o a ligh powe me e . The o he one was sen
o he senso h ough a di use o assu e ha all he pho odiodes ecei e he
same amoun o powe . In be ween he ligh sou ce and he in eg a ing sphe e,
we placed wo il e holde s o place colo and neu al densi y il e s. Main
componen s ha e been highligh ed.
a Newpo 1930-C ligh powe me e o measu e he powe
o he inciden ligh . The second one is di ec ed o he chip
h ough a di use o assu e ha all he pixels ecei e exac ly
he same ligh in ensi y. Hence, i is always possible o moni o
he powe o he inciden ligh on chip. The e a e wo il e
8452 IEEE SENSORS JOURNAL, VOL. 16, NO. 23, DECEMBER 1, 2016
Fig. 7. Spiking equencies e sus illumina ion alues. Pho odiodes we e
illumina ed wi h a whi e Lambe ian sou ce.
holde s in he pa h in be ween he ligh sou ce and he
in eg a ing sphe e. I s pu pose is o place disc e e il e s o
ei he a enua e o il e he inciden ligh when necessa y,
depending on he expe imen . The se up is obus o possible
a ia ions o he il e s ansmission coe icien s, and he lamp
powe i adiance a ia ions a di e en wa eleng hs.
B. Compa ison o Diodes’ Sensi i i y o Whi e Ligh
To compa e he diodes’ sensi i i y o whi e ligh ,
we exposed he chip o he whi e Lambe ian sou ce
O iel/Newpo 66884. Neu al densi y il e s we e employed
o a enua e he ligh in ensi y emi ed by he ligh sou ce.
Measu emen s we e epea ed o di e en illumina ion alues
a cons an empe a u e. The ou pu spiking equency o each
pho odiode o each illumina ion alue has been plo ed in
Fig. 7. E o ba s indica e he s anda d de ia ion be ween
measu emen s. Fo all he diodes, he e is a linea dependence
be ween illumina ion and he i ing equency and he illu-
mina ion alues. Hence, we can assume ha Iph −Ida k >
Ileakage. Acco ding o Equa ion 5, he a io be ween wo
diodes i ing equencies is p opo ional o he a io be ween
pho odiodes’ sensi i i ies, i.e.:
1
2
=S1
S2=Iph1
Iph2
·C1+Cph1
C1+Cph2
(6)
A e analyzing he esul s, he double diode (D2) made wi h
deep p-well/deep n-well and a deep n-well/p−subs a e hap-
pens o be he mo e e icien one. In second place, i comes he
iple-junc ion pho odiode, D1 (n+/deep p-well, p-well/deep
n-well and a deep n-well/p−subs a e junc ions). The con-
en ional diode wi h a n-well/p- subs a e (D3) junc ion o e s
good pe o mance in he whole isible spec um, bu i has
less sensi i i y han he ones buil wi h s acked pho odiodes
Fig. 8. Pho odiodes spec al sensi i i y. Disc e e op ical il e s we e in o-
duced o ob ain each measu emen . The DP/DN/p−subs a e pho odiode (D2)
has a he highes sensi i i y a 900nm.
ope a ing in pa allel. The n+/p−subs a e diode (D4) is he
one wi h less sensi i i y, as i was expec ed.
I we compu e he a ios be ween he i ing equencies, wi h
he da a o Fig. 7, we ob ain: S2/S1=1.25, S2/S3=1.55,
and S2/S4=35. We can s a e ha he new pho odiodes
made wi h a deep n-well o e mo e sensi i i y han he classic
ones. Hence, echnologies ha o e a deep n-well laye could
bene i o i . We could expec mo e sensi i i y o he iple
junc ion pho odiode (D1). Howe e i s pe o mance is sligh ly
wo se han he one o he double-junc ion diode. The easons
can be ha he op ex a diode p esen s in he iple-junc ion
diode o e s poo esponsi i y and adds an ex a junc ion
capaci ance. Me al lines, and ias in ol ed in i s layou design
also limi he pe o mance.
C. Spec al Sensi i i y
In o de o de e mine he spec al diode sensi i i y, we
exposed hem o colo ed ligh . To do so, we placed colo
disc e e il e s in he lens holde s in be ween he whi e ligh
sou ce and he pho odiodes as i is shown in Fig. 6. Fil e s
ha e na ow band spec a o app oxima ely 20nm cen e ed a
ce ain wa eleng hs. Inciden powe on chip was measu ed
o each il e o de e mine he spec al sensi i i y o each
pho odiode acco ding Equa ion 5. No e ha o ake his
measu emen s, i is necessa y o measu e he inciden powe
because all he il e s do no ha e he same ansmission
coe icien s, and he ligh sou ce spec um is no o ally
la .
Fig. 8 displays he he sensi i i y o each pho odiode o
each wa eleng h. As we we e expec ing, he n+/p−sub-
s a e diode (D4) has be e pe o mance o sho e wa e-
leng hs. I s sensi i i y is lowe han he o he pho odiodes
o all he wa eleng h alues. The double- and iple-junc ion

LEÑERO-BARDALLO e al.: ENHANCED SENSITIVITY OF CMOS IMAGE SENSORS BY STACKED DIODES 8453
Fig. 9. Ra io be ween pho odiodes’ sensi i i ies. We ha e compa ed he
pho odiode wi h highe sensi i i y (D2, DP/DN/p−subs a e) o e he o he
h ee pho odiodes depic ed in Fig. 1 (D1, D3, and D4).
pho odiodes (D2 and D1) ha e mo e sensi i i y wi hin he
NIR band han o he s. The eason is ha he bu ied pho o-
diodes a e mo e sensi i e o longe wa eleng hs [10], [11].
Longe wa eleng h pho ons a e less ene ge ic. Hence, hey
ha e highe p obabili y o a eling deepe in o he c is al
be o e gene a ing elec on-hole pai s. Such elec ons can be
caugh easie i he p/n junc ions a e placed close o he
egions whe e hey a e gene a ed. Thus, by ha ing di e en
diodes whose deple ion egions a e a di e en dep hs, he
p obabili y o de ec ing pho ons a di e en wa eleng hs o he
isible and he NIR spec um is highe . The double-junc ion
pho odiode (D2) is he one wi h highe sensi i i y o all he
wa eleng hs alues. Howe e , i s shows simila pe o mance
han he iple-junc ion diode (D1) o sho e wa eleng hs
because i s op n+/deep p-well diode con ibu es mo e o he
esul an pho ocu en , inc easing he pho odiode’s sensi i i y.
The sensi i i y alues ha we measu ed single junc ion diodes
a e simila o he ones epo ed by o he au ho s. Fo ins ance,
o he n-well/p−sub diode (D3), he sensi i i y alues a e
alike o he epo ed by Ka ic e al. [3], using a s anda d
non-CIS echnology. Fo he s acked pho odiodes p oposed
in he pape , we did no ind equi alen esul s published
so a .
Fig. 9 shows he a ios be ween he pho odiodes sensi i i ies
o each wa eleng h. We ha e compa ed he sensi i i y o he
mos e icien diode, D2 (DP/DN/p−sub) o e he sensi i i y
o he o he h ee pho odiodes (D1, D3, and D4). I can be
Fig. 10. (a) RS-72 NIR il e measu ed spec al esponse. (b) Spiking
equencies e sus illumina ion alues. Diodes we e illumina ed wi h NIR
ligh be ween [750,1100]nm.
no iced ha i is he mos e icien o all he wa eleng hs. I
we compa e i s pe o mance o he classic n-well/p−subs a e
pho odiode sensi i i y (S3), we obse e ha he double-s acked
pho odiode (D1) has is specially mo e e icien wi hin he NIR
band. Fo ins ance, we measu ed o e 70% mo e sensi i i y a
900nm.
D. Pe o mance in he NIR Band
Since we obse ed a clea bene i o using s acked pho-
odiodes ope a ing wi hin he NIR band, we ha e compa ed
he diodes sensi i i y wi hin his spec al egion. To do so,
we employed a R72 il e om Edmund Op ics. I is a band-
pass il e wi h a cu on wa eleng h a ound 750nm. I s spec al
esponse was measu ed and i is shown in Fig. 10.a. Wi hin he
in e al [750, 1100]nm, i has la esponse. Radia ion below
700nm is ejec ed. We gauged he diodes spiking equencies
o di e en NIR ligh in ensi y alues. The a io be ween he
diodes sensi i i ies is cons an as long as Iph+Ida k >Ileakage.
8454 IEEE SENSORS JOURNAL, VOL. 16, NO. 23, DECEMBER 1, 2016
Resul s a e shown in Fig. 10.b. Ra ios be ween s acked diodes
i ing equencies and non-s acked diodes ones a e highe han
in Fig. 7, whe e diodes we e exposed o whi e ligh . The
mos sensi i e diode (D2) has 62% mo e sensi i i y han he
classic n-well/p- sub diode in he NIR band. The e o e, i is
ad an ageous o use s acked pho odiodes o applica ions ha
equi e good sensi i i y beyond he isible spec um [12].
E. S acked Diodes Design T ade-O s
The implemen a ion o s acked diodes in s anda d ab ica-
ion p ocesses has some ade-o s ha should be aken in o
accoun . Acco ding o ou expe ise implemen ing hem in di -
e en s anda d ab ica ion echnologies, we can ema k ha :
•S acked pho odiodes equi e a deep n-well laye o
hei implemen a ion. Usually, he minumum dis ances
be ween a deep n-well and a n-well a e highe han
be ween wo con en ional n-wells.
•Layou design is a bi mo e complica ed. i.e. he e a e
mo e laye s and design ules in ol ed in he pho odiode
composi ion.
•Some echnologies do no p o ide models o o he
bu ied pho odiodes.
•The minimum pi ch equi ed o place an deep n-well is
usually highe han o a con en ional n-well.
Pa icula ly, using s aked pho odiodes, i was challenging
o achie e in a pixel design a diode pi ch below 10µmin
he 180nm echnology chosen o conduc his esea ch wo k.
Nowadays almos all mode n s anda d ab ica ion echnologies
o e deep n-well implemen a ions. Al hough he possibili y o
alloca ing a deep n-well on a chip design was no ini ially
concei ed o c ea e s acked pho odiodes, we belie e ha
ound ies will exploi his po en ial soon, by elaxing he
design ules in ol ing deep n-well design. Thus, he minimum
pi ch o implemen s acked pho odiodes could be educed.
IV. DISCUSSION
Acco ding o he esul s o Fig. 7, Fig. 8, and Fig. 10, i can
be s a ed ha i is ad an ageous o use s acked pho odiodes
o implemen pho onic de ices in o de o inc ease hei
sensi i i y o ligh . The bene i o using hem is specially
ema kable wo king in he NIR band.
Compa ing he implemen ed pho odiodes depic ed in Fig. 1,
he double-junc ion pho odiode (D2) is he one ha o e s
be e pe o mance. Adding an ex a diode made wi h a
n+/deep p-well junc ion does no imp o e sensi i i y. The
a e se e al easons: his ex a diode has e y low quan um
e iciency in he isible spec um, due o he low a ea o i s
deple ion egion; i adds ex a complexi y o he layou (me al
lines and ias), and i has an ex a junc ion capaci ance. Classic
pho odiodes wi h simple p/n junc ions (D3 and D4) o e s less
sensi i i y. Ne e heless, hey can s ill be in e es ing (o he
only choice) in senso s ha equi e pixels wi h ine pi ch wi h
mo e elaxed layou design ules.
The esul s o his pape sugges ha he classic choice
o a n-well/p−subs a e diode (D3) is less compe i i e, in
e ms o sensi i i y, han he p oposed s acked pho odiodes.
The sensi i i y o whi e ligh can be inc eased by 55% using
a double-s acked pho odiode o e a con en ional diode made
wi h a n-well/p−subs a e junc ion. Fu he mo e, in he
NIR band he sensi i i y inc emen is highe . We measu ed
an o e all sensi i i y inc emen o 62% ope a ing he NIR
band wi h peaks o 70% a 900nm. These ea u es should
be aken in o accoun o maximize he pho odiodes’ sen-
si i i y when designing chip p o o ypes in a s anda d ab-
ica ion echnology. The ci cui y desc ibed o cha ac e ize
he pho odiodes is simple and does no equi e a lo o
a ea: only h ee pins a e necessa y o compu e he pho odi-
odes’ sensi i i y wi hou using dedica ed equipmen o gauge
pho ocu en s.
ACKNOWLEDGMENTS
The au ho s a e eally g a e ul o Miguel A. Lagos-Flo ido
o he PCB design.
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LEÑERO-BARDALLO e al.: ENHANCED SENSITIVITY OF CMOS IMAGE SENSORS BY STACKED DIODES 8455
Juan An onio Leñe o-Ba dallo ecei ed he M.Sc.
deg ee in elecommunica ions enginee ing and he
Ph.D. deg ee in mic oelec onics om he Uni e -
sidad de Se illa, Se ille, Spain, in 2005 and 2010,
espec i ely.
He se ed in se e al academic ins i u ions and
he semiconduc o indus y. In 2010, he was
a Pos -Doc o al Associa e a Yale Uni e si y,
New Ha en, CT, USA. F om 2010 o 2013, he was
a Pos -Doc o al Associa e a he Uni e si y o Oslo.
F om 2013 o 2016, he was a Pos -Doc o al Asso-
cia e a he Uni e sidad de Se illa, Spain. F om Ma ch 2016 o Augus 2016,
he was a Senio Enginee a Ch onocam Inc.
Since Sep embe 2016, he is an Assis an Teache a he Uni e si y o Cádiz,
Spain, whe e he eaches and conduc s esea ch.
D . Leñe o-Ba dallo’s main esea ch in e es s include add ess e en ep e-
sen a ion ision sys ems, ame-based ision senso s, sma senso s, wi eless
ision senso ne wo ks, signal p ocessing, and e y la ge scale in eg a ion
emula o s o biological sys ems. He has been a membe o he IEEE Senso y
Sys ems Commi ee since 2012.
Manuel Delgado-Res i u o (M’96–SM’12)
ecei ed he M.S. deg ee in physics and he Ph.D.
deg ee (Hons.) in physics elec onics om he
Uni e sidad de Se illa, Spain, in 1988 and 1996,
espec i ely. Since he Doc o a e, he has been
wo king wi h he Ins i u e o Mic oelec onics
o Se ille/CNM-CSIC (IMSE-CNM/CSIC). In
Sep embe 1999, he ob ained a pe manen posi ion
as “Cien í ico Ti ula del CSIC” (CSIC Tenu ed
Scien is , equi alen o Assis an P o esso ) and in
June 2009, he upg aded o “In es igado Cien í ico
CSIC” (CSIC Resea ch Scien is , equi alen o Associa e P o esso ).
Cu en ly, he heads a esea ch g oup a IMSE-CNM/CSIC on low-powe
medical mic oelec onics and wo ks in he design o silicon mic osys ems
o unde s anding biological neu al sys ems, he de elopmen o neu al
p os heses and b ain-machine in e aces, he implemen a ion o wi eless
body a ea ne wo k anscei e s and he ealiza ion o RFID ansponde s
wi h biomedical sensing capabili ies (2005).
D . Delgado-Res i u o has co-au ho ed he books De ice-Le el Modeling
and Syn hesis o High-Pe o mance Pipeline ADCs (Sp inge , 2011) and
Ul alow Powe T anscei e o Wi eless Body A ea Ne wo ks (Sp inge ,
2013), mo e han 20 chap e s in con ibu ed books, including o iginal
u o ials on chao ic in eg a ed ci cui s, design o da a con e e s, and
chips o bioenginee ing and neu oscience, and 150 a icles in pee - e iew
specialized publica ions.
D . Delgado-Res i u o is a membe o he IEEE CAS Biomedical Ci cui s
and Sys ems Technical Commi ee. He has se ed as he Technical P og am
Chai in di e en in e na ional IEEE con e ences, including ECCTD 2007,
ESSCIRC 2010, and ICECS 2012. He se ed as an Associa e Edi o o he
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II om 2006 o 2007
and he IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I om 2008 o
2011. He also se ed as he Depu y Edi o -in-Chie o he IEEE JOURNAL
ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS om
2011 o 2013 and an Edi o -in-Chie o he IEEE JOURNAL ON EMERGING
AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS om 2014 o 2015.
He is cu en ly he Vice P esiden o Publica ions o he IEEE CAS in 2016.
Rica do Ca mona-Galán (M’98–SM’16) ecei ed
he deg ee in elec onic physics and he Ph.D. deg ee
in mic oelec onics om he Uni e sidad de Se illa,
Spain. He was a Resea ch Assis an wi h he EECS
Depa men , Uni e si y o Cali o nia a Be keley.
He was an Assis an P o esso a he School o
Enginee ing, Uni e sidad de Se illa. Since 2005, he
has been a Tenu ed Scien is wi h he Ins i u e o
Mic oelec onics o Se ille. He held a pos -doc o al
posi ion wi h he Uni e si y o No e Dame, IN,
whe e he was in ol ed in in e aces o CMOS
compa ible nanos uc u es o mul ispec al ligh sensing. He has collabo a ed
wi h s a -up companies, such as Ana ocus, Se ille, and Eu ecus, Be keley. He
has designed se e al ision chips implemen ing di e en ocal plane ope a o s
o ea ly ision p ocessing. He is cu en ly he Co-In en o o se e al pa en s.
He has co-au ho ed o e 120 jou nal and con e ence pape s and a book Low-
Powe Vision Senso s o ision-enabled senso ne wo ks. His cu en esea ch
in e es s lie in he design o low-powe sma image senso s, single-pho on
de ec ion and ToF es ima ion, 3-D in eg a ed ci cui s o au onomous ision
sys ems, and VLSI implemen a ion o concu en senso /p ocesso a ays o
eal ime image p ocessing and ision. He is a membe o he IEEE Ci cui s
and Sys ems and Solid-S a e Ci cui s Socie ies. He has ecei ed he Bes
Pape Awa d o he IEEE-CASS Technical Commi ee on Senso y Sys ems a
ISCAS 2015, oge he wi h D . Vo nicu and P o . Rod íguez-Vázquez. He has
been an Associa e Edi o o he IEEE TCAS-I. He is cu en ly an Associa e
Edi o o he Jou nal on Real-Time Image P ocessing (Sp inge ). He ecei ed
a Ce i ica e o Teaching Excellence om he Uni e sidad de Se illa.
Ángel Rod íguez-Vázquez (F’99) ecei ed he
unde g adua e and Ph.D. deg ees in physics-
elec onics wi h se e al na ional and in e na ional
awa ds, including an IEEE Awa d. A e di e en
esea ch s ays wi h he Uni e si y o Cali o nia-
Be keley and Texas A&M Uni e si y, he became
a Full P o esso o Elec onics wi h he Uni e si y
o Se illa in 1995. He co- ounded he Ins i u e
o Mic oelec onics o Se illa, unde he umb ella
o he Spanish Council Resea ch (CSIC) and he
Uni e si y o Se illa and s a ed a esea ch g oup
on Analog and Mixed-Signal Ci cui s o Senso s and Communica ions. In
2001, he was he main p omo o and co- ounde o he s a -up company
AnaFocus L d., and se ed as he CEO, on lea e om he Uni e si y, un il
2009, when he company eached ma u i y as a wo ldwide p o ide o sma
CMOS image s and ision sys ems-on-chip.
His esea ch is on he design o analog and mixed-signal on -ends o
sensing and communica ion, including sma image s, ision chips, and
low-powe senso y-p ocessing mic osys ems. He has au ho ed 11 books,
36 addi ional book chap e s, and some 150 jou nal a icles in pee - e iew
specialized publica ions. He has p esen ed in i ed plena y lec u es a di e en
in e na ional con e ences and has ecei ed a numbe o awa ds o his esea ch
( he IEEE Guillemin-Caue Bes Pape Awa d, wo Wiley’s IJCTA Bes Pape
Awa ds, wo IEEE ECCTD Bes Pape Awa d, one SPIE-IST Elec onic
Imaging Bes Pape Awa d, one IEEE ISCAS Bes Pape Awa d, one IEEE
ISCAS Bes Demo-Pape Awa d, and one IEEE ICECS Bes Demo-Pape
Awa d). He was an elec ed Fellow o he IEEE o his con ibu ions o
he design o chaos-based communica ion chips and neu o uzzy chips. His
esea ch wo k ecei ed some 6939 ci a ions; he has an h-index o 42 and an
i10-index o 142.
He has always been looking o he balance be ween long- e m esea ch
and inno a i e indus ial de elopmen s. AnaFocus L d. was ounded on he
basis o his pa en s on ision chips and he pa icipa ed in he ounda ion o
he Hunga ian s a -up company AnaLogic L d. He has eigh pa en s iled,
h ee o which ha e been licensed o companies. He has se ed as Edi o ,
Associa e Edi o , and Gues Edi o o di e en IEEE and non-IEEE jou nals.
He is on he commi ee o se e al in e na ional jou nals and con e ences, and
has chai ed se e al in e na ional IEEE and SPIE con e ences. He se ed as
VP Region 8 o he IEEE Ci cui s and Sys ems Socie y om 2009 o 2012
and as Chai o he IEEE CASS Fellow E alua ion Commi ee in 2010 and
om 2012 o 2015.