1310 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 2, FEBRUARY 2012
An Ul alow-Powe Mixed-Signal Back End o
Passi e Senso UHF RFID T ansponde s
José A. Rod íguez-Rod íguez, Fellow, IEEE, Manuel Delgado-Res i u o, Membe , IEEE,
Jens Masuch, S uden Membe , IEEE, Albe o Rod íguez-Pé ez, S uden Membe , IEEE,
Edua d Ala cón, Membe , IEEE, and Ángel Rod íguez-Vázquez, Fellow, IEEE
Abs ac —This pape desc ibes he design o mixed-signal back
end o an ul ahigh- equency senso -enabled adio- equency
iden i ica ion ansponde in ull compliance wi h he Elec onic
P oduc Code Class-1 Gene a ion-2 p o ocol, de ined in he s an-
da d ISO 18000-6C. The chip, implemen ed in a low-cos 0.35-µm
CMOS echnology p ocess, includes a baseband p ocesso , an
analog- o-digi al con e e (ADC) o digi ize he signal acqui ed
om he ex e nal senso , and some auxilia y ci cui y o ol age
egula ion and e e ence gene a ion. The p oposed solu ion uses
wo di e en supply ol ages, one o he p ocesso and he o he
o he mixed-signal ci cui y, and de ines a no el communica ion
p o ocol be ween bo h blocks so ha analog eadou s a e mini-
mally a ec ed by he digi al ac i i y o he ag. The whole sys em
was i s unc ionally alida ed by exhaus i ely es ing wi h ex e -
nal dc powe supplies en p o o ype samples, and hen, he wo
main blocks, p ocesso , and ADC we e indi idually es ed o as-
sess hei pe o mance limi s. Rega ding he baseband p ocesso ,
expe imen s we e pe o med owa d he calcula ion o i s packe
e o a e (PER) unde wo ypical biasing con igu a ions o
passi e ags, using ei he c ude clamps o egula o s. I was ound
ha he egula ed biasing ou pe o ms he clamping solu ion and
ob ains a PER o 3×10−3wi h a supply ol age o 0.75 V. The
cu en consump ion o he p ocesso du ing he ecep ion and
esponse o a Read command a maximum backwa d a e is only
2.2 µA om a 0.9-V supply. Rega ding he ADC, i is a 10-b
successi e app oxima ion egis e con e e which ob ains 9.41 b
o e ec i e esolu ion a 2-kS/s sampling equency wi h a powe
consump ion o 250 nW, including he dissipa ion o a cu en
gene a ion cell and he clock gene a ion ci cui y, om 1-V supply.
Index Te ms—Baseband p ocessing, Elec onic P oduc Code
(EPC) Class-1 Gene a ion-2 (Gen2) p o ocol, ISO 18000-6C,
low-powe design, passi e ansponde , adio- equency (RF)
iden i ica ion (RFID), senso in e ace, successi e app oxima ion
egis e (SAR) analog- o-digi al con e e (ADC) (SAR-ADC).
Manusc ip ecei ed Ma ch 22, 2011; accep ed May 7, 2011. Da e o
publica ion June 23, 2011; da e o cu en e sion Oc obe 18, 2011. This wo k
was suppo ed by he Spanish Minis y o Science and Inno a ion unde G an
TEC2009-08447, by he Jun a de Andalucía unde G an TIC-02818, and by
2007-2013 FEDER P og amme.
J. A. Rod íguez-Rod íguez, M. Delgado-Res i u o, J. Masuch, and
A. Rod íguez-Pé ez we e wi h he Uni e si y o Se ille, 41004 Se ille, Spain.
They a e now wi h he Ins i u e o Mic oelec onics o Se ille, Cen o Nacional
de Mic oelec ónica, Consejo Supe io de In es igaciones Cien í icas, 41092
Se ille, Spain (e-mail: [email p o ec ed]; Manuel.Delgado@imse-
cnm.csic.es; [email p o ec ed]; [email p o ec ed]).
E. Ala cón is wi h he Technical Uni e si y o Ca alunya (UPC
Ba celonaTech), 08034 Ba celona, Spain (e-mail: [email p o ec ed]).
A. Rod íguez-Vázquez is wi h he Uni e si y o Se ille, 41004 Se ille,
Spain, and also wi h he Ins i u e o Mic oelec onics o Se ille, Cen o
Nacional de Mic oelec ónica, Consejo Supe io de In es igaciones Cien í icas,
41092 Se ille, Spain (e-mail: [email p o ec ed]).
Colo e sions o one o mo e o he igu es in his pape a e a ailable online
a h p://ieeexplo e.ieee.o g.
Digi al Objec Iden i ie 10.1109/TIE.2011.2159695
Fig. 1. Block diag am o a senso y ag.
I. INTRODUCTION
THE abili ies o senso -enabled adio- equency (RF) iden-
i ica ion (RFID) ansponde s (senso ags, in sho ) o
moni o , eco d, and e en eac o ambien condi ions a e
expec ed o p omo e a new wo ld o applica ions a beyond
a simple ba code sys em eplacemen [1]–[3]. In hese ags,
he in o ma ion deli e ed o he eade may no only consis
o iden i ica ion da a [4], [5] bu also con ain en i onmen al
eadou s (e.g., empe a u e, p essu e, and op ical o chemical
a iables) ob ained om an accompanying senso .
Nowadays, he e a e no many manu ac u e s who o e ags
wi h senso unc ionali y, and mos o en, solu ions a e ac i e
o semipassi e [6], [7]. Howe e , o ake ull ad an age o
he RFID echnology in e ms o de ice au onomy, small o m
ac o , and low p ice, passi e ags ha e o be a ge ed. Con a y
o hei ac i e coun e pa s, passi e ags ha e no in e nal powe
sou ce a ailable, bu hey a e emo ely biased by he eade by
means o an on-chip RF- o-dc con e sion s age [8]–[13].
Fig. 1 shows he basic block diag am o a passi e senso ag
[8]–[13]. The RF- o-dc con e e is implemen ed by a se o
ec i ie s and limi e s which, oge he wi h ol age egula o s,
p o ide s able supplies o all he blocks o he ag, including
he a ached senso . A powe -on ese (POR) ci cui moni o s
he ol age a he RF- o-dc con e e and de e mines i i s
ou pu has eached a sui ably high ol age le el o eliably
powe he ag. In such a case, he POR ci cui p o ides he
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RODRÍGUEZ-RODRÍGUEZ e al.: ULTRALOW-POWER MIXED-SIGNAL BACK END FOR PASSIVE SENSOR UHF RFID TRANSPONDERS 1311
ini ial logic signal o enable he baseband p ocesso . O he wise,
i s ops he en i e digi al sys em o p e en unp edic able be-
ha io o ansmission o e oneous da a. In he signal pa h, he
demodula o ex ac s he bina y ins uc ions o be handled by
he baseband p ocesso om he incoming RF signal. A sel -
oscilla ing clock gene a o , enabled by he POR ci cui , de ines
he mas e equency o he ag. Backwa d communica ion
o he eade is accomplished by modula ing he ampli ude
and/o he phase o he RF ca ie by means o a swi chable
an enna ma ching ne wo k d i en by he baseband ci cui y.
Speci ic o senso ags, a signal condi ioning ci cui , including
an analog- o-digi al con e e (ADC), is used o acqui e he
physical a iable measu ed by he senso . The condi ioning ci -
cui and he senso i sel a e supplied by a dedica ed egula ed
ol age o a oid pe u ba ions om he digi al ac i i y o he
p ocesso .
Because o he sca ce supplying condi ions, powe consump-
ion minimiza ion is a p io i y o passi e ags in gene al and
senso ones in pa icula as o he addi ional esou ces equi ed
by he senso ci cui y. Ano he impo an challenge o passi e
senso ags is o de ine a eliable p o ocol be ween he signal
condi ioning ci cui y and he baseband p ocesso o he ag, so
ha senso eadou s can be obus ly ans e ed and p ocessed.
This pape add esses bo h challenges and p esen s he design
o he baseband p ocesso , da a-con e sion s age, and o he
auxilia y blocks (shaded elemen s in Fig. 1) o a passi e ul-
ahigh equency (UHF) senso ag o hal -duplex commu-
nica ions in he 860–960-MHz ange. The design has been
concei ed as a mul ipu pose pla o m no ied o a pa icula
senso de ice. Hence, any e en ual signal ansduc ion equi ed
by he senso o p o ide i s ou pu in ol age o m is assumed
o be ealized o -chip. Despi e his limi a ion, which mus
be anyhow balanced wi h he mul ipu pose ea u e o he so-
lu ion, he p oposed p ocedu es and echniques can be like-
wise applied o any a bi a y senso -enabled ag wi h on-chip
senso s.
The p oposed design, implemen ed in a low-cos 0.35-µm
CMOS echnology, a ge s he Elec onic P oduc Code (EPC)
Class-1 Gene a ion-2 (Gen2) p o ocol [14], included in he
s anda d ISO 18000-6C [15], which is b ie ly e iewed in
Sec ion II. The a chi ec u e o he baseband p ocesso is p e-
sen ed in Sec ion III, and Sec ion IV desc ibes i s iming con ol
uni which suppo s many o he low-powe design s a egies
implemen ed in he chip. Sec ion V p esen s he p o ocol used
o he communica ion be ween he p ocesso and he da a-
con e sion s age. I also b ie ly desc ibes he design o he
con e e , a ail- o- ail 2-kS/s 10-b successi e app oxima ion
egis e (SAR) ADC (SAR-ADC). Nex , Sec ion VI shows he
expe imen al esul s which con i m ha he p ocesso is ully
unc ional, mee s he packe e o a e (PER) speci ica ions
o he a ailable egula ions, and is able o ole a e mas e
clock equency de ia ions as high as 15% om he nominal.
This is demons a ed o wo di e en biasing ci cui s, ei he
using a dedica ed ol age egula o o a p og ammable supply
capaci o , o compa ison pu poses. The baseband p ocesso
only consumes 2.2 µA a 0.9-V supply using a supply ol age
egula o , and he SAR-ADC ob ains 9.4 b o e ec i e eso-
lu ion [e ec i e numbe o bi s (ENOB)] o 1-V supply wi h
TABLE I
EPC Gen2 COMMANDS
Fig. 2. (a) P eamble used in eade - o- ag signaling du ing a Que y command.
(b) Da a encoding in PIE o ma .
only 250 nW o powe consump ion. Finally, Sec ion VII gi es
some concluding ema ks.
II. EPC Gen2 REVIEW
The EPC Class-1 Gen2 p o ocol [14] is a highly lexible
RFID p o ocol which allows o he ansmission o simple
commands be ween eade and ags. These ins uc ions a e
lis ed in Table I oge he wi h hei iden i ica ion codes. They
a e g ouped in o h ee ca ego ies (Selec ,In en o y, and Access)
ela ed o he di e en phases along an RFID communica ion.
All hese commands ha e been ully implemen ed in he p o-
posed baseband p ocesso .
Reade - o- ag communica ions a e always p eceded by a
p eamble. Fig. 2(a) shows an example, co esponding o a
Que y ins uc ion. The p eamble comp ises a ixed-leng h de-
limi e ,ada a-0 symbol, a eade - o- ag calib a ion symbol
(RTcal), and a ag- o- eade calib a ion symbol (TRcal). These
wo la e symbols a e used o de ine he o wa d ( eade - o-
ag) and backwa d ( ag- o- eade ) da a a es, espec i ely. The
du a ion o RTcal is equal o he leng h o a da a-0 symbol plus
he leng h o a da a-1 symbol, bo h shown in Fig. 2(b). These
symbols de ine he pulse-in e al encoding (PIE) o ma used
o eade - o- ag signaling.
The da a a es o he backwa d link (which may amoun
om 5 o 640 kb/s) a e ob ained by di iding he mas e clock
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1312 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 2, FEBRUARY 2012
Fig. 3. A chi ec u e o he p oposed baseband p ocesso .
equency by in ege alues. The numbe o clock cycles pe bi
in he backwa d link NBLF is he e o e compu ed as
NBLF = oundin (TRcal · m)
DR (1)
whe e he di ide a io DR speci ied in he Que y command can
be 8 o 64/3, mis he mas e clock equency, and in (·)is an
ope a o whose ou pu may ake on wo possible in ege alues
which a e ob ained by ei he ounding up o down i s a gumen .
This depends on he ap io iunknown phase ela ion be ween
he local oscilla o and he demodula ed RF signal. The Gen2
p o ocol de ines ole ance ma gins o he di e en backwa d
equencies which can be syn hesized om (1). Taking in o
accoun hese ole ances and he iming esolu ion equi emen s
o he o wa d link, as well as he need o educing he dynamic
powe consump ion o he p ocesso , i can be heo e ically
ound ha he minimum mas e clock equency imposed by
Gen2 equi emen s is 1.92 MHz [16], [17].
III. BASEBAND PROCESSOR ARCHITECTURE
The baseband p ocesso o a senso y RFID ag decodes
he demodula ed signal, checks consis ency, pe o ms he op-
e a ions eques ed by he eade , manages he access o he
memo y blocks (and, e en ually, o he da a acqui ed om he
senso ), and gene a es he in o ma ion o be backsca e ed o
he in e oga o .
Fig. 3 shows he block diag am o he p oposed p ocesso .
I s ope a ion is enabled by he baseband POR signal h ough
a lip- lop synch onized o he sys em mas e clock clk_mas e .
When enabled, he p ocesso p o ides a single ou pu s eaming
esponse o he demodula ed signal coming om he analog
on end o he RFID da a_dem and, e en ually, om he
ol age acqui ed om he senso y plane sens_in.
Aside om he Timing Uni , o be discussed in Sec ion IV,
he p ocesso consis s in h ee majo blocks which implemen
decoding, encoding, and p ocessing ope a ions, espec i ely.
In he decoding sec ion, a alling-edge igge ed lip- lop
Sync_FF is used o synch onize da a_dem o he mas e clock
signal. Then, a PIE Decode block is used o con e he
esul ing digi ized o wa d link om PIE o bina y o ma . This
is simply accomplished by a ime- o-digi al con e sion. The
numbe o clock cycles comp ised du ing he symbol RTCal
is compu ed and di ided by wo o de ine a pi o . I a symbol
has less numbe o cycles han he pi o , hen i is a da a-0
symbol; o he wise, i is a da a-1 symbol. The ou pu o he
PIE Decode block bi _ou is sequen ially s o ed in a 16-b Shi
Regis e block o be e alua ed by he Command Decode block.
The pu pose o he Command Decode is o iden i y which
ins uc ion has been sen by he eade . This is a simple ask
because commands in he Gen2 p o ocol include a code which
unequi ocally add esses he ins uc ion ecei ed by he ag
( hi d column o Table I). Command iden i ica ion is accom-
plished when he las bi o his code is ecei ed. Then, he
Command Decode codi ies he ins uc ion in a 4-b ec o
cmd_ID ( ou h column o Table I).
Aside om illing Shi Regis e , he ou pu o he PIE
Decode block is also ans e ed o a cyclic edundancy check
(CRC) uni o ansmission e o de ec ion. The esul s o he
CRC compu a ions a e s o ed in bu e s and used by a CRC
Check block o assess hei alidi y.
A e command iden i ica ion, he Command Decode passes
cmd_ID o he FSM Rx block inside he p ocessing sec ion. This
block is o med by a se o ini e-s a e machines (FSMs), one
pe Gen2 command. Only ha FSM add essed by he Command
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RODRÍGUEZ-RODRÍGUEZ e al.: ULTRALOW-POWER MIXED-SIGNAL BACK END FOR PASSIVE SENSOR UHF RFID TRANSPONDERS 1313
Fig. 4. S uc u e o he Timing Uni block.
Decode is ac i e; he o he s a e disabled. The ac i e FSM
sequen ially s o es he command pa ame e s in he egis e s o
he S ack block. Only ha egis e which is being add essed by
he FSM Rx block is ac i e; he o he s emain o .
The FSM Co e block decides he ag’s s a e, pe o ms he
equi ed s a e ansi ions, eads he pa ame e s s o ed in he
S ack by he FSM Rx, and igge s he FSM Tx block acco ding
o he command ha has been ecei ed. When ope a ions a
FSM Co e a e concluded, a nonze o 5-b ec o o de _ou is
ansmi ed o he FSM Tx block.
A he encoding sec ion, he FSM Tx block pe o ms he
ac ions eques ed by he eade , such as o ead he non ola ile
memo y o he ag ( ep esen ed in Fig. 3 by he PROM block),
ga he pa ame e s o in o ma ion o send (including da a om
he senso in e ace), o con ol he ansmi e o he backwa d
link. Depending on he handled command, he FSM Tx block
also uses a 16-b andom numbe gene a o o au hen ica ion,
da a enc yp ion, and key adminis a ion.
The FSM Tx is o med by a se o FSMs. The e is one FSM
o each possible ac ion, and as be o e, only one FSM is enabled
a a ime. The FSM Tx block calcula es he numbe o mas e
clock cycles equi ed o he syn hesis o he backsca e ing link
equency (BLF) using he DR and he TRcal in o ma ion.
This coun ing numbe is la e ans e ed o he Tx block which
encodes he da a a he bi a e eques ed by he eade . When
he eques ed ac ion has been inished o he ansmission is
comple ed, FSM Tx and Tx (i equi ed) a e disabled, and FSM
Co e is ac i a ed again o check i he p ocesso mus change
he s a e o emain in he same con igu a ion.
The PROM is a 128-b one- ime-p og ammable memo y a ay
based on Zene Zap diodes ac ing as an i uses [31]. The mem-
o y and i s d i ing ci cui y use s anda d cells a ailable in he
echnology. The EPC Numbe o he iden i ica ion o he ag is
s o ed in he i s 96 b o he memo y, and he emaining 32 b is
ese ed o use da a, o ins ance, senso calib a ion da a.
IV. TIMING UNIT
The Timing Uni gene a es he con ol signals equi ed by
he decoding, encoding, and p ocessing ope a ions desc ibed
in Sec ion III. Two basic powe sa ing design s a egies ha e
been conside ed in i s implemen a ion, namely, he clock-ga ing
(CG) and clock-managemen (CM) app oaches [13].
The o me is a well-known app oach which builds on he
idea o disabling blocks when hey a e dispensable, hus e-
ducing he o e all powe consump ion o he sys em [18], [19].
Fo ins ance, i he p ocesso has no comple ely in e p e ed a
ecei ed command, he e is no need o ac i a e hose blocks
in ol ed in he backwa d link communica ion. CG can be sim-
ply ealized by combining he inpu clock wi h an enable lag
in acco dance o he command ha he p ocesso is cu en ly
handling. I he enable lag is only ac i e du ing a single clock
pe iod, he ga ed signal is a simple pulse, he ein deno ed as a
igge .
In o he espec s, no all he blocks o he p ocesso need
o un a ull speed. Ra he , some o hem can be clocked a
a ac ion o he mas e equency o sa e powe . Mo eo e ,
he e a e blocks ha can be d i en a di e en equencies,
depending on he pa icula p ocesso s a e. This is he design
p inciple o he CM app oach, i.e., o de ine dedica ed clocks
pe block and s a e in o de o educe he o e all dynamic powe
consump ion o he p ocesso . The lowe limi o he dedica ed
clock equencies is de e mined by he ime in e al be ween
wo ising edges o he demodula ed inpu signal.
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1314 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 2, FEBRUARY 2012
TABLE II
DEDICATED CLOCKS OBTAINED BY APPLYING CM STRATEGIES
Fig. 5. Timing diag am o clk_co e.
TABLE III
TRIGGER SIGNALS
The schema ic o he Timing Uni block is shown in Fig. 4. I
consis s o h ee main sec ions: FSM Con ol, dedica ed clocks
syn hesis, and igge signals gene a ion.
The FSM Con ol handles he s a e o he baseband p ocesso
and decides he clocks and igge s which a e ac i e along he
ci cui ope a ion. I is d i en by a se o inpu signals and ec o s
and clocked by clk_mas e .
Dedica ed clocks a e ob ained by means o a 6-b coun e
d i en by he clk_mas e . Acco dingly, clocks wi h equen-
cies m= m/2n,n=0,...,6, can be syn hesized. Table II
summa izes he di e en dedica ed clocks syn hesized by he
Timing Uni , along wi h he baseband blocks ha hey d i e,
he signals used o enable and disable he clock, hei ou pu
equencies, and he associa ed commands. As an example,
Fig. 5 shows a iming diag am o he syn hesis o clk_co e
which uns a hal he equency o he mas e clock. Following
CG s a egies, clk_co e is only ac i e in esponse o a delayed
e sion o he enabling signal en_co e.
Table III shows he di e en igge pulses gene a ed by
he Timing Uni , along wi h he baseband blocks ha hey
d i e and he signals used o enable and disable hem. The
i s h ee igge s in Table III a e ela ed o changes in he
inpu da a signal da a_in, whe eas he o he wo igge s a e
ela ed o CRC ope a ions. As an example, Fig. 6 shows he
Fig. 6. Timing diag am o en_pulse_shi .
iming diag am o he signals in ol ed in he gene a ion o he
en_pulse_shi igge signal, which is used o enable he Shi
Regis e block.
I is wo h obse ing ha igge s en_pulse_cmd and
en_pulse_ x a e delayed e sions o en_pulse_shi , by one o
wo mas e clock cycles, espec i ely. This a o s he co ec
synch oniza ion o he Shi Regis e ,Command Decode , and
FSM RX blocks and also allows o a mo e uni o m dis ibu ion
o cu en consump ion o e ime.
V. S ENSORY INTERFACE AND DATA TRANSFER
Speci ic o senso y- ype RFIDs, he a chi ec u e in Fig. 3 also
includes an ADC which con e s he quasi-s a ic ol age signal
gene a ed by he ex e nal senso .
Da a ans e om he con e e o he eade implies wo
manda o y Gen2 commands: W i e and Read. The p ocedu e is
shown in Fig. 7. The in e ace ci cui y is enabled when he
W i e command add esses he Use Bank o he ag.1When
his occu s, he p ocesso u ns down a powe down lag, and
he ADC s a s con e ing he analog inpu signal acqui ed
by he ol age bu e a e a 50-µs delay o gua an ee a qui e
supply— he digi al ac i i y o he p ocesso conside ably de-
c eases a e such a delay. The con e sion p ocess is epea ed
i e imes. The i s one D0is disca ded because o possible
sampling e o s du ing ADC powe on, and he emaining ou
1Da a s o age in he Gen2 s anda d is di ided in o ou di e en banks,
in e nally di ided in 16-b leng h wo ds, deno ed as Rese ed, EPC, Tag
Iden i ica ion (TID), and Use banks [14]. The op ional Rese ed bank con ains
he kill and/o access passwo ds o he ag in case such a ea u e is implemen ed.
The EPC bank s o es he a iable-leng h EPC oge he wi h a 16-b p o ocol
con ol wo d. I also con ains a 16-b CRC code which is calcula ed upon each
powe -up. The TID bank s o es he manu ac u e ’s code which allows o an
in e oga o o iden i y he cus om commands and/o op ional ea u es ha he
ansponde suppo s. Finally, he Use bank is op ional and can be exploi ed in
senso y ags o ead/w i e senso measu emen s.
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RODRÍGUEZ-RODRÍGUEZ e al.: ULTRALOW-POWER MIXED-SIGNAL BACK END FOR PASSIVE SENSOR UHF RFID TRANSPONDERS 1315
Fig. 7. Communica ion diag am o he p ocesso /ADC in e ace.
Fig. 8. Simpli ied schema ic o he 10-b cha ge- edis ibu ion SAR-ADC.
con e sions D1,...,D4a e a e aged in digi al domain and
s o ed in he Use Bank posi ion speci ied in he W i e com-
mand. A e wa d, he ag in o ms he eade ha he con e sion
has been success ully comple ed (o he wise, an e o command
is e u ned). Finally, he in e oga o sends a Read command
add essing he memo y posi ion whe e he ADC con e sion has
been s o ed, and he in o ma ion is e ie ed.
The in e ace ci cui y uses he ga ed clock clk_adc ( unning
a a equency o m/64) du ing he con e sions D0,...,D4.
This equency is in e nally di ided by wo by means o le el-
shi ed lip- lops which also adap he logic le els o he eg-
ula ed e e ence. Al oge he , he ADC ope a es a a equency
128 imes slowe han he mas e clock. As he ADC equi es
12 clock cycles o comple e a con e sion, i s nominal h ough-
pu a e is 1.25 kS/s.
Fig. 8 shows he schema ic o he ADC. I is a cha ge-
edis ibu ion SAR con e e which consis s o a capaci i e
digi al- o-analog con e e (DAC), a compa a o , and some
con ol logic (i sel called he SAR). Ci cui ope a ion is as
ollows. The inpu signal is i s sampled and s o ed in he
capaci i e DAC and hen added o he analog equi alen o he
i s SAR code [ he mos signi ican bi (MSB) is se o “1”
while he emaining bi s a e “0”] o gi e
VDAC =Vin +VDDA/2(2)
whe e VDDA is he egula ed powe supply o he whole in-
e ace ci cui y. The alue (2) is compa ed o VDDA, and
Fig. 9. Schema ics o he (a) au oze oed compa a o , (b) p eampli ie , and
(c) dynamic la ch.
depending on he ou pu o he compa a o , he MSB o he
ADC ou pu is de ini i ely se o “1” i Vin >V
DDA/2o “0”
i o he wise. Co espondingly, he MSB capaci o is ied o
VSS o VDDA ( he SAR and ADC ou pu s a e complemen a y).
A e wa d, he nex bi o he SAR egis e is ac i a ed o an
addi ional compa ison, and he p ocedu e is epea ed un il he
N-bi con e sion is comple ed. A he end o he con e sion
phase, he ou pu o he DAC is gi en by
VDAC =Vin +
N

n=1
Vcomp(n)·VDDA
2n(3)
whe e Vcomp(n)=[0,1] is he n h compa ison esul .
The capaci i e DAC uses wo 5-b bina y-weigh ed suba ays
connec ed by a uni a y capaci o o ob ain he equi ed 10-b
esolu ion [20]. Swi ches in he a ay a e pMOS o nMOS, de-
pending on whe he he bo om pla e o capaci o s is connec ed
o he nega i e o posi i e ails (VSS o VDDA, espec i ely).
Sampling swi ches S1 and S2 a e boo s apped o allow o ail-
o- ail ope a ion o he con e e [21].
The compa a o uses an inpu o se -compensa ed a chi ec-
u e so ha he s a ic esolu ion o he ci cui emains below he
con e e quan iza ion s ep. The schema ic o he compa a o is
shown in Fig. 9(a) and consis s o an au oze oed p eampli ie
[Fig. 9(b)] ollowed by a dynamic la ch [Fig. 9(c)]. As VDAC
swings om VDDA/2 o 3VDDA/2, a simple pMOS swi ch S2
is used o eliably sample his ol age. On he con a y, S1 is a
boo s apped swi ch, and S3 and S4 a e CMOS swi ches.
Finally, he SAR logic block has been implemen ed using he
cus om a chi ec u e p esen ed in [22], which p o ides nea ly
40% less powe han con en ional lib a y cell solu ions.
Bo h he ol age bu e and he ADC a e supplied by he bias
cu en gene a o in Fig. 10. I is based on he ci cui p esen ed
in [23] and p o ides a nominal cu en e e ence I e o 30 nA.
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1316 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 2, FEBRUARY 2012
Fig. 10. Bias cu en gene a o o he signal condi ioning ci cui .
Fig. 11. Schema ic o he egula o employed o supply he signal condi ion-
ing ci cui and he ex e nal senso .
The cu en gene a o includes a s a -up ci cui which a oids
he e e ence ci cui o ge apped in a pa asi ic ze o cu en
s a e [24]. Ci cui ope a ion is enabled when signal pw _down
is in i s high s a e. O he wise, he gene a o is swi ched o
wi h a negligible powe consump ion and he d i en blocks u n
unbiased.
As shown in Fig. 1, he comple e mixed-signal senso in e -
ace is powe ed by a dedica ed low-d opou egula o (LDO).
I s schema ic is shown in Fig. 11 and p o ides a s able ou pu
supply ol age VDDA o 1 V. The un egula ed inpu ol age
V ec can ange om 1.1 o 3 V. The ou pu ol age VDDA
is s abilized by means o a le hal -plane ze o compensa ion
echnique implemen ed by RZand CZ[25]. The load o he
egula o is de ined by he on-chip signal condi ioning ci cui y
and he ex e nal senso . The maximum ou pu load cu en and
maximum load capaci ance ole a ed by he egula o a e 50 µA
and 30 pF, espec i ely. The quiescen cu en o he egula o
is 700 nA, 50 nA o which is consumed by he e o ampli ie ,
and i ob ains a line egula ion o 17 µV/V, a load egula ion o
10 mV/mA, and a peak d opou ol age o 160 mV.
Fig. 12. (a) Die mic og aph o he passi e UHF RFID baseband p ocesso and
he da a-con e sion s age. (b) E alua ion se up.
VI. EXPERIMENTAL RESULTS
The a chi ec u e o Fig. 3 has been implemen ed in a
0.35-µm CMOS echnology. Fig. 12(a) shows a mic opho o-
g aph o he chip, in which he signal acquisi ion ci cui y
and he digi al baseband p ocesso can be easily iden i ied.
The baseband p ocesso occupies 1.0 mm2. Fig. 12(b) shows
a pho og aph o he se up employed o es ing.
Tes has been ealized by using an Agilen 16902B logic
analyze and a Tek onix AFG3102 o mas e clock equency
gene a ion. Measu emen s ha e add essed he unc ional
alida ion o he p ocesso , i s PER and powe consump ion
pe o mances unde di e en supply condi ions, and he cha -
ac e iza ion o he mixed-signal senso in e ace. They a e
sepa a ely discussed nex .
A. Func ional Ve i ica ion
Ten samples o he p o o ype ha e been exhaus i ely es ed o
alida e hei unc ionali y. Ou measu emen s con i med ha
he sys em wo ks p ope ly in all he samples and o all he
ins uc ions de ined by he EPC s anda d. In he expe imen s,
we used a supply ol age VDDD =0.9V o he baseband
p ocesso and VDDA =1.0V o he senso y in e ace ci cui y
( he V e and V ec in Fig. 11 we e 650 mV and 1.5 V, espec-
i ely). Vol ages VDDD,V e , and V ec we e ex e nally p o ided
by dc powe supplies.
As an illus a ion, Fig. 13 shows he sys em esponse o a
sequence o commands which conclude wi h a da a acquisi ion
om he senso . The inse o Fig. 13 shows he de ails o
some o he signals in ol ed in he Read ope a ion. Signals
clk_pie and en_pulse_shi a e only ac i e when he p ocesso
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RODRÍGUEZ-RODRÍGUEZ e al.: ULTRALOW-POWER MIXED-SIGNAL BACK END FOR PASSIVE SENSOR UHF RFID TRANSPONDERS 1317
Fig. 13. Example o ag- eade communica ion, including a senso in o ma-
ion low using FM0 encoding o he backwa d link.
is decoding he inpu signal da a_in. A he end o he Read
command, clk_co e is enabled o p ocess he ecei ed in o -
ma ion. Once he p ocessing inishes, clk_co e is disabled, and
clk_ x u ns on o ansmi ing he eques ed da a da a_ou .I is
a digi al sequence which con ains he a e aged da a con e sion
gene a ed du ing he p e ious W i e command, oge he wi h
o he pa ame e s imposed by he communica ion p o ocol. I
is wo h obse ing ha only he en less-signi ican bi s o he
Use Bank a e occupied by he da a-con e sion ou come, in
acco dance o he esolu ion o he ADC. Once he in o ma ion
is ansmi ed, clk_ x s ops.
Ano he es conce ned he obus ness o he p ocesso
agains de ia ions o he mas e equency. Fig. 14 shows he
backsca e equency e o o he sys em measu ed a 1.92
Fig. 14. BLF e o de ia ion. (a) DR =8.(b)DR =64/3.
and 1.632 MHz, i.e., using a mas e clock equency 15%
slowe han he nominal. Di ide a ios o 8 and 64/3 ha e been
conside ed in Fig. 14(a) and (b), espec i ely. In bo h cases,
he bounda y lines a e pe he Gen2 speci ica ion equi emen s.
The ob ained saw oo h cha ac e is ics a e a di ec consequence
o he ounding e o s inhe en o (1). Fig. 14 shows ha , e en
wi h a 15% equency de ia ion, he sys em mee s he Gen2
equi emen s wi h ma gin.
B. PER
In o de o assess he pe o mance limi s o he p esen ed
baseband p ocesso alone2unde ealis ic ope a ion condi ions,
wo di e en expe imen al se ups ha e been conside ed. They
a e aimed o ep oduce, wi hou eso ing o RF signaling,
he wo ypes o baseband biasing con igu a ions ha can be
ound in passi e ags, hose using c ude clamps [12], [26] o
using egula o s [8]–[11], [27], [28]. I is wo h insis ing ha
no ex e nal clean supply has been used in he measu emen s
2The pe o mance o he mixed-signal senso in e ace is p esen ed in
Sec ion VI-D.
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1318 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 2, FEBRUARY 2012
Fig. 15. Tes se ups o e alua e he PER pe o mance o he baseband p oces-
so . (a) Non egula ed and (b) egula ed supply ol ages.
which o he wise would un ealis ically amelio a e he ue pe -
o mance o he p ocesso .
In one scena io [deno ed as he non egula ed case and shown
in Fig. 15(a)], he sys em is di ec ly powe ed by he ec i ied
a e age o he incoming bina y da a da a_pg. This bi s eam,
gene a ed by an Agilen 16702A pa e n gene a o , can be
in e p e ed as an ampli ude-adjus able e sion o he ampli ude
shi keying (ASK) modula ing signal used by he eade .
Rec i ica ion is simply implemen ed by a p og ammable on-
chip supply capaci o Con−chip and an ex e nal Scho ky diode
(Agilen HSM S-2850), oge he wi h some passi e il e ing
ci cui y. The di e en capaci ance alues o Con−chip, nom-
inally anging om 0 o 800 pF, a e ex e nally p og ammed
h ough dedica ed con ol pins. The il e , which is a simple
RC sec ion, has been added o model he o wa d ime cons an
o he ec i ie and, hence, o be e emula e he ol age ipples
which can be obse ed a he ou pu o he ec i ie /limi e block
in monoli hic RFID ags [28], [29]. No e ha , due o he PIE
encoding o ma used in he o wa d link [see Fig. 2(b)], he
ampli ude o he ecei ed ASK signal emains a maximum
alue (no ma e i da a-0 o da a-1 has been ansmi ed) excep
du ing he RF no ches o du a ion PW, in which he ampli ude
d as ically d ops wi h a nominal modula ion index o 90%. As
he du a ion o he in e al PW, which may amoun om 2 o
13.125 µs [14], is much la ge han he pe iod o he ca ie
signal, he ipple a he ou pu o he ec i ie /limi e in Fig. 1
is essen ially domina ed by he RF no ches [28], he e ec ha
can be easily ep oduced wi h he se up o Fig. 15(a) wi h no
need o RF signals. As an illus a ion, Fig. 16 shows a snapsho
o he gene a ed supply signal VDDD, o a 1-V ampli ude
da a_pg signal, assuming ha PW =13.125 µs and a load
capaci ance Con−chip = 100 pF. As he o wa d ol age o he
Scho ky diode is 150 mV, he peak alue o VDDD is 900 mV.
In his scena io, he ol age d op (312.5 mV in he example)
due o he ASK modula ion depends in e sely on he supply
capaci o [29]. This is illus a ed in Fig. 17, which shows he
expe imen ally obse ed peak ipple ol age in e ms o he on-
chip supply capaci ance o a VDDD ampli ude o 0.9 V. No e
ha , o low supply capaci ances, he ol age d op can be as
high as 0.44 V.
In he second scena io [deno ed as he egula ed case and
shown in Fig. 15(b)], he sys em is powe ed by an LDO
Fig. 16. Measu ed signals in he expe imen al se up o Fig. 15(a). Inpu signal
da a_pg is a 40-kHz pulse ain wi h 1-V ampli ude and 47.5% du y cycle. The
peak ampli ude o he ec i ied signal VDDD is 0.9 V, and he ol age d op is
312.5 mV.
Fig. 17. Peak ol age d op in he supply line o he p ocesso , wi h a VDDD
ampli ude o 0.9 V. The ci cles co espond o he measu ed esul s, and he
con inuous ace is a i ing cu e.
p eceded by a ec i ica ion ci cui , simila o ha shown in
Fig. 15(a), bu using an ex e nal capaci o Coff−chip = 300 pF.
The baseband egula o ollows a s uc u e simila o ha in
Fig. 11, bu ins ead o le hal -plane ze o compensa ion (RZ
is eplaced by a sho ), i uses Mille compensa ion (a 1-pF
capaci o is connec ed be ween he ga e and d ain o he pass
ansis o M6) [25]. Capaci o CZamoun s 200 pF, and i is
implemen ed by p ope ly p og amming he on-chip capaci o
Con−chip. Simila o he LDO o he signal acquisi ion sec ion,
he un egula ed inpu ol age V ec can ange om 1.1 o 3 V
(V ec =1.5V was used in he expe imen s). The maximum
ou pu load cu en is 100 µA, and he quiescen cu en is
only 125 nA, 25 nA o which is used by he e o ampli ie .
The egula o ob ains a line egula ion wi hin 25 µV, a load
egula ion o 8 µV/µA, and a peak d opou ol age o 150 mV.
In bo h powe ing s a egies, he p ocesso da a inpu da a_in
is con amina ed by he supply a ia ions (simila o ha occu s
in ully in eg a ed ansponde s) by means o ol age bu e s
biased by he syn hesized VDDD.
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