Resonation-based Cascade ΣΔ Modulators for High-Linearity Broadband A/D Conversion

Resonation-based Cascade ΣΔ Modulators for High-Linearity Broadband A/D Conversion A. Morgado, R. del Río and J.M. de la Rosa Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Ed. CNM-CICA, Av. Reina Mercedes s/n, 41012 Sevilla, SPAIN. Phone: +34955056666, Fax: +34955056686, E-mail: {alonso|rocio|jrosa}@imse.cnm.es Abstract - This paper presents two new architectures of cascade ΣΔ modulators that, based on the use of resonation, allow to increase the effective resolution compared to previously reported topologies whereas keeping relaxed output swing and high robustness to non-linearities of the amplifiers. In addition, the use of loop filters based on Forward-Euler integrators, instead of Backward-Euler integrators as proposed in earlier approaches, simplifies the switched-capacitor implementation and makes the proposed architectures very suited for the implementation of highly-linear broadband A/D conversion†. I. INTRODUCTION The increasing demand for high data-rate A/D converters for the next generation of telecom systems implemented in nanometer CMOS technologies is motivating the exploration of new topologies of wideband ΣΔ Modulators (ΣΔMs) [1]-[7]. Among others, the use of resonation [5] and/or unity Signal Transfer Function (STF) [2][3] are demonstrating to be good candidates for low-voltage implementation. On the one hand, loop-filter resonators allow to increase the effective resolution as compared with integrator-based noise-shaping filtering. On the other hand, by making STF unity, the integrators ideally process quantization error only, thus relaxing their requirements of amplifier gain non-linearity and output swing. The above mentioned strategies can be combined with cascade topologies in order to increase the order of the modulator whereas keeping stability and low oversampling ratio [1][7]. However, the implementation of in-loop resonators requires using Backward-Euler (BE) or non-delayed integrators which makes their Switched-Capacitor (SC) implementation more difficult. This paper presents two novel topologies of cascade ΣΔMs intended for high-speed and low-voltage applications. Both modulators combine resonation techniques and unity STF. One of them is based on local resonation whereas the other one employs global resonation. In both cases, Forward-Euler (FE) instead of BE integrators are used, thus circumventing the implementation problems presented in the former architectures based on cascaded resonators. The paper is organized as follows. Section II provides a background on previously reported low-voltage broadband cascade ΣΔM architectures, based on the use of unity STF and resonation. Section III describes the ΣΔ topologies proposed in this paper. Finally, behavioral simulations are shown in Section IV that demonstrate the benefits of the proposed architectures in terms of effective resolution and robustness to opamp non-linearities and relaxed output swing. II. BACKGROUND ON BROADBAND CASCADE ΣΔMs As discussed previously, most promising ΣΔM architectures for low-voltage broadband applications combine cascade topologies with unity STF and resonation. These architectures are briefly described in this section. A. Unity STF cascade ΣΔ M topologies Fig.1 shows a second-order single-loop that makes use of Analog FeedForward (AFF) paths to implement a unity STF [2][3]. Using a linear model for the internal quantizer, the Z-transform of the modulator output, , is given by: (1) where and are the Z-transform of the input and quantization error, respectively; and and are the Signaland NoiseTransfer Functions, respectively given by: (2) One of the most remarkable advantages of the modulator in Fig.1 is that, at least ideally, there is no †. This work has been supported by the Spanish Ministry of Science and Education (contract TEC2004-01752/MIC) and the Spanish Ministry of Industry, Tourism and Commerce (FIT-330100-2006-134 SPIRIT). Fig. 1: Second-order single-loop ΣΔM with unity STF [2]. - +Σ Σ +++ 2 Hz() z1– 1z1– – ---------------- = xi x1x2 y y Hz() Hz() B bits B-bit Yz() Yz() STF z()Xz() NTF z()Ez()+= Xz() Ez() STF z() NTF z() STF z() 1= NTF z() 1z1– –() 2 = XXII Conference on Design of Circuits and Integrated Systems ISBN-13 978-84690-8629-2 23 input signal trace processed by the integrators. This is easy to demonstrate by obtaining the Z-transform of the integrators inputs, and , given by (3) Therefore, the combination of feedforward paths −giving rise to unity STF−, together with multibit internal quantizers, make the architecture in Fig.1 very suited for low output swing requirements, reduced sensitivity to amplifier non-linearities and high overload levels. The principles underlying in Fig.1 can be extended to cascade ΣΔMs [3][4]. This is illustrated in the modulator shown in Fig.2, proposed in [4]. This modulator, which from now on will be referred to as AFF-AFF, has the additional advantage of using only one interstage path, with the subsequent circuit simplification and increment of robustness with respect to circuit non-idealities. B. Resonation-based cascade ΣΔ M topologies An efficient way to increase the resolution without penalizing the number of integrators consists of including resonators inside the modulator loop filter. Thus, the so-called local resonation technique has been used in ΣΔMs considering either single-loop [5] or cascades [1]. In both cases, this technique allows to shift the zeroes of NTF from DC, thus allowing to distribute them in an optimum way such that the in-band noise can be minimized [6]. In the case of cascade architectures, only the last stage normally uses resonation in order to reduce the digital cancellation logic. As an illustration, Fig.3 shows a cascade with local resonation in the last stage. This topology, originally presented in [1], takes advantage of both the unity STF of the first stage and the feedforward path at the last one, thus obtaining relaxed output swing requirements. Recently, a new kind of resonation strategy, named global resonation, has been applied to cascade ΣΔMs [7]. This new approach, illustrated in Fig.4 for a fourth-order cascade architecture, is obtained by feeding back the error component from the last stage to the previous one. Note that, this topology achieves resonation thanks to a global path that feeds back a scaling version of the last stage quantization error at the input of the first stage quantizer. In both cases, either using local or global resonation, the is: (4) where stands for the inter-stage gain. Note that the zeroes of are a function of , which can be X1z() X2z() X1z() 1z1– –() 2 –Ez()⋅= X2z() z1– 1z1– –() 2Ez()⋅⋅= Fig. 2: Fourth-order Cascade AFF-AFF ΣΔM architecture with unity STF [4]. - + Σ Σ +++ - + Σ Σ ++++ Σ + 2 z2– Hz() 1z1– –() 2 1d⁄ Hz() Hz() Hz() 2 d y xB1 B2 Fig. 3: Fourth-order Cascade ΣΔM architecture with local resonation and unity STF [1]. - +Σ Σ ++ + - +Σ Σ ++++Σ - a1z1– –() 2 1d⁄ Hz() Hz() Hz() Hnd z() K 2 a1K–= Hz() z1– 1z1– – ---------------- = Hnd z() 1 1z1– – ---------------- = Σ+ - y xB1 B2 d NTF z() NTF z() 1z1– –()–212K–()z1– ⋅z2– +–[]⋅ d ----------------------------------------------------------------------------------------- = dNTF z() K 24 optimally chosen to maximize the Signal-to-(Noise+Distortion) Ratio (SNDR). Indeed, practical cases may lead to a resolution increase of up to 10dB [7]. As an illustration, Fig.5(a) shows the optimal distribution of the zeros in the unity-circle for an oversampling ratio of 4, 8 and 16. The effect on the noise-shaping is depicted in Fig.5(b) by representing for the different cases. Another conclusion that is derived from (4) is that increasing (to reduce the quantization noise) yields a reduction of the feedback coefficient, , (see Fig.4). In practice, this results in a smaller capacitor ratio, which makes the electrical implementation more difficult and prone to circuit non-idealities. III. PROPOSED CASCADE ΣΔM ARCHITECTURES Previously reported resonation-based ΣΔMs like those shown in Fig.3 and Fig.4 require using BE or non-delayed integrators, [ ], which makes the electrical implementation using SC circuits more difficult and prone to circuit-level errors. Instead of that, the proposed architectures make use of both local and global resonation strategies and include FE-Integrator based loop-filters, that are more suited for implementing high-linearity low-voltage A/D converters than previous reported topologies. A. Proposed cascade ΣΔM with local resonation Fig.6 shows the proposed fourth-order ΣΔM architecture. This topology is a cascade architecture implementing local resonation with only delayed or FE integrators. The price to pay is that additional analog coefficients and a feedback path are needed. Note that this modulator is based on the one depicted in Fig.3 with two modifications. The first one is the use of a second-order single-loop FE-Integrator based resonator topology, proposed in [5], as the last stage of the resulting cascade. The second one is that only one branch − instead of two ones as in Fig. 3 − are needed to feed the first-stage quantization error to the input of the second stage. B. Proposed cascade ΣΔM with global resonation Fig.7 shows the second proposed topology, that makes use of unity STF at every stage whereas resonates through a feedback path from the last stage to the previous one, i.e. using global resonation. However, contrary to the cascade AFF-AFF ΣΔΜ, the modulator in Fig.7 feeds necessarily the last stage input through Fig. 4: Fourth-order Cascade ΣΔM with Global Resonator [7]. - +Σ - +Σ Σ + + +Σ - Σ - Σ + Σ - + - - d + z2– 2Hz()⋅1z1– –() 2 1d⁄ 2Hz()⋅ 12⁄H⋅nd z() + 12⁄H⋅nd z() c c c1 2 --- = aK d ---- = y xB1 B2 Σ a 10-3 10-2 10-1 100 –150 –100 –50 0 50 |NTF|2 (dB) Normalized frequency K 1 =0.027 K 2 =0.109 K 3 =0.4042 BW1 (OSR1=16) BW2 (OSR2=8) BW3 (OSR3=4) –1 –0.5 00.5 1 –1 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1 22 Real Part Imaginary Part K=0 K1=0.027 K3=0.4042 K3=0.4042 K2=0.109 K2=0.109 K1=0.027 1z 1– –() 4 Fig. 5: Optimum distribution of NTF zeroes in resonation-based ΣΔMs with different oversampling ratios. (a) Zero location in the unity-circle. (b) NTF vs. frequency. (a) (b) OSR3=4 OSR2=8 OSR1=16 OSR1=16 OSR2=8 OSR3=4 NTF z() NTF z() da Hnd z() 11z1– –()⁄= 25 two branches. However, since FE integrators are used, an additional analog delay − that can be implemented by proper clock-phase scheme [8] − is required. Nevertheless, in order to overcome the implementation of the extra analog delay, there is a more efficient mode to realize the global resonation with unity STFs stages. Indeed, analysing the linearized Z-transform of Fig.7, it can be shown that the input and the output of the second-integrator in the last-stage are respectively given by: (5) Note from (5) that the delayed quantization error of the last stage can be directly obtained as (6) This modification has been incorporated in Fig.7, resulting in the architecture depicted in Fig.8. Notice that the addition is already done at the Fig. 6: Proposed (I) Cascade ΣΔM with Local Resonator. - +Σ Σ + ++ - +Σ Σ +++ 2 +Σ + z2– Hz() Hz() Hz() Hz() K Kb a1z1– –() 2 1d⁄ a1K–= b2K–= y xB1 B2 d Fig. 7: A first approach to the Proposed Cascade with Global Resonation Topology. - +Σ+++ 2 - +Σ Σ +++ 2 +Σ - Σ Σ - d+ - -+ Hz() 1z1– –() 2 1d⁄ Hz() Hz() Hz() z1– aK d ---- = x4i2 x y B1 B2 aΣ X4z() z1– –1z1– –()E2 ⋅⋅z()= I2z() z2– –E2z()⋅= X4z() I2z()+z1– –E2z()⋅= Fig. 8: Proposed (II) Cascade with Global Resonation Topology. - +ΣHz() Hz() +++ 2 - +ΣHz() Hz() Σ +++ 2 1d⁄ +Σ - Σ + Σ+ 1z1– –() 2 - x4i2 xy B1 B2 aK d ---- = aa + d X4z() I2z()+ 26 input of the first-stage quantizer. Therefore −contrary to the modulator in Fig.4 − there is no need of an extra addition. Note that, in addition to avoiding the use of an extra delay, the ΣΔM in Fig.8 requires only one analog coefficient ( ) to make the resonation, instead of three coefficients [ , and ] as in Fig.6, which simplifies the electrical implementation and reduces the sensitivity to circuit non-idealities. IV. SIMULATION RESULTS In order to compare the performance of the proposed ΣΔM architectures (Fig.6 and Fig.8), several behavioral simulations has been done using SIMSIDES, a Simulink-based time-domain simulator for ΣΔ modulators [9]. All topologies operate with an oversampling ratio of 16, 4-bit internal quantizers, an inter-stage gain ( ) of 1 and a 1-V reference voltage. As an illustration, Fig.9 shows the effect of resonation on the output spectrum of the proposed topologies. Note that the resulting spectrum is the same for both architectures. The optimal feedback coefficient that causes the resonation in the topology depicted in Fig.8 is , resulting in a shift of two zeroes of the from 0 to . Note that, thanks to this optimum distribution of the zeroes, the in-band noise has already been minimized. This is better illustrated in Fig.10 where the SNDR is represented versus the input amplitude. In this example the resolution of the proposed architectures is slightly 10dB larger than the one obtained by the cascade AFF-AFF in Fig.2 within the whole input range. This increase of the SNDR is due to the use of resonation. Another advantage of the proposed architectures comes from the use of unity STFs yielding to the subsequent reduction of the amplifiers’ output swing. This is illustrated in Fig.11 and Fig.12 by plotting the histograms of the integrator outputs in the architectures proposed in this work and those previously reported. In addition, a classical cascade 2-2 architecture is also included in the comparison for completeness. Note that, the integrator output swings of the proposed modulators are similar to those in the modulator of Fig.2. However, they are smaller than the ones in the modulator of Fig.4. This is translated in a better linearity of the proposed architectures as compared to the one in Fig.4. KK1K–() 2K–() d Fig. 9: Modulator spectrum with resonation. 10-3 10-2 10-1 100 –250 –200 –150 –100 –50 0 Normalized Frequency PSD x freq. bin (dB) K0.027= NTF 0.9865 j0.1638⋅± NTF Fig. 10: SNDR versus input amplitude. –40 –35 –30 –25 –20 –15 –10 –5 0 5 40 50 60 70 80 90 100 110 120 Input Amplitude (dBFS) SNDR (dB) Proposed (I) and (II) AFF–AFF –0.2–0.15–0.1–0.0500.05 0.1 0.15 0.2 0 100 200 300 400 500 600 700 800 900 1000 Output Voltage (V) # Occurrences Fig. 11: Output swing requirements for the proposed topologies: a) Proposed (I) and b) Proposed (II). 3rd amp (OA3) 1st amp (OA1) 4th amp (OA4) 2nd amp (OA2) –0.2 –0.1 00.1 0.2 0 200 400 600 800 1000 Output Voltage (V) # Occurrences b) OA1 OA2OA3 OA4 OA1 OA2OA3 OA4 a) 27 The latter is illustrated in Fig.13 by plotting the effect of opamp gain non-linearity on the SNDR. In this simulation, a finite gain of 55dB is considered for all the amplifiers, while the gain second-order non-linearity for the first stage amplifiers is varied. The results of the previous simulations are summarized in Table 1, which shows the non-linearity that causes the SNDR to fall 3dB. Note that the robustness of the proposed architectures to non-linearities is similar (strictly speaking it is slightly smaller for this example) than the cascade AFF-AFF (Fig.2). However, the proposed ΣΔMs present an increased effective resolution by the action of resonation. On the other hand, compared with classical cascade (MASH) architectures, the presented ΣΔMs have better linearity performance. CONCLUSIONS Two novel topologies of cascade ΣΔMs have been presented. They combine resonation-based loop-filter with unity STF to achieve high-linearity whereas increasing resolution and robustness with respect to non-linearities as compared to previous approaches. These characteristics make the proposed modulators very appropriate for the implementation of low-voltage wideband A/D conversion. REFERENCES [1] X. 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Fig. 12: Output swing requirements for the amplifiers of: a) Classical MASH architecture, b) Global Resonation structure in Fig.4 and c) AFF-AFF in Fig.2. –1 –0.5 00.5 1 0 200 400 600 800 1000 1200 Output Voltage (V) # Occurrences –1 –0.5 00.5 1 0 200 400 600 800 Output Voltage (V) # Occurrences –0.2 –0.1 00.1 0.2 0 200 400 600 800 1000 Output Voltage (V) # Occurrences 3rd amp (OA3) 1st amp (OA1) 4th amp (OA4) 2nd amp (OA2) a) b) c) OA1 OA2 OA3 OA4 OA1 OA2 OA4 OA3 OA1 OA2 OA4 OA3 TABLE 1. Summary of non-linearity effects Topology Maximum non-linear gain Proposed (I) 4000% Proposed (II) 3500% AFF-AFF 5000% Classical MASH 10% 100101102103104 50 60 70 80 90 100 110 Gain non–linearity (%) SNDR (dB) Fig. 13: Non-linearities effect on the SDNR. Proposed (II) AFF-AFF Proposed (I) MASH 28