RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

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RD53 pixel eadou in eg a ed ci cui s o ATLAS
and CMS HL-LHC upg ades
To ci e his a icle: G. Alimon i
e al
2025
JINST
20 P03024
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This con en was downloaded om IP add ess 193.147.173.198 on 16/04/2025 a 09:35
2025 JINST 20 P03024
Published by IOP Publishing o Sissa Medialab
Recei ed: May 29, 2024
Re ised: No embe 6, 2024
Accep ed: Feb ua y 7, 2025
Published: Ma ch 19, 2025
RD53 pixel eadou in eg a ed ci cui s o ATLAS and
CMS HL-LHC upg ades
The RD53 collabo a ion
G. Alimon i,11 A. And eazza,11 F. A eche,22 M.B. Ba be o,1P. Ba illon,1R. Becche le,16
G. Bonomelli,20 G.M. Bilei,15 W. Bialas,3D. Bo ole o,5G. Calde ini,26 A. Ca a elli,3
A. Cassese,9J. Ch is iansen,3,∗E. Con i,3,15 F. C escioli,26 M. Daas,35 L. Damen i,9,10
S.D’Au ia,11 F. De Canio,13 G. De Robe is,8N. Dema ia,17 J. DeWi ,31 Y. Die e ,35
A. Dimi ie ska,25 W. E dmann,29 S. Esposi o,3D. Exa chou,3D. Fouge on,1L. Gaioni,13
M. Ga cia-Sci e es,25 D. Gnani,25 C. Gozalez Ren e ia,36 M. G ippo,17,18 A. Gua dino,36
M. Hame ,35 T. Heim,25 T. Hempe ek,35 F. Hin e keuse ,35 S. Huibe s,34 L.M. Ja a Casas,3
J.J. John,5J. Kampkö e ,33 M. Ka agounis,33 I. Kazas,27 Y. Khwai a,23 R. Klui ,28
D. Koukola,3A. K iege ,25 H. K üge ,35 J. Lalic,3M. Lau i zen,34 F. Licciulli,8Peilian Liu,21
F. Loddo,8E. Lopez Mo illo,6A. Lounis,23 F. Luongo,17,18 M. Manghisoni,13 S. Ma coni,3,15
F. Ma quez Lasso,6C. Ma zocca,30 K. Maue ,35 A. Mekkaoui,4Lingxin Meng,24
M. Menichelli,15 M. Menouni,1M. Minu i,16 M. Mi ono a,25 S. Mi yala,2M. Missi oli,29,32
E. Mon eil,17,18 K. Mous akas,35 F. Muñoz Cha e o,6G. Neue,7S. O anelli,3
A. Paccagnella,12 L. Pache ,17,18 F. Palla,16 F.R. Palomo Pin o,6A. Papadopoulou,25
A. Pa e no,17,18 A.R. Pe i,11 P. Placidi,15 R. Placke ,5A. P adas,22 A. Pulli,3B. Raci i,19
L. Ra i,
14
V. Re,
13
A. Rehman,
34
P. Rymaszewski,
35
P. Sande ,
20
M.C. Solal,
23
M. S andke,
35
B. S ugu,34 E. Thompson,25 G. T a e si,13 D. Vog ig,12 M. Vog ,35 Tianyang Wang,35
Hong ao Yang37 and J. Zdenko7
1Aix Ma seille Uni e si é, CNRS/IN2P3, CPPM, Ma seille, F ance
2B ookha en Na ional Labo a o y, Up on, NY, U.S.A.
3CERN, Eu opean O ganiza ion o Nuclea Resea ch, Gene a, Swi ze land
4Cle e Sys ems LLC , Wes Hen ie a, NY, U.S.A.
5Dep . o Physics, Ox o d Uni e si y, Ox o d, Uni ed Kingdom
6ETSI, Uni e sidad de Se illa, Se illa, Spain
7Facul y o Nuclea Sciences and Physical Enginee ing, Czech Technical Uni e si y in P ague,
P ague, Czech Republic
8INFN Sezione di Ba i, Ba i, I aly
9INFN Sezione di Fi enze, Flo ence, I aly
10Uni e si à di Fi enze, Flo ence, I aly
∗Co esponding au ho .
©2025 The Au ho (s). Published by IOP Publishing L d on behal o
Sissa Medialab. O iginal con en om his wo k may be used unde he
e ms o he C ea i e Commons A ibu ion 4.0 licence. Any u he dis ibu ion o his
wo k mus main ain a ibu ion o he au ho (s) and he i le o he wo k, jou nal ci a ion
and DOI.
h ps://doi.o g/10.1088/1748-0221/20/03/P03024
2025 JINST 20 P03024
11INFN Sezione di Milano and Uni e si à degli S udi di Milano, Milano, I aly
12INFN Sezione di Pado a and Uni e si à di Pado a, Pado a, I aly
13INFN Sezione di Pa ia and Uni e si à di Be gamo, Be gamo, I aly
14INFN Sezione di Pa ia and Uni e si à di Pa ia, Pa ia, I aly
15INFN Sezione di Pe ugia and Uni e si à di Pe ugia, Pe ugia, I aly
16INFN Sezione di Pisa, Pisa, I aly
17INFN Sezione di To ino, To ino, I aly
18Uni e si à di To ino, To ino, I aly
19Ins i u ü Expe imen alphysik, Uni e si ä Hambu g, Hambu g, Ge many
20Ins i u e o Pa icle Physics, ETH, Zu ich, Swi ze land
21Ins i u e o High Ene gy Physics, Beijing, People’s Republic o China
22Ins i u o Tecnologico de A agon, Za agoza, Spain
23Labo a oi e de Physique des 2 In inis I éne Jolio Cu ie, O say, CNRS / Uni e si è Pa is-Saclay,
Pa is, F ance
24Lancas e Uni e si y, Lancas e , Uni ed Kingdom
25Law ence Be keley Na ional Labo a o y, Be keley, CA, U.S.A.
26LPNHE, So bonne Uni e si é, Uni e si é Pa is Ci é, CNRS, Pa is, F ance
27Na ional Cen e o Scien i ic Resea ch, DEMOKRITOS, Agia Pa aske i, G eece
28Na ional Ins i u e o Suba omic Physics (NIKHEF), Ams e dam, Ne he lands
29Paul Sche e Ins i u , Villigen, Swi ze land
30Poli ecnico di Ba i, Ba i, I aly
31SCIPP, Uni e si y o Cali o nia, San a C uz, CA, U.S.A.
32Uni e si ä Zü ich, Zü ich, Swi ze land
33Uni e si y o Applied Sciences and A s Do mund, Do mund, Ge many
34Uni e si y o Be gen, Be gen, No way
35Uni e si y o Bonn, Bonn, Ge many
36Uni e si y o Cali o nia, Be keley, CA, U.S.A.
37Uni e si y o Science and Technology o China, He ei, China
E-mail: [email p o ec ed]
Abs ac : The RD53 collabo a ion has since 2013 de eloped new hyb id pixel de ec o chips wi h
50 ×50 μ
m
2
pixels o he HL-LHC upg ades o he ATLAS and CMS expe imen s a CERN. A
common a chi ec u e, design and e i ica ion amewo k has been de eloped o enable inal pixel
chips o di e en sizes o be designed, e i ied and es ed o handle ex eme hi a es o 3 GHz/cm
2
(up o 12 GHz pe chip) oge he wi h an inc eased igge a e o 1 MHz and e icien eadou o up o
5.12 Gbi s/s pe pixel chip. Tole ance o an ex emely hos ile adia ion en i onmen wi h 1 G ad o e
10 yea s and induced SEU (Single E en Upse ) a es o up o 100 upse s pe second pe chip ha e been
majo challenges o make eliable pixel chips. Th ee gene a ions o pixel chips, and many speci ic
mixed signal building blocks and adia ion es chips, ha e been submi ed and ex ensi ely es ed o
ge o inal p oduc ion chips. The la ge, complex and high a e pixel chips ha e been de eloped wi h a
s ong emphasis on low powe consump ion oge he wi h a concu en de elopmen and quali ica ion
o no el se ial powe ing a chip, module and sys em le el, o minimize de ec o ma e ial budge .
Keywo ds: F on -end elec onics o de ec o eadou ; Pa icle acking de ec o s (Solid-s a e
de ec o s); Radia ion-ha d elec onics; VLSI ci cui s
2025 JINST 20 P03024
Con en s
1 In oduc ion and equi emen s 1
2 Pixel de ec o sys em 6
3 Chip a chi ec u e 8
4 Analog on -ends and hi digi iza ion 10
4.1 CMS Linea on -end 19
4.2 ATLAS di e en ial on -end 24
5 Da a bu e ing and igge ing 29
6 Con ol and eadou 33
7 Powe and e e ences 37
8 Moni o ing 45
9 Radia ion ole ance 46
10 Implemen a ion 52
11 Ve i ica ion 56
12 Tes and cha ac e iza ion 59
13 Conclusions 63
1 In oduc ion and equi emen s
This pape gi es an o e iew o he gene al equi emen s, design, a chi ec u e and measu ed
pe o mance o he RD53 pixel chips, de eloped o he ATLAS and CMS High Luminosi y La ge
Had on Collide (HL-LHC) upg ades. This de elopmen has been a majo e o by a la ge numbe
o people (
∼100
) o e 10 yea s. The RD53 collabo a ion [
1
], wi h 24 ins i u es, was es ablished in
2013 o de elop he equi ed hyb id pixel de ec o eadou in eg a ed ci cui s o he ATLAS [
2
] and
CMS [
3
] pixel de ec o upg ades o he HL-LHC. The wo expe imen s ha e e y simila equi emen s
o hei pixel de ec o upg ades and bo h a e using lpGBT (low powe GigaBi T anscei e ) links [4]
o con ol and eadou . I was he e o e ag eed o do such a challenging chip de elopmen in common
among ATLAS and CMS pixel de ec o g oups wi h ASIC design and es expe ience. A common
a chi ec u e, design and e i ica ion amewo k has been de eloped o make inal p oduc ion pixel
chips, wi h sligh ly di e en chip sizes o enable op imal in eg a ion in o he wo pixel de ec o sys ems.
The gene al layou o he ATLAS and CMS pixel de ec o s a e indica ed in igu e 1.
–1–
2025 JINST 20 P03024
Figu e 1. Uppe : ATLAS acke layou wi h pixel de ec o a i s cen e. Lowe : one qua e o CMS pixel
de ec o layou . The pixel de ec o s a e highly compac a he cen e o he expe imen s wi h c i ical ma e ial
budge and di icul access. Bo h de ec o s a e cons uc ed om o e lapping ladde s/s a es o mul i (2,3 o
4) chip pixel modules o he cen al ba el pa and concen ic ings o he o wa d egions. Inne laye s a e
speci ically cons uc ed o enable pa ial eplacemen du ing long shu downs, in case o signi ican pe o mance
deg ada ion om adia ion damage in pixel senso s o pixel chips.
RD53 chips ha e been de eloped o mee he s ingen a e and adia ion equi emen s o
ope a ion a he HL-LHC, p ojec ed o begin ope a ion in 2030. The HL-LHC will ope a e a an
ins an aneous luminosi y o up o
7.5×1034
cm
−2
s
−1
co esponding o an a e age pileup o 200
inelas ic p o on-p o on collisions pe bunch c ossing. This ansla es in o an a e age pixel hi a e o
up o 3 GHz/cm
2
in he inne mos pixel laye a he 40 MHz bunch c ossing a e. Inne pixel laye s will
ha e o wo k eliably in an ex emely hos ile adia ion en i onmen wi h up o 1 G ad To al Ionizing
Dose (TID) and a Non Ionizing Ene gy Loss (NIEL) dose o 10
16
1 MeV n
eq
cm
−2
o e 10 yea s
ope a ion. I is assumed ha inne mos pixel laye (s) will possibly need eplacemen a e 5-10 yea s,
depending on he ac ual in eg a ed luminosi y and pixel senso and chip pe o mance deg ada ion.
The in eg a ion o he pixel de ec o s in he expe imen s has been made o enable pa ial eplacemen
o inne pixel laye (s). The ex eme adia ion le els equi e he pixel chip design o be made wi h a
s ong emphasis on ad-ha d design and e ec i e SEE (Single E en E ec s) p o ec ion. An inne
laye pixel chip can be es ima ed o ha e up o 100 Hz o SEUs (Single E en Upse s) and SETs
(Single E en T ansien s) and mus unc ion eliably despi e hese upse s in i s in e nal da a bu e s,
–2–

2025 JINST 20 P03024
s a e-machines and con igu a ion egis e s. This unp eceden ed adia ion ole ance equi emen is a
ac o
∼10
highe han wha has p e iously been made o High Ene gy Physics (HEP) applica ions
and a ac o
∼10
,000 highe han no mally equi ed o ad-ha d space applica ions.
The gene al chip equi emen s a e ou lined in able 1. The RD53 chip will be bump-bonded
o senso s wi h a pixel size o
50 ×50 μ
m
2
in he o wa d laye s and
25 ×100 μ
m
2
in he cen al
ba el laye s. These sizes a e
∼4
imes smalle han in p e ious gene a ion ATLAS and CMS pixel
senso s. This combined wi h he inc eased hi a e ( ac o
∼4
) and ex ended igge la ency ( ac o
∼2
) implies ha e ec i e igge la ency hi bu e ing has been inc eased by a ac o o mo e han
10 compa ed o cu en ATLAS [
7
] and CMS [
8
] pixel de ec o s. The inc eased igge a e, om
100 kHz o 1 MHz, combined wi h highe hi a e and smalle pixels implies ha e ec i e eadou
bandwid h is inc eased by a ac o
∼100
, main aining a 4 bi cha ge measu emen pe pixel hi .
Requi emen s o pixel senso capaci ance and adia ion induced leakage oge he wi h app op ia e
cha ge de ec ion h eshold ha e been de e mined om scaling om p e ious pixel de ec o s and
measu emen s on pixel senso p o o ypes in he wo expe imen s.
Table 1. Gene al equi emen s o RD53 pixel chips o use in ATLAS and CMS pixel de ec o s a HL-LHC.
A he pixel de ec o le el i is c i ical o keep he ma e ial budge o pixel de ec o modules
and ela ed se ices as small as possible, so as no o de e io a e signi ican ly acking pe o mance
–3–
2025 JINST 20 P03024
om pa icle sca e ing and con e sions in he pixel de ec o and i s ela ed cooling, powe ing and
eadou se ices. The chip powe consump ion mus be kep as small as possible, a simila le el as
he p e ious gene a ion pixel chips, despi e signi ican ly highe pixel densi y and complexi y wi h
highe hi and eadou a es. The use o a scaled CMOS echnology is c i ical o keep an accep able
powe consump ion, om educed capaci i e loading o on-chip ga es and he educ ion o powe
supply ol age (Powe scales wi h powe supply ol age as
𝑉2
DD
). An un o una e side e ec o powe
supply ol age scaling is ha o he same powe consump ion, he equi ed powe supply cu en
inc eases, posing p oblems making an app op ia e low mass powe dis ibu ion sys em. The use o
swi ched mode DC-DC powe con e sion on he pixel chip, o on he pixel module, was in es iga ed,
bu excluded because o he equi ed adia ion ole ance and associa ed space and ma e ial budge o
local induc i e o capaci i e powe con e e s. A no el se ial powe ing scheme has he e o e been
adop ed, wi h on-chip SLDO (Se ial Low D opOu ) powe egula o s, based on ini ial easibili y
demons a ions wi h he FEI4 chip [
5
,
26
,
31
]. This pa icula se ial powe dis ibu ion sys em has
been de eloped, es ed and quali ied a he chip, module and sys em le el, while he RD53 pixel
chips we e ac i ely being de eloped.
The i s yea s o de elopmen in RD53 we e ocused on adia ion ole ance s udies o he chosen
65 nm CMOS echnology and implemen ing and es ing he equi ed adia ion ha d building blocks:
Digi al o Analog Con e e s (DAC), Analog o Digi al Con e e (ADC), Analog pixel F on -Ends
(AFE), biasing s uc u es, band-gap e e ence, Phase Locked Loop (PLL), Inpu -Ou pu s (IO), SLDO
powe egula o and empe a u e and adia ion senso s. An app op ia e hi bu e ing, p ocessing and
eadou a chi ec u e o he high hi and igge a es was de eloped and ex ensi ely simula ed and
e i ied in a lexible simula ion and e i ica ion amewo k wi h de ec o Mon e Ca lo hi da a.
A i s 1/2 sized pixel chip called RD53A, submi ed in 2017 on a sha ed submission, has been
used o e i ica ion o de eloped building blocks and gene al a chi ec u e. RD53A has also been
ins umen al as a es ehicle o es and quali y di e en pixel senso s [
6
] and o sys em s udies,
co e ing se ial powe ing, design and es ing o pixel modules and es ing wi h lpGBT based eadou
sys em wi h op ical links o he o -de ec o DAQ. A la ge se o i adia ion es campaigns ha e been
made wi h his chip o ge a good unde s anding o eliable unc ionali y o such a complex chip
co e ing TID (To al Ionizing Dose) e ec s as a unc ion o empe a u e, dose a e e ec s, and ini ial
SEE es s. Th ee di e en analog on -ends we e p esen in his chip oge he wi h wo di e en
igge la ency bu e ing schemes o de e mine he mos app op ia e implemen a ion o inal chips.
A second gene a ion o RD53 chips, named RD53B-ATLAS & RD53B-CMS [
9
,
10
], a e
comple e ull sized pixel chips made wi h he chosen la ency bu e a chi ec u e and imp o ed building
blocks. RD53 de eloped a lexible pa ame e ized design and e i ica ion en i onmen whe e ull
cus om mac os and Regis e T ans e Le el (RTL) code a e ins an ia ed acco ding o he speci ic
ATLAS o CMS implemen a ions. The RD53B gene a ion chips we e made speci ically o each
expe imen (RD53B-ATLAS, known as ITkPix 1 in ATLAS, and RD53B-CMS, known as CROC 1
in CMS) wi h hei speci ic AFEs and chip size adap ed o speci ic in eg a ion cons ain s o each
expe imen . These wo chips, submi ed in 2020 and 2021, a e unc ionally equi alen wi h he
same con ol and eadou in e aces, wi h mino speci ic ea u es ela ed o he analog on -ends
and speci ic ea u es and bugs. The RD53B-ATLAS chip un o una ely had non- unc ional TOT
(Time O e Th eshold) cha ge measu emen and could only be used wi h bina y eadou . The RD53B
gene a ion chips ha e been ins umen al o ex ended chip es ing in RD53 and pixel module and
–4–
2025 JINST 20 P03024
Figu e 2. RD53A o RD53C chip gene a ions wi h chip submission da es.
sys em de elopmen s, es ing and quali ica ion in he ATLAS and CMS pixel de ec o g oups. The
e olu ion o he RD53 chips is shown in igu e 2.
Bug ixes and imp o emen s ha e been made in he inal gene a ion p oduc ion chips: RD53C-
ATLAS and RD53C-CMS [
11
]. Moni o ing unc ions ha e been imp o ed and ex ended. SEU and
SET ole ance ha e been signi ican ly imp o ed based on ex ensi e RD53B ion, p o on and lase beam
es ing and SEU/SET simula ions a ansis o , ga e and RTL le el. Tes ing o se ially powe ed quad
chip pixel de ec o modules, in he ATLAS and CMS pixel de ec o g oups, ha e enabled sys em
issues o be iden i ied and co ec ed. An ex ended e i ica ion amewo k was speci ically de eloped
o exhaus i e unc ional and SEU/SET e i ica ion.
The la ge scale p o o ype chips RD53A, RD53B-ATLAS and RD53B-CMS ha e been p oduced
and ex ensi ely es ed as epo ed in his pape . Final p oduc ion e sion chips, RD53C-ATLAS and
RD53C-CMS, ha e ecen ly been submi ed and a e in p oduc ion o use in he expe imen upg ades.
The RD53C chips ha e ecen ly been h ough ex ensi e chip es ing and cha ac e iza ion, wi h es
esul s as epo ed in his pape . They a e used o pixel module p e-p oduc ion o la ge scale sys em
es s. Wa e le el p oduc ion es se ups ha e been de eloped and quali ied o he wo expe imen s.
Tes esul s shown in his pape a e in gene al o he ba e pixel chip wi hou a pixel senso ,
unless speci ically men ioned in he igu e cap ion. Bump bonded pixel chip and pixel senso
assemblies ha e only ecen ly become a ailable in su icien quan i y and quali y o make de ailed
chip cha ac e iza ion o hese wi h measu emen s shown in sec ion 12. Ex ensi e pixel module es ,
cha ac e iza ion and quali ica ion is cu en ly ongoing in he ATLAS and CMS pixel g oups wi h
hei speci ically chosen pixel senso s.
The chip a chi ec u e and implemen a ions a e ou lined oge he wi h ci cui de ails o c i ical
blocks o achie e equi ed pe o mance in he hos ile adia ion en i onmen . Mos o he discussions
make no dis inc ion be ween he ATLAS and CMS chips, as hese a e based on a common a chi ec u e
wi h only mino implemen a ion di e ences. The pape is o ganized as ollows. Sec ion 2p o ides a
sho o e iew o he planned use o he pixel chips in he ATLAS and CMS pixel de ec o s. Sec ion 3
gi es an o e iew o he pixel chip a chi ec u e. Sec ion 4desc ibes he analog on -ends, pe o ming
pixel hi de ec ion wi h a 4 bi cha ge measu emen . Sec ion 5ou lines hi da a bu e ing du ing he
igge la ency and ollowing da a p ocessing. Sec ion 6de ines he con ol and eadou in e aces.
Sec ion 7co e s he on-chip se ial powe egula o and he gene a ion o biasing and e e ences.
Sec ion 8desc ibes he implemen ed on-chip moni o ing ea u es. Sec ion 9summa izes adia ion
ole ance aspec s. Sec ion 10 ou lines he in eg a ion and implemen a ion. Sec ion 11 desc ibes
inal unc ional and SEU/SET e i ica ion. Sec ion 12 summa izes gene al es esul s and wa e
p obing. Finally sec ion 13 concludes he pape .
–5–
2025 JINST 20 P03024
2 Pixel de ec o sys em
The upg aded pixel de ec o sys ems o ATLAS [
2
] and CMS [
3
] a e made o ha e he same on -end
con ol, eadou and powe ing in e aces de ined o he RD53 pixel chips. Pixel chips a e in eg a ed
on dual, iple o quad pixel chip modules wi h a single bump-bonded pixel senso . E ec i e hi a es
and equi ed eadou a es ha e a s ong dependency on he adial dis ance o he in e ac ion poin
(
𝑟−2
). Inne laye chips equi e up o 5.12 Gbi s/s eadou bandwid h, while pixel chips in ou e laye s
only need a ac o 20–50 lowe eadou bandwid h (depending on de ec o layou , numbe o laye s
and ba el e sus o wa d). The eadou ia he lpGBT has he e o e been de ined o allow a high le el
o eadou link modula i y o minimize he numbe , and ma e ial, o equi ed eadou links. Each
pixel chip can use om 1 up o 4 se ial Elec ical links (E-links) a 1.28 Gbi s/s (lpGBT max E-link
speed). RD53 pixel chips can also be used in a p ima y-seconda y con igu a ion, whe e eadou da a
om 2 o 4 pixel chips a e me ged in o a single 1.28 Gbi s/s link as illus a ed in igu e 3wi h pixel
module p o o ypes shown in igu e 4. Mul iple chips on he same pixel module a e con olled wi h a
single 160 Mbi s/s con ol link ca ying clock, con igu a ion and eal- ime con ol in o ma ion. In
ATLAS, con ol and eadou links be ween pixel chips and he lpGBT a e up o 8 m long [
24
], using
a dedica ed cable d i e and equalize GBCR ASIC [
23
] . In CMS, wi h an E-link dis ance limi ed
o 1.5 m, he pixel chips a e connec ed di ec ly o he lpGBT.
Se ial powe ing is used in bo h pixel de ec o sys ems o minimize he ma e ial budge o he
powe dis ibu ion. The powe supply cu en on a single powe cable pai is used o powe up o
16 pixel modules in se ies as shown in igu e 5. Mul iple pixel modules a e powe ed in se ies wi h
a cons an cu en and on-chip SLDO egula o s dynamically adjus hei chip powe impedance,
o ha e cons an and well egula ed local ol ages o he analog and digi al pa s o he chip. In
such a powe ing scheme i is c i ical o minimize luc ua ions in ci cui powe consump ion and ha e
su icien cu en head oom and local decoupling capaci o s o enable he local powe egula o s o
abso b such luc ua ions, as shown in igu e 5in uppe igh plo . Each chip has sepa a e analog
and digi al SLDO egula o s, connec ed in pa allel o he common inpu powe , o assu e he bes
possible isola ion o he sensi i e analog on -ends om swi ching noise induced in he powe ails
by he digi al ci cui s. The e ec i e load impedance is dynamically egula ed wi h a con olled
shun cu en , main aining cons an inpu ol ages and cu en s, independen ly o he ac ual cu en
consumed by he analog and digi al ci cui s in he chip.
Such a cons an cu en (and cons an ol age) powe ing sys em is highly ad an ageous in sys ems
whe e low noise is p imo dial and whe e long powe cables will ha e signi ican ol age d ops.
Assu ing cons an powe supply cu en s also p e en s powe cables in s ong magne ic ields o ha e
induced dynamic o ces wi h possible esonances. Sys em d awbacks o se ial powe ing a e he
powe dissipa ed in he on-chip egula o s , wi h necessa y cu en (10–20 %) and ol age (0.2–0.3 V)
head ooms, adding up o a o al powe o e head o 20–40 %. In pa icula , i he pixel chip goes
in o a low powe s a e, he on-chip egula o s will ha e o dissipa e he ull nominal chip powe
as shown in igu e 5lowe igh he mal image. Bo h pixel de ec o s will be cooled wi h highly
e icien high p essu e CO
2
cooling sys ems ha will be designed o cope wi h his. Ano he sys em
issue wi h se ial powe ing is he equi emen ha all con ol and eadou links o/ om he pixel
chips mus ha e AC coupling, wi h app op ia e DC balanced link encoding. Special ca e mus be
aken o sys em g ounding as pixel module g ounds can no be connec ed o sys em g ound, which
implies he need o good gal anic isola ion be ween pixel chips and local CO
2
cooling. The High
–6–
2025 JINST 20 P03024
en o cing a sho a e age TOT ime below 133 ns. In ou e low a e laye s a longe TOT ime can
be used o ge be e cha ge esolu ion.
I can be men ioned ha i he cha ge in eg a ed analog signal has ampli ude sa u a ion e ec s,
he TOT cha ge measu emen can be co ec ed o -line, when used a low h esholds as indica ed in
igu e 11. I he de ec ion h eshold is se a a cha ge le el below whe e he sa u a ion e ec se s in, he
leading edge is de ec ed a he co ec le el. Sa u a ion e ec s occu ing abo e he h eshold de ec ion
le el will a ec he TOT pulse wid h. This can be co ec ed o o line i his non-linea i y has
been app op ia ely cha ac e ized. This TOT non-linea i y can hough ha e ela i ely la ge a ia ions
be ween indi idual pixels and be sensi i e o empe a u e and adia ion e ec s.
Small hi signals, jus abo e h eshold (e.g. a edge o pixel clus e s), will ge ime walk om
he combined e ec o analog signal shape and he disc imina o eac ing slowe when ha ing small
signal o e -d i e. Fo a ime-walk below 20 ns (25 ns clock pe iod minus 5 ns sampling ma gin
o sys em ji e and ime alignmen o collisions) he hi will be de ec ed in he app op ia e bunch
c ossing o igge ed eadou . Fo ime walk la ge han his, he hi can be seen as a low TOT/cha ge
′′
noise
”
hi in he ollowing bunch c ossing and will he e o e no be ead ou o he co esponding
igge (unless o cing double igge ing).
Each expe imen has chosen hei speci ic low powe AFE implemen a ion based on hei speci ic
emphasis on pa icula pe o mance cha ac e is ics. The di e en ial AFE used in he ATLAS chip
has pa icula emphasis on low noise and small ime-walk. The linea AFE used in he CMS chip
has pa icula emphasis on linea i y (
∼5
%) and capabili y o wo k wi h sho analog/TOT dead- ime
in inne high a e pixel laye s [
16
]. The wo AFEs ha e simila e ec i e a ea and in e aces and a e
in eg a ed in o he RD53 design amewo k wi h a ew design con igu a ion pa ame e s.
Mul iple biasing le els o he AFEs a e de ined by global con igu a ion egis e s connec ed o
biasing DACs d i ing he analog pixel a ay ia column d i e s as shown in igu e 12:
•
P e-ampli ie bias: de e mines he e ec i e speed o AFE cha ge in eg a ion, bu also a ec s
e ec i e gain, noise and dispe sion. Majo con ibu o o AFE powe consump ion.
•
TOT discha ge cu en : de e mines he discha ge a e o in eg a ed cha ge, he eby de ining
TOT esolu ion and ela ed analog dead- ime.
•Disc imina o bias: de e mines he e ec i e speed (and ime-walk) o disc imina o .
•
Global h eshold: global chip h eshold on o which local pixel h eshold adjus men is applied.
•Th eshold adjus ange: de e mines he ange o local h eshold adjus DACs.
Biasing o he AFEs has signi ican e ec s on hei beha io and is a delica e op imiza ion o
be done acco ding o he allowed powe consump ion, hi a e, noise, ime walk and pixel senso
cha ac e is ics. I will also be needed o ake in o accoun accumula ed adia ion e ec s in bo h
pixel senso and he pixel chip i sel . Edge and co ne pixels ha e sepa a e p e-ampli ie biasing as
hey a e ypically 2-4 imes la ge o co e he gap be ween pixel chips on mul i-chip pixel modules
(e.g. quad pixel modules) and minimize insensi i e a eas a pixel module edges. This is o ganized
in 6 g oups: Main, Le side, Righ side, Top, Top Le co ne , Top Righ co ne , as indica ed in
igu e 12, o enable lexible adap a ion o di e en pixel senso and module con igu a ions wi h enla ge
pixels in bounda y egions be ween pixel chips.
– 13 –

2025 JINST 20 P03024
Figu e 12. AFE bias dis ibu ion wi h di e en p e-amp biasing o di e en pixel egions: Main (M), Le side
(L), Top Le side (TL) , Top (T), Righ side (R), Top Righ (TR).
The leading edge o he disc imina o hi signal is a measu e o he pa icle Time O A i al
(TOA), wi h associa ed ime walk, and he Time O e Th eshold (TOT) is p opo ional o he collec ed
cha ge. The leading edge is synch onized o he 40 MHz sampling clock and he pulse wid h is
measu ed wi h he ising o bo h edges o he 25 ns sampling clock (40 and 80 MHz TOT sampling)
o a 6 bi TOT coun . The 6 bi TOT coun can be mapped di ec ly in o 4 bi TOT, igno ing he 2 MSB
(Mos Signi ican Bi s) bi s wi h sa u a ion, o can be mapped in o 4 bi s wi h a dual slope mapping.
Wi h dual slope mapping he ull TOT esolu ion is main ained in he i s hal o he 4 bi dynamic
ange, whe eas ex ended dynamic ange is ob ained in he second hal as illus a ed in igu e 13. Dual
slope mapping assu es good posi ion in e pola ion a he edge o pixel clus e s, whe e he collec ed
cha ge is no mally small, and high dynamic ange o dE/dx measu emen s o pixel clus e s ha can
be used o iden i y highly ionizing pa icles and con ibu e o gene al pa icle iden i ica ion [
15
].
Cap u e o he disc imina ed hi signal can be pe o med synch onously o asynch onously. Fo
synch onous/simple sampling, sho hi s no p esen a he ising edge o he sampling clock will be
igno ed. Fo asynch onous/la ched sampling, a disc imina o hi pulse is kep high un il i has been
cap u ed by he i s coming 40 MHz sampling clock edge. Async sampling is gua an eed o cap u e
sho hi pulses, bu will ha e sligh ly highe sensi i i y o noise hi s as indica ed in igu e 14. One
should also be awa e ha sho /small hi s will ypically also be a ec ed by ime-walk. In RD53B chips
he hi sampling mode was con igu able. Fo he inal RD53C chips, ATLAS has chosen he async
sampling mode, gi en he low noise and low ime-walk AFE and issues i ing bo h modes in a ailable
a ea. Fo he RD53C-CMS chip i has been possible o main ain bo h sampling modes.
The 40 MHz sampling clock o he hi de ec ion in he indi idual pixels is ca e ully dis ibu ed
ac oss he pixel a ay wi h ypical (maximum) ime skew ac oss he whole a ay below 1 ns (2 ns)
– 14 –
2025 JINST 20 P03024
Figu e 13. Measu ed Linea and Dual slope TOT wi h 40 MHz and 80 MHz sampling using digi al pulse wid h
injec ion. Le : CMS chip wi h pulse wid h in BX uni s (25 ns) and TOT=15 ep esen ing no hi (so no shown).
Righ : ATLAS chip wi h pulse wid h injec ion in ns and TOT=0 ep esen ing no hi . Does no include analog
non-linea i y o he AFE (desc ibed la e ).
Figu e 14. Hi sampling wi h synch/asynch sampling. Indica ion o op ional 80 MHz TOT sampling.
o assu e ha hi s a e cap u ed in he co ec bunch c ossing o igge ing and eadou . This gi es
sho digi al powe su ges o e he pixel a ay a he ising edge o he clock ha can a ec he analog
on -ends and hi digi iza ion. Local decoupling capaci o s a e dis ibu ed ac oss he a ay o minimize
his e ec and he AFEs ha e been decoupled as much a possible om he digi al wi h sepa a e powe
domains and he use o sepa a e iple wells o analog and digi al. A h eshold a ia ion o e he
40 MHz clock pe iod has been obse ed in he ull RD53 chips as indica ed in igu e 15 and igu e 16.
This can be seen o be ela ed o on-chip powe dis ibu ion wi h ou dis ibu ed sub-ins ances o
each SLDO. The magni ude o his e ec is dependen on he sampling mode used (sync o async)
and on he con igu ed TOT discha ge a e ( as /slow). The Async sampling mode, assu ed o cap u e
incoming hi s in he ull clock cycle is in insically less sensi i e o he a i al ime o hi s. A a
1000 e h eshold he async sampling will ha e a 50 e ( as shaping assumed use in inal applica ion)
- 450 e (slow shaping) h eshold a ia ion e ec . This has been measu ed o be p opo ional o he
numbe o pixel co e columns ac i ely being clocked and will he e o e also in p ac ice depend on
powe decoupling and wi e-bonding ( esis ance and induc ance) on a pixel module. The measu ed
h eshold a ia ion ac oss he pixel a ay is caused by s a ic and dynamic ol age d ops in he on-chip
powe dis ibu ion ne wo k wi hin he pixel a ay and ou dis ibu ed ins ances o he SLDOs. In
– 15 –
2025 JINST 20 P03024
Figu e 15. Le : RD53B-ATLAS h eshold a ia ion (async sampling) ac oss clock cycle om powe supply
pe u ba ions [
56
]. Righ : h eshold a ia ion ampli ude ac oss pixel a ay o e layed on RD53B layou wi h
indica ion o dis ibu ed SLDOs in ou g oups. DVCAL is digi al h eshold con igu a ion DAC in s eps o 5 e.
sync sampling mode, he e ec i e hi cap u e h eshold has a ela i ely la ge dependency on he
ela i e phase o he sampling clock and used TOT discha ge a e as shown in igu e 16, because
sho hi s can be missed depending on i s ela i e iming/phase o he sampling clock. I has no been
possible o imp o e his u he o a one-side powe ed chip, needed o quad chip pixel modules
wi h no dead de ec ion zones be ween chips. I should be no ed ha di ec pa icles om he bunch
collisions o he LHC a i e wi hin a ela i ely na ow ime window (
∼1
ns) and will he e o e no be
signi ican ly a ec ed by his. I is o each expe imen o de e mine how hey wan o ime align hei
pixel de ec o o he bunch collisions, using p og ammable delays in hei iming dis ibu ion sys em
and in he RD53 chip, and how o ob ain app op ia e absolu e h eshold and cha ge measu emen
calib a ion, using calib a ion pulse injec ions in he RD53 chip.
Disc imina ed hi signals om indi idual pixels, wi h local enables, a e also connec ed o a
con igu able hi -OR column ne wo k o measu e Time O A i al (TOA) and TOT wi h 640 MHz
p ecision TDCs (Time o Digi al Con e e ) in he Digi al Chip Bo om (DCB). The hi -OR signals a e
also used o a lexible sel - igge unc ion ha can be used o de ailed chip and senso cha ac e iza ion
in es beams and wi h adioac i e sou ces. An example o using he p ecision TOA is shown in
igu e 17 o measu e calib a ion injec ion and hi -OR skew along pixel columns in he RD53B-ATLAS
chip (imp o ed in RD53C chips o ha e educed skew), and measu e analog pulse shape wi h a
h eshold scan using he p ecision TOA and TOT.
An analog injec ion ci cui is implemen ed in each pixel, wi h an equi alen ci cui as shown in
igu e 18, o pe o m p ecise h eshold uning and calib a ion. The calib a ion injec ion ci cui uses
wo dis ibu ed DC ol ages (Vcal_Med and Vcal_Hi), om wo on-chip 12 bi s DACs, ollowed by
in-pixel swi ches o gene a e cha ge injec ions ia a pixel injec ion capaci o (Cinj). Ha ing wo cha ge
injec ion ol ages enables p ecise di e en ial cha ge injec ions (Vcal_Hi - Vcal_Med), independen o
g ound ol age d ops ac oss he pixel a ay, as well as making wo consecu i e injec ions (Vcal_Hi
- Vcal_Med ollowed by Vcal_Med - g ound) in o he same pixel. The iming o he injec ion is
– 16 –
2025 JINST 20 P03024
Figu e 16. RD53B-CMS Th eshold a ia ion ac oss clock cycle. Uppe le : sync sampling mode o di e en
TOT discha ge a es om Fas (K um=190) o Slow (K um=50). Uppe igh : async sampling mode. Lowe
le : 2D map o async h eshold a ia ion ac oss pixel a ay in as mode wi h 10 e colo s ep. Lowe igh :
es ima ed max h eshold a ia ion e ec o as (inne ) and no mal (ou e laye s) discha ge a e o 3D and
plana pixel senso s. Rep oduced wi h pe mission om [17].
24
Recen S udies — F on -end Scope Scan
Adjus ing pa ame e s o he analog on -end and measu ing hei impac
on he analog on -end ou pu
Di V con ols he cons an -cu en
discha ge in he eedback ci cui y in
he i s s age o he analog on end
As he discha ge a e inc eases, he pulse wid h (ToT) dec eases — bu also
he pulse ampli ude ( he discha ge a e begins o o e ake he cha ge-up a e)
Figu e 17. RD53B-ATLAS p ecision TOA and TOT. Le : digi al pixel injec ion ac oss pixel a ay wi h
measu ed TOA using he high esolu ion TDC ia he hi -OR ne wo k. Righ : analog pulse shape econs uc ed
om measu ed TOA and TOT wi h high esolu ion TDC, o e di e en cha ge injec ions. Di V se s he
cha ge in eg a ion discha ge cu en o he Di e en ial AFE and he shaded a ea indica es he sp ead among
pixels in he pixel a ay.
– 17 –
2025 JINST 20 P03024
con olled by a digi al pulse gene a o wi h p og ammable injec ion ime (0.78 ns esolu ion) and
ime be ween wo consecu i e injec ions, using he wo calib a ion ol ages plus local g ound. The
same pulse gene a o can be used o di ec digi al hi injec ions.
Two 12 bi ol age DACs loca ed in he ACB gene a e he cha ge injec ion ol ages, d i en wi h
dedica ed ol age d i e s o he in-pixel cha ge injec ion ci cui s in each pixel. The DAC cha ac e is ics
a e shown in igu e 18. Calib a ion injec ion has an e ec i e esolu ion o
∼5
e when being used
concu en ly on a limi ed numbe (
∼100
) o pixels. Used o massi e concu en injec ions in a
la ge numbe o pixels, he e ec i e p ecision is de e io a ed by dynamic capaci i e loading om
he ol age swi ches in he pixels. Injec ion capaci ance sp ead among chips on he same wa e has
been seen o be 1 - 1.5 % wi h a 5-10 % di e ence be ween wa e s.
Figu e 18. Calib a ion injec ion ol age as unc ion o DAC se ing wi h a linea i and ex ac ed DNL
(Di e en ial Non-Linea i y) and INL (In eg al Non-Linea i y). Pixel cha ge injec ion ci cui shown as an
inse wi h i s wo injec ion ol ages (Vcal_Med, Vcal_Hi) and local g ound, enabling wo consecu i e cha ge
injec ions o be made.
A dedica ed cha ge injec ion capaci o calib a ion ci cui , shown in igu e 19, is a ailable in he
ACB o make a p ecise injec ion capaci o measu emen pe chip, du ing wa e p obing o enable
calib a ed cha ge injec ions in he inal sys ems.
Shown AFE es esul s a e in gene al o ba e chips wi hou bump-bonded pixel senso s. Bump
bonded assemblies wi h senso s ha e only ecen ly become a ailable in su icien quan i y and quali y
o make de ailed AFE cha ac e iza ion wi h hese. No signi ican changes in pixel chip pe o mance
ha e been seen when es ed wi h a bump bonded pixel senso , excep an AFE noise inc ease o 10–30 e,
as can be expec ed when ha ing inc eased inpu capaci ance [
19
].
– 18 –

2025 JINST 20 P03024
Figu e 19. Le : Pixel Injec ion capaci o (C es ) measu emen ci cui measu ing he a e age cu en , wi h
on-chip ADC (GADC) o ex e nal pin (V_Mux_pad), when cha ging and discha ging he injec ion capaci o
a a cons an injec ion a e. An equi alen b anch, wi hou injec ion capaci o , enables o measu e pa asi ic
capaci ance (Cp) o he ci cui . Righ : measu ed injec ion capaci o dispe sion o e wo wa e s om he same
p oduc ion lo .
4.1 CMS Linea on -end
The schema ic o he linea analog on -end [
18
,
19
] adop ed in he RD53B/C-CMS chip is shown in
igu e 20 wi h a Cha ge Sensi i e Ampli ie (CSA) wi h K ummenache eedback [
14
] complying
wi h he expec ed adia ion induced de ec o leakage and p o iding a linea discha ge o he eedback
+
CF
V e
IK
IK/2
VDDA
V h
Injec ion
ci cui Vou ,csa
senso
bump PAD
CK
Vou ,comp
5-bi
h eshold
uning DAC
Figu e 20. Schema ic o CMS linea analog on -end.
– 19 –
2025 JINST 20 P03024
Figu e 21. T ansis o le el implemen a ion o linea AFE p e-ampli ie (le ) and compa a o ( igh ).
capaci o
𝐶𝐹
. The choice o a single ampli ica ion s age is dic a ed by powe consump ion and a ea
cons ain s wi h a cha ge sensi i i y, se by
𝐶𝐹
, o a ound 26 mV/ke
−
. The signal om he CSA is
ed o a low powe compa a o wi h a 5 bi , cu en -mode bina y weigh ed DAC o local h eshold
uning. The on -end has been op imized o a linea esponse o an inpu cha ge up o 30 ke and
ea u es an o e all cu en consump ion o 5
μ
A.
The cha ge sensi i e ampli ie , shown in igu e 21 le , is based on a olded cascode inpu s age
wi h wo local eedback ne wo ks, composed o he M4-M5 and M7-M8 pai s, boos ing he signal
esis ance a he ou pu node. A 3
μ
A biasing cu en in he inpu b anch and 200 nA in he cascode
b anch a e esponsible o mos o he powe consump ion wi h a simula ed open-loop DC gain o
76 dB wi h
−3
dB cu o equency a 140 kHz wi h an e ec i e closed loop peaking ime o 22 ns.
Noise is domina ed by he inpu de ice and he PMOS ansis o in he eedback. The compa a o
shown in igu e 21 igh , has a ansconduc ance s age (M1-M5) ollowed by a T ans-Impedance
Ampli ie (TIA) (M6-M10) o as swi ching, wi h an op imized eedback ne wo k (M6 and M7) o
accep able ime-walk. Two in e e s a e used a he ou pu o assu e as signal ansi ions o he digi al
pixel sampling logic. The layou and measu ed analog pulse shape a e shown in igu e 22.
Figu e 22. Le : linea AFE layou . Righ : ypical analog wa e o m be o e compa a o , wi h 1–10 ke cha ge
injec ions, measu ed on analog ou pu o he RD53A chip.
– 20 –
2025 JINST 20 P03024
Figu e 23. RD53B-CMS Linea AFE pulse shape and h eshold linea i y. Le : econs uc ed pulse shape
om h eshold and ime scan combined wi h high p ecision TDC in o ma ion, in as mode wi h sho TOT
cha ge encoding. Righ : h eshold as unc ion o global h eshold se ing. GDAC: global h eshold se ing,
Del aVCAL: injec ion ol age DAC se ing (5 e pe LSB).
Figu e 24. RD53B-CMS Linea AFE ime-walk as unc ion o injec ed cha ge (Le ), a slow discha ge and
sync mode, and a di e en empe a u es ( igh ), a 1000 e h eshold o di e en combina ions o sync/async
mode and as /slow discha ge a e.
A econs uc ed AFE pulse shape om a combined scan o injec ion ime and h eshold wi h
TOT is shown in igu e 23 oge he wi h h eshold linea i y as unc ion o global h eshold se ing.
Figu e 24 shows he ime-walk measu ed as unc ion o injec ed cha ge oge he wi h ime-walk
dependency on chip empe a u e wi h sync and async sampling and o as (inne laye s) and slow
(ou e laye s) TOT discha ge imes. TOT linea i y, wi h sa u a ion, is shown in igu e 25 oge he
wi h i s dependency on sampling clock phase o di e en cha ge injec ions and TOT sp ead ac oss
he pixel a ay. Figu e 26 shows un uned (be o e local h eshold imming) h eshold dispe sion
o e he ull pixel a ay oge he wi h a 2D map o app op ia e pixel imming o ob ain uned pixel
h eshold dispe sion as shown in igu e 27, when using he op imal imming DAC ange o co e
he ull dispe sion ange wi h he bes possible esolu ion. Tuned pixel h eshold dispe sion a 1000 e
be o e and a e 1 G ad i adia ion is shown in igu e 28 wi h only a small deg ada ion o h eshold
dispe sion (a e e- uning a 1 G ad). Finally pixel noise dis ibu ion is shown in igu e 29 a oom
empe a u e and cold wi h mean noise as unc ion o empe a u e o as and slow TOT discha ge. No
no iceable change o noise has been obse ed wi h i adia ion up o 1 G ad.
– 21 –
2025 JINST 20 P03024
0 500 1000 1500 2000 2500 3000 3500 VCal∆
0
2
4
6
8
10
12
14
ToT
D_B(0)_O(0)_H(0)_Gain_Chip(15)
En ies 5806080
Mean x 1901
Mean y 7.462
S d De x 1125
S d De y 4.704
1
10
2
10
3
10
4
10
5
10
D_B(0)_O(0)_H(0)_Gain_Chip(15)
En ies 5806080
Mean x 1901
Mean y 7.462
S d De x 1125
S d De y 4.704
2000 4000 6000 8000 10000 12000 14000 16000 18000
Cha ge (elec ons)
Figu e 25. RD53C-CMS Linea AFE TOT linea i y and sp ead. Le : a e age TOT alue as unc ion o
injec ed cha ge wi h linea encoding up o 15 ke, o in e es o hi posi ion in e pola ion be ween pixel hi s in
pixel clus e , o di e en ela i e clock phases (CE uni = 25 ns/32 = 0.78 ns). Righ : measu ed TOT linea i y
and sp ead ac oss pixel a ay.
Figu e 26. RD53B-CMS Linea AFE un uned h eshold dispe sion oge he wi h 2D im DAC alues o ge
uni o m h eshold (e ec i ely shows un uned h eshold map). Del a VCAL = 5 e. A column s uc u e is clea ly
isible, coming om columns o pixel islands wi h hei biasing d i e s.
No di e ences ha e been seen o he linea AFE in he RD53B-CMS and RD53C-CMS chips.
In sho i can be summa ized ha he linea AFE wi h a plana (o 3D) bump-bonded pixel senso
complies wi h he de ined equi emen s in able 1and wo ks ully sa is ac o y o he CMS pixel
de ec o upg ade a a 1000 e h eshold wi h
∼50
e dispe sion, mean noise below
∼70
e (80-100 e
wi h pixel senso ), ime walk below 17 ns wi h a linea TOT cha ge measu emen and adia ion
ole ance up o 1 G ad. A he ime o w i ing, ex ended es ing o he RD53C-CMS chip is ongoing
in he CMS pixel de ec o p ojec wi h di e en senso ypes on p e-p oduc ion modules in es
beams and a e i adia ion.
– 22 –
2025 JINST 20 P03024
Figu e 39. RD53C-ATLAS Di e en ial AFE noise a ia ion a 1000 e h eshold. Le : be o e and a e 1 G ad
I adia ion. Righ : a ia ion ac oss pixel a ay a e 1 G ad.
0 100 200 300 400 500 600 700 800 900 1000
Noisy pixel h eshold [e]
1
10
2
10
3
10
4
10
Numbe o pixels
ITkPix-V1.1 Chip SN: 0x162D7
(a)
0 200 400 600 800 1000
Pixel h eshold [e]
0.95
0.96
0.97
0.98
0.99
1
F ac ion o good pixels
ITkPix-V1.1 Chip SN: 0x162D7
(b)
Figu e 40. RD53B-ATLAS Di e en ial AFE noisy pixels as unc ion o h eshold. Le : numbe o noisy
pixels ( ela i e noise occupancy g ea e han 10−6). Righ : ac ion o no -noisy pixels. The di e en ial AFE
can be seen o ha e excellen noise pe o mance wi h h esholds as low as 500 e.
pixel de ec o upg ade a a 1000 e h eshold wi h
∼50
e dispe sion, noise o
∼55
e (65-85 e wi h
pixel senso ), ime walk as low as
∼15
ns, a comp essed TOT cha ge measu emen , and adia ion
ha dness up o 1 G ad. A he ime o w i ing, ex ended es ing and quali ica ion o he RD53C-ATLAS
chip is ongoing in he ATLAS pixel de ec o p ojec wi h inal pixel senso s on p e-p oduc ion
modules in es beams and a e i adia ion.
5 Da a bu e ing and igge ing
Al e na i e hi bu e ing and igge ing a chi ec u es ha e been e alua ed o choose a inal im-
plemen a ion ul illing igge la ency bu e ing equi emen s, wi h he lowes possible hi loss
and accep able powe consump ion. Fi ing he logic in he a ailable a ea in he pixel a ay is a
c i ical design cons ain . Sha ing o hi bu e ing be ween 4 neighbo pixels was quickly iden i-
– 29 –

2025 JINST 20 P03024
ied o be c i ical o p o i om locally clus e ed hi s om a single pa icle ( ypically om 1–4
pixel hi s pe clus e ). Ini ial s udies ound a pixel egion o
2×2
pixels o be ideal o he high
hi a e in he middle o he inne ba el laye . Fu he s udies, wi h de ailed Mon e Ca lo hi
da a om di e en pa s o he de ec o s, wi h bo h
50 ×50 μ
m
2
and
25 ×100 μ
m
2
sized pix-
els, de e mined ha a pixel egion o
4×1
pixels is a be e o e all op imiza ion o he wo
pixel de ec o layou s. Pixel hi s a e clus e ed om a e sing pa icles depending on mul iple
ac o s: loca ion o a e sing pa icle, pa icle angle, senso hickness, magne ic ield, and also
adia ion damage in he pixel senso . Two al e na i e bu e ing a chi ec u es we e implemen ed
in he RD53A p o o ype [
12
]. The “ze o-supp essed FIFO” a chi ec u e uses wo le els o sha ed
FIFOs o minimize he equi ed numbe o s o age bi s, a he cos o inc eased logic complex-
i y. The “dis ibu ed la ency coun e ” a chi ec u e minimizes logic complexi y, a he cos o an
inc eased use o memo y cells. Bo h schemes we e ound ully unc ional in simula ions and
in he RD53A chip. The inal choice o using he dis ibu ed la ency coun e a chi ec u e was
based on e ec i e hi losses, and minimizing logic and layou complexi y o assu e bes possible
SEU/SET ole ance.
Sampled pixel hi signals a e p ocessed and bu e ed in small local pixel egions consis ing o 4
pixels. When one, o mul iple, pixels in a pixel egion ha e a hi , a 4 bi TOT egis e pe pixel s o es
he measu ed TOT. The ou TOT alues in he pixel egion a e s o ed in a local la ency bu e loca ion
oge he wi h a 9 bi Bunch ID ime-s amp om a cen al 40 MHz Bunch-ID coun e , as indica ed in
igu e 41. A TOT egis e alue o 1111 bin indica es ha no pixel hi has been de ec ed. W i ing
o a 4 pixel bu e loca ion is comple ed when all 4 TOT coun ing measu emen s a e inalized. The
pixel egion hi cap u e and bu e ing is non-blocking so a new hi a i ing in ollowing clock cycles,
on a pixel no pa o he i s clus e , is cap u ed in he nex ee bu e loca ion. Each pixel egion
has 8 local la ency bu e loca ions. Hi losses om he limi ed hi bu e ing, a he highes hi a es
o 3 GHz/cm
2
, ha e been modeled and simula ed wi h Mon e Ca lo hi da a and shown o be well
below 1 % [
12
], as shown in igu e 42. Signi ican design e o s ha e been in es ed o i he equi ed
la ency bu e ing in he highly cons ained pixel a ea, using a cus om made compac mul i-bi la ch
and highly op imized logic. E ec i e hi losses ha e been measu ed wi h X- ay i adia ions o a pixel
module, as shown in igu e 43 and scaled o an icipa ed HL-LHC hi a es (compensa ed o di e en
clus e size be ween X- ays and pa icles in he HL-LHC en i onmen ).
When a la ency bu e loca ion is in ac i e use, he s o ed Bunch ID is con inuously compa ed
o a global la ency coun e wi h a ela i e o se , de ining he e ec i e igge la ency. When hey
ma ch and an ac i e igge is gene a ed, he bu e loca ion is lagged as igge ed, o he bu e
loca ion is eleased. Bunch ID in o ma ion is hen eplaced wi h a igge e en ID o handle he
eadou o mul iple pending igge ed e en s wi h hi da a.
Digi al logic in he pixel a ay uses op imized clock ga ing o ob ain signi ican powe sa ings.
The hi cap u e logic in he pixel egion has ac i e local clocking only du ing he cap u e window o a
hi (e ec i e ime window depends on TOT leng h), making he ins an aneous powe consump ion
dependen on hi a es. This equi es ca e ul op imiza ion o local powe decoupling capaci o s, bo h
on-chip and on pixel modules, o wo k eliably wi h se ial powe ing.
Readou o igge ed hi da a om he local pixel egion la ency bu e s is con olled by a co e
column eadou con olle a he end o each co e column bus. Pixel co es, consis ing o
2×8
pixel
egions (
8×8
pixels), sha e a co e column eadou bus, wi h i s associa ed con olle in he DCB.
– 30 –
2025 JINST 20 P03024
Figu e 41. Pixel egion logic o dis ibu ed la ency coun e bu e ing wi h TOT and Bunch-c ossing ID ime
ags (Times amp coun ). Hi de ec ion is made pe pixel, wi h s o age o associa ed hi TOTs (blue). Hi ime
s amps a e s o ed in common wi h associa ed bu e managemen logic, handling igge ing and oken based
eadou om he pixel a ay (yellow). Rep oduced wi h pe mission om [12].
Figu e 42. Le : pixel egion la ency bu e occupancy p obabili y o he wo al e na i e a chi ec u es e alua ed.
The selec ed a chi ec u e is he dis ibu ed la ency coun e bu e s o
4×1
pixel egions. I has lowes hi
loss o high hi a es and has he simples and mos compac implemen a ion. Righ : hi loss p obabili y o
dis ibu ed la ency coun e bu e s wi h de ec o Mon e Ca lo hi s a 3 GHz/cm
2
o 7, 8 and 9 bu e loca ions.
Eigh Bu e loca ions a e used in inal chip implemen a ions as i i s in he a ailable a ea and ha e accep able
hi loss in he highes a e egions (below 0.25 %). Rep oduced wi h pe mission om [12].
– 31 –
2025 JINST 20 P03024
012345678
0.80
0.85
0.90
0.95
1.00 AllP ima y ROC3 [12.5 s]
Digi al E iciency
D
= /
A
-co ec ed X- ay Hi a e [
GHz
/
cm
2]
0123456
]
2
Expe imen hi a e [GHz/cm
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1
1.01
1.02
CROC bu e ing e iciency
( egion- o pixel- a e a io: 0.655)
= 0 inne ladde )η(TBPX laye 1,
a e simula ion-based a e co ec ion
sµe iciency @ L1 la ency = 12.5
Measu ed a e age CROC bu e ing
Phase 2, PU 200 (14 TeV)
CMS
Simula ion P elimina y
Figu e 43. RD53B-CMS X- ay hi loss p obabili y om la ency bu e ing as unc ion o hi a e, measu ed in
a non i adia ed chip wi h a plana senso . Le : co ec ed o analog TOT dead- ime. Righ : o es ima ed
equi alen HL-LHC hi a e, wi h pa icle clus e size o 1.53 hi s/clus e .
Readou om he pixel a ay is ini ia ed by he co e column con olle signaling he e en ID and
asse ing a eadou oken. Pixel egions ha ing igge ed hi da a awai he a i al o he eadou
oken and hen asse hei hi da a on he eadou bus oge he wi h i s pixel egion add ess and
passes he oken. When he oken inally e u ns o he pixel co e column con olle , all e en da a in
he co e column o his e en ID has been collec ed. Pixel co e columns ha e independen eadou
con olle s ha can be in he p ocess o eading ou di e en e en s. This imp o es he e ec i e
eadou a e om he a ay when ha ing mul iple pending igge ed e en s. A cen al igge able
keeps ack o e en s awai ing eadou om he pixel a ay.
A pixel co e column bus is co e ing a la ge numbe o pixel egions. This limi s he e ec i e
eadou speed on his long bus and makes i signi ican ly a ec ed by adia ion deg ada ion o i s
bus d i e s and handshake logic. The e ec i e eadou ime is wo clock cycles pe pixel egion
wi h hi da a, ha wi h adia ion deg ada ion can ge as long as 3(4) clock cycles (con igu able). I
has been con i med in simula ions ha such a educed pixel a ay eadou speed is compa ible wi h
equi ed hi and igge a es. In p ac ice i has no ye been seen necessa y o use his ex ended
eadou pe iod o highly i adia ed chips.
I is possible by con igu a ion o cons ain he maximum numbe o pixel egions o ead ou
om each co e column pe e en , o p e en possible eadou conges ion om e en s wi h excessi e
numbe o hi s. I is also possible o cons ain he maximum ime a ailable o eadou all pixel co e
columns, he eby e ec i ely cons aining he maximum numbe o hi s pe e en .
An ex ended wo le el igge mode o po en ial u u e igge upg ades has been implemen ed.
In his mode, L0 igge ed hi s emain in he pixel egion la ency bu e s o a con igu able ime-ou
pe iod (max 25.6
μ
s). Du ing his ime-ou pe iod (L1 igge la ency), e en s can be lagged o
eadou (L1 accep ), o by de aul be ejec ed (L1 ejec ).
E en da a accep ed o eadou will go h ough mul iple le els o p ocessing, e en building,
bu e ing and o ma ing, as shown in igu e 44, be o e being eady o inal eadou ia he se ial
eadou links. To al e en da a bu e ing be o e inal eadou is o he o de o 25 kBy es in he DCB.
Signi ican hi da a bu e ing also akes place in he pixel a ay, om when a igge is ecei ed un il
ha ing been ead ou om he pixel a ay. This bu e ing assu es e icien hi da a de- andomiza ion
ha enables good eadou bandwid h u iliza ion.
– 32 –
2025 JINST 20 P03024
Figu e 44. Ou line o p ocessing and bu e ing o e en da a in mul iple s ages om pixel co e columns, p ocessed
by End O Column (EOC) logic, o inal eadou link Au o a o ma ing ia Clock Domain C ossing (CDC) bu e .
In e media e FIFO’s a e used o da a bu e ing o enable he di e en s ages o wo k concu en ly o sus ain he
equi ed bandwid h. Ba el-shi e s a e used o e ec i e da a me ging and e-packaging o ze o-supp essed e en
da a be ween p ocessing s ages. Colo s shown in da a bu e s ep esen e en da a, belonging o same igge ed
e en , in di e en s ages o p ocessing. Da a low: igge ed hi s a e ead ou o he pixel a ay wi h ci cula ing
ead okens in he co e columns o hi map encode s wi h column add esses o EOC bu e s. Hi da a om EOC
bu e s a e me ged in wo bu e ing s ages (DC and CDC bu e s) o o m 64 bi da a wo ds o chip eadou .
6 Con ol and eadou
The con ol and eadou in e aces o he RD53 chips a e highly cons ained om hei speci ic use in
an inne high a e and low mass de ec o wi h lpGBT based op ical links o DAQ and con ol sys ems.
An e icien a iable leng h hi da a encoding o ma , called bina y ee encoding, has been de eloped
o minimize eadou bandwid h. The use o 1, 2, 3 o 4 eadou links pe pixel chip, and he op ion
o me ging da a om 2 o 4 chips in o one link, enables he numbe o equi ed eadou cables o
be op imized and minimized o di e en sys em con igu a ions. Con ol and eadou links use DC
balanced encoding, o he AC coupled links equi ed in a se ially powe ed de ec o sys em.
A 160 Mbi s/s DC balanced di e en ial con ol link, wi h ansmission e o de ec ion, has been
speci ically de eloped o add ess up o 15 chips (e.g. chip speci ic con igu a ion) and wi h b oadcas
capabili y (e.g. common con igu a ion). I has an embedded 40 MHz e e ence clock wi h sub-ns
iming con ol, o app op ia ely align pixel hi sampling wi h bunch collisions. Real ime commands
a 25 ns le el ha e p io i y o e con ol, con igu a ion and moni o ing commands. The con ol link
has su icien bandwid h o pe o m con inuous sc ubbing o pixel con igu a ion, in case needed in
he hos ile adia ion en i onmen (see sec ion 9).
– 33 –
2025 JINST 20 P03024
A adia ion ha d 1.28 GHz Phase Locked Loop (PLL) has been de eloped o app op ia e Clock
and Da a Reco e y (CDR) om he con ol link and gene a e he clock o he se ial eadou links.
Ini ial p o o ypes ha e been ex ensi ely es ed and g adually imp o ed o ge lowe ji e wi h su icien
TID and SEU/SET ole ance [
21
,
22
]. The PLL locks o he 160 Mbi s/s con ol s eam and gene a es
he equi ed on-chip clocks. The 40 MHz hi sampling clock is gene a ed wi h a ame alignmen
ci cui , based on egula sync symbols. I can be phase shi ed in s eps o 0.78 ns o pe o m p ecise
ime alignmen o pa icles om he HL-LHC collisions. The PLL is sepa a ely powe ed o allow
addi ional ex e nal il e ing o he analog chip powe in case needed. The classical PLL a chi ec u e,
wi h equency and phase de ec o s, is shown in igu e 45 wi h measu ed ji e and eye diag am
o a eadou link shown in igu e 46.
Figu e 45. PLL gene a ing high equency clocks used in he chip. PLL con ol loop wi h combined Phase
De ec o (PD) and Phase - F equency De ec o (PFD) con olling a Vol age Con olled Oscilla o (VCO) ia
analog Cha ge Pumps (CP) and loop il e . F equency mul iplica ion om he 160 Mbi s/s con ol link o he
1.28 GHz se ialize clock is ob ained wi h SEU p o ec ed coun e s (CNT and DIV).
Figu e 46. Measu ed eye diag am and PLL ji e on 1.28 Gbi s/s se ial eadou .
Pa icula emphasis has been pu on e icien and eliable s a up, ese ing and con igu a ion
o he chips o use in a se ially powe ed de ec o sys em in a hos ile adia ion en i onmen . A
– 34 –

2025 JINST 20 P03024
powe -on s a up (see also SLDO s a up in sec ion 7) he chip will ini ially use a de aul ha dwi ed
con igu a ion. Only when all c i ical e-con igu a ion da a ha e been downloaded, will hese se ings
be ac i a ed wi h a dedica ed enable code. Full chip da a pa h and bu e s can be clea ed quickly o
speci ic pa s o he chip can be ese wi h speci ic commands. In a wo s case scena io whe e con ol
link synch oniza ion is los , and i does no sel eco e as i should no mally be he case, a dedica ed
link ese can be applied ha ini ializes all chip con igu a ion and s a s a ull chip e-synch oniza ion
(as done a powe up). This is done by unning he con ol link a a low equency (in alid link bi a e,
bu s ill compa ible wi h AC coupling), ha is de ec ed by he chip o be ou o no mal wo king ange.
This emo es he need o using powe cycling o eco e chip ope a ion, which is highly undesi able
in a la ge se ial powe ed sys em wi h high ol age senso biasing.
Up o 4 eadou links o 1.28 Gbi s/s (o 640 Mbi s/s o 320 Mbi s/s) a e a ailable pe chip o
eadou and moni o ing. A subse o he Au o a encoding [
20
] is used as i suppo s all he equi ed
ea u es: DC balanced 64B/66B encoding, aming wi h minimum o e head, mul i lane suppo , da a
and se ice ype ames. Au o a o ma ing is well documen ed and well suppo ed o FPGAs in es
and DAQ sys ems, wi h gene al e en and se ice da a o ma ing as indica ed in igu e 47. When used
in inal ATLAS/CMS pixel de ec o s wi h lpGBT op ical links, wo le els o link encoding (Au o a
64B/66B plus lpGBT FEC) will be p esen , o be decoded by he DAQ sys em FPGAs. I should be
no ed ha Au o a o ma ing does no use Fo wa d E o Co ec ion (FEC). Single bi ansmission
e o s (o SEUs in pixel chip se ialize ) can he e o e occasionally cause he co up ion o e en
agmen s. The use o FEC was conside ed bu i was ound o ha e oo la ge bandwid h o e head,
especially in combina ion wi h he ex ensi e e o co ec ion used in he lpGBT. The RD53C-CMS
chip has he op ion o add a CRC (Cyclic Redundancy Check) a he end o each e en .
Raw ze o-supp essed hi da a om he pixel egions consis o a pixel egion add ess ollowed by
4 bi TOT in o ma ion om he 4 pixels in he egion, wi h TOT=1111 bin indica ing no hi . This is
al eady a ela i ely e icien da a o ma o clus e ed hi s, compa ed o indi idual pixel hi add esses
wi h TOT (18 bi pixel add ess + 4 bi TOT = 22 bi pe hi ). An op imized bina y ee hi encoding
scheme can u he educe eadou bandwid h by 10–20 %. I is also possible o supp ess TOT cha ge
eadou in o ma ion, ha ing only bina y hi in o ma ion, gi ing a da a educ ion o
∼30
%.
In bina y h ee encoding, he 16 bi hi map om 4 pixel egions co e ing
8×2
pixels, is encoded
o p oduce a comp essed hi map ep esen a ion, wi h ewe han 16 bi s pe hi on a e age o clus e ed
hi da a. The algo i hm di ides he hi map, con aining one o mul iple hi s, in hal (e.g. uppe and
lowe hal as shown in uppe igh co ne o igu e 47) and labels each hal as con aining hi s (1) o
no (0). This is applied ecu si ely o e e y non-emp y hi pa e n un il only 2 bi hi pa e ns a e le .
A bi code subs i u ion is hen applied o comp ess his. In any s ep, he wo-bi code 00, o he wo
hal es wi hou hi s, is ze o-supp essed. Code 01 is ep esen ed by a single bi se o 0, while 10 and 11
a e kep as a 2 bi code. This esul s in a comp essed 16-pixel hi map wi h be ween 5 bi s (single hi )
and 30 bi s (all 16 pixels hi ). The encoded hi map is p eceded by a pixel hi map add ess (loca ion in
ull pixel a ay) and ollowed by pixel hi TOT(s). This encoding is in he chip implemen ed wi h
simple and as logic based on a small look-up able. A complex Hu man encoding was in simula ions
seen o ob ain 10-20 % be e comp ession on HL-LHC da a, bu equi es complex on-chip p ocessing.
The e ec i e numbe o bi s pe hi wi h bina y ee encoding has wi h Mon e Ca lo hi da a been
seen o be in he ange o 10-15 bi s/hi , as shown in igu e 48 depending on clus e size. This can
be compa ed o he aw ze o-supp essed hi da a o ma wi h 14-28 bi s/hi .
– 35 –
2025 JINST 20 P03024
Figu e 47. Ou line o e en building wi h bina y hi encoding and eadou o ma ing. Uppe le : e en
building, wi h hi encoding (Enc) and bu e ing (FIFO), be ween e en agmen s ( igge ed hi s) om pixel
a ay co e columns, made om pixel co es wi h pixel egions, o inal e en da a s eams. Uppe igh : bina y
ee hi encoding, aking ad an age o mul iple pixel hi s in local clus e s. Lowe : encoding o pixel da a
(physics e en da a) and se ice da a (moni o ing o egis e eads), indica ed in 64B/66B ames. Pixel
da a consis s o a 8 b e en ag/ID and bina y ee encoded pixel add esses, ollowed by co esponding TOT
in o ma ion ha can op ionally be omi ed. Pixel da a om single igge ed e en s can be con ained in well
sepa a ed single-e en s eams, indica ed wi h EOS (End O S eam) = 1, wi h equi ed 64B/66B ame bi
padding a he end. Al e na i ely pixel da a eadou can be made wi h mul i-e en s eams, wi h educed bi
padding o e head. Se ice da a ames a e sen a egula in e als (con igu able) wi h eques ed moni o ing
and con igu a ion ead-back da a. Rep oduced wi h pe mission om [11]
When ha ing a small numbe o pixel hi s pe chip, as is he case o ou e pixel laye s, a ela i ely
la ge o e head is used o e en heade in o ma ion and equi ed 66 bi ame padding a he end. An
op ional mul i-e en s eam o ma ing, wi h mul iple e en s sha ing a single ansmission s eam, can
educe his o e head. I mus hough be kep in mind ha a single bi ansmission e o (o SEU,
SET) can hen co up mul iple e en s. I is he e o e encou aged o use single s eam e en o ma ing
when e e possible, as his enables co ec da a decoding o be ees ablished a he s a o each e en .
Da a me ging be ween chips is a ailable o low a e ou e pixel laye s, o me ge eadou da a om
2 o 4 chips on a pixel module in o a single eadou link, he eby signi ican ly educing he numbe o
– 36 –
2025 JINST 20 P03024
6−
10 5−
10 4−
10 3−
10 2−
10
Pixel occ.
10
2
10
A g. hi size [Bi ]
ηClus e ex ends in
Clus e size = 1
Clus e size = 2
Clus e size = 3
Clus e size = 5
Clus e size = 10
6−
10 5−
10 4−
10 3−
10 2−
10
Pixel occ.
0.6
0.8
1
1.2
1.4
Bina y/Plain
Figu e 48. Simula ed numbe o bi s pe hi wi h bina y ee encoding and 4 bi TOT as unc ion o pixel hi
occupancy and clus e size. Lowe : ela i e da a bandwid h gain om bina y ee encoding.
equi ed eadou links/cables. A p ima y chip is d i ing a single 1.28 Gbi s/s eadou link and 1 o 3
seconda y chips d i e 320 Mbi s/s se ial da a on a local single o dual lane link o he p ima y chip.
Chip o chip da a me ging equi es he chips o be d i en by he same con ol link and he in e ace
is based on o e sampling a 640 MHz in he p ima y chip. Used in a lexible manne , a quad pixel
chip module can be con igu ed o ha e 4, 3, 2 o only 1 eadou links as shown in igu e 49. Da a
me ging uses simple ame by ame ime mul iplexing wi h a 2 bi sou ce ID, so he DAQ sys em
mus handle 2 o 4 independen e en s eams on he eadou link.
E en eadou la ency ( ime in e al om ecei ing igge message o comple ion o co esponding
e en eadou ) will ha e a complex dependency on s a is ical luc ua ions in hi s and igge s and he
a ailable eadou bandwid h as indica ed in Mon e Ca lo simula ions shown in igu e 50. The eadou
la ency can become pa icula ly long i he eadou bandwid h is highly u ilized (e.g. abo e 90 % ). The
chip will e en ually be o ced o d op e en s, i on-chip da a bu e s un ull ( lagged in chip moni o ing).
Readou links a e d i en by di e en ial CML (Cu en Mode Logic) d i e s wi h con igu able
d i e cu en and p e-emphasis. The d i e has a 100 Ohm di e en ial ou pu impedance, assu ing he
bes possible ma ching o low mass 100 Ohm di e en ial elec ical cables ( wis ed pai , lex mic o
s ip-lines, winax), wi h he abso p ion o possible ansmission e lec ions.
7 Powe and e e ences
RD53 chips ha e on-chip SLDO powe egula o s o se ial powe ing o pixel modules, wi h chips
on he same module connec ed in pa allel [
30
]. Se ial powe ing o pa allel connec ed chips on a
pixel module enables he use o a single sha ed pixel senso o mul iple chips and also assu es
sys em eliabili y when ha ing pixel chip powe ailu es (opens). The SLDOs can also be (ha dwa e)
– 37 –
2025 JINST 20 P03024
Figu e 49. Da a me ging be ween p ima y and seconda y chips on a lexible quad module ha can be con igu ed
o ha e 4, 3, 2 o 1 ac i e eadou links. Up o ou 1.28 Gbi s/s eadou links shown in blue on module connec o
in cen e . Local 320 Mbi s/s da a me ging links be ween chips shown in yellow.
Figu e 50. Simula ed eadou la ency o pixel chip wi h 3 eadou E-links. Uppe : a 2.7 GHz/cm
2
hi a e, o
di e en igge a es. Lowe : a 1 MHz igge a e, o di e en hi a es. I can be no iced ha he eadou
la ency ge s excessi ely long abo e an a e age eadou link u iliza ion o 90-95 % . Abo e a eadou link
u iliza ion o 95% he e is a signi ican isk o loosing e en agmen s.
– 38 –
2025 JINST 20 P03024
8 Moni o ing
RD53 chips ha e ex ensi e on-chip moni o ing capabili ies [
36
] co e ing: on-chip empe a u e senso s,
pixel module empe a u e wi h ex e nal NTC (Nega i e Tempe a u e Coe icien ) he mis o , SLDO
inpu and ou pu ol ages and cu en s, in e nal e e ences and biasing le els, plus adia ion e ec s
moni o ing. Analog moni o ing is pe o med wi h an ADC con e sion eques command on he
con ol link ollowed by an ADC ead eques . Moni o ing da a a e ead ou in dedica ed Au o a
se ice ames on he eadou links as indica ed in igu e 47.
Analog moni o ing is made wi h a mul iplexed 12 bi swi ched capaci o ADC [
37
,
38
] wi h
layou shown in igu e 60 and wi h measu ed esolu ion and linea i y as shown in igu e 61. Absolu e
ADC calib a ion pe chip is pe o med du ing wa e p obing, wi h ADC calib a ion pa ame e s o
each chip being s o ed in a cen al da a base.
Figu e 60. 12 bi swi ched capaci o moni o ing ADC layou wi h analog moni o ing mul iplexe .
Figu e 61. 12 bi ADC linea i y and INL.
The swi ched capaci o ADC co e has been shown o ha e excellen adia ion ole ance. Howe e ,
adia ion es campaigns ha e shown a signi ican d i o abou 5% o 500 M ad, 10% o 1 G ad, o
moni o ed ol ages. This o igina es om a TID d i o he ADC e e ence, which di ec ly impac s
– 45 –

2025 JINST 20 P03024
ol age measu emen s as shown in igu e 62. A me hod o co ec o he TID d i o he ADC e e ence
has been de eloped, based on speci ic p ope ies o he used empe a u e senso s as desc ibed below.
Th ee empe a u e senso s in he chip bo om, close o he SLDO powe egula o s, a e based
on la ge-a ea NMOS ansis o s biased in sub- h eshold egion. Tempe a u e measu emen accu acy
has been g ea ly imp o ed by making mul iple measu emen s a di e en cu en s (con igu able)
in he NMOS senso . I has been possible o demons a e an e ec i e empe a u e linea i y and
esolu ion o
∼1◦
C as shown in igu e 63 wi h good TID ole ance. This measu emen does no
depend on he ADC e e ence ol age and allows o con ain TID e ec d i s o alues lowe han
2
◦
C a 500 M ad [
36
]. This allows o deduc he eal ol age ac oss he empe a u e senso s and use
he appa en ol age measu ed by he ADC o co ec o he ol age measu emen s acco dingly o
ge an e ec i e TID d i o 1–2% o ol age moni o ing. Two esis i e empe a u e senso s wi h
lowe esolu ion a e a ailable o measu e empe a u e g adien ac oss he pixel a ay. These esis i e
empe a u e senso s a e e y na ow o i on op o he pixel a ay.
Figu e 62. RD53B moni o ing dependency on adia ion induced ADC e e ence d i . When using he ADC o
measu e adia ion d i s in he biasing e e ence, VREFA, he appa en TID d i seems small (yellow), as bo h
e e ences ha e simila TID d i s. I VREFA is measu ed wi h an ex e nal ADC (blue
&
g een) hen i s eal
5 % TID d i a 500 M ad becomes isible.
Radia ion e ec s moni o ing o digi al logic is made wi h a se o digi al ing oscilla o s wi h
di e en ga e ypes and ansis o sizes and o analog ansis o s by di ec analog measu emen s
on a ew e e ence MOS ansis o s. The ing oscilla o equency is measu ed using he 40 MHz
chip/sys em clock as e e ence, om which he e ec i e ga e delay can be calcula ed. Typical ga e
delays o he implemen ed ing oscilla o s can be seen in igu e 65 as unc ion o TID.
9 Radia ion ole ance
Achie ing he equi ed adia ion ole ance o he RD53 pixel chips o 1 G ad o 10 yea s ope a ion
in inne pixel laye s a HL-LHC has been a majo challenge. The used 65 nm echnology has been
seen o ha e excellen adia ion ole ance up o dose le els o
∼100
M ad [
39
]. To each an e ec i e
TID ole ance o up o 1 G ad, he RD53 collabo a ion has in es ed signi ican e o s on adia ion
e ec s s udies wi h dedica ed adia ion es chips. Ini ially i was hough impossible o implemen
such a complex mixed signal chip wi h 1 G ad adia ion ole ance, as adia ion es s showed la ge
ansis o and ci cui deg ada ion a adia ion le els abo e 100 M ad. Wi h sys ema ic adia ion es s
– 46 –
2025 JINST 20 P03024
Figu e 63. Calib a ion o 3 (A,C,D) on-chip MOS based empe a u e senso s in clima ic chambe . The NTC he -
mis o is a e e ence senso on he es boa d. The measu ed empe a u e di e ence be ween he clima ic chambe
and he NTC senso is caused by he pixel chip powe dissipa ion. Do ed line showing ideal cu e, as an eye guide.
o di e en ansis o ypes and sizes unde di e en i adia ion condi ions ( ol age, empe a u e, dose
a e), indica ions we e ound on how o each 500 M ad, and po en ially highe , adia ion ole ance
wi h speci ic design cons ain s and unde pa icula ope a ion condi ions. Dedica ed analog and
digi al ci cui es chips we e made o con i m ha his seemed iable [
41
–
43
]. Finally, i has been
con i med wi h ull sized pixel chips (RD53B/C gene a ions) ha 1 G ad is easible, when using
speci ic design p ecau ions and ope a ion condi ions as ou lined below.
Wide ansis o s ha e excellen adia ion ole ance wi hou signi ican leakage (o he simila
echnologies ha e been seen o ha e ansis o leakage issues). This has enabled app op ia ely designed
analog ci cui s o demons a e excellen adia ion ole ance. In he RD53B chips, issues we e seen
wi h inc eased misma ch in c i ical cu en mi o s o biasing di e en pa s o he chip. The o igin
o his was aced o be an x- ay shielding e ec om hick op coppe ou ing laye s abo e c i ical
ansis o s, as was seen o be signi ican ly smalle wi h p o on i adia ion. In inal RD53C chips i is
assu ed o ha e he same hick coppe ou ing abo e c i ical cu en biasing ansis o s.
Na ow ansis o s show la ge adia ion deg ada ion, wi h addi ional de imen al annealing when
ope a ed a ele a ed empe a u e, especially unde speci ic biasing condi ions, as indica ed in igu e 64.
Na ow 65 nm ga e leng h ansis o s a e c i ical in high densi y logic, pa icula ly needed in he
pixel a ay logic. T ansis o s in digi al logic a e only unde wo s case biasing condi ions du ing e y
sho signal ansi ions. No using he highes densi y digi al lib a y (wi h name ex ension D i e0)
bu ins ead he second highes densi y lib a y (D i e1), wi h wide ansis o s, gi es signi ican ly
imp o ed adia ion ole ance. F om D i e0 o D i e1 ga e cells, he ou pu ansis o s ha e inc eased
(double) ga e wid h (W) and he e o e signi ican ly imp o ed adia ion ole ance. F om D i e1 o
D i e2 (and highe d i e) ga es, mul iple pa allel ou pu ansis o s a e used, o same size as used
in D i e1. D i e1 and D i e4 cells he e o e ha e e y simila adia ion ole ance cha ac e is ics.
Finally, i was de e mined ha i used cold (below
−10 ◦
C) and ne e (less han a ew days) powe ed
a oom empe a u e a e high TID exposu e, he obse ed de imen al annealing can be kep unde
con ol. The basic mechanism behind his beha io has now been unde s ood [
39
] and con i med. I is
caused by adia ion induced apped cha ges in ga e space s ha a ele a ed empe a u e and unde
speci ic biasing condi ions d i in o ac i e ga e egions. Ini ially he pixel chip ope a ion empe a u e
– 47 –
2025 JINST 20 P03024
Figu e 64. PMOS Ion d i e capabili y adia ion deg ada ion o sho channel (60 nm digi al) ansis o s o di e -
en wid h unde wo s case biasing condi ions (
𝑉DS =1.2
V,
𝑉GS =1.2
V) a
−15 ◦
C (le ) and ela ed de imen al
annealing ( igh ) a di e en empe a u es. Rep oduced wi h pe mission om [
41
]. ©CERN 2015. CC BY 3.0.
was es ima ed o be
−20 ◦
C, bu has wi h mo e de ailed he mal modeling o he pixel de ec o s been
seen o be up o
−10 ◦
C in ce ain loca ions. No signi ican di e ence in adia ion ole ance has been
seen be ween
−20 ◦
C and
−10 ◦
C ope a ion empe a u e.
Wi h hese design and ope a ion cons ain s (below
−10 ◦
C), digi al logic will a e 1 G ad s ill ha e
a
∼50
% speed deg ada ion, when i adia ed a high dose a es (1 G ad in 1 week). When i adia ed a
low dose a es he speed deg ada ion was ound o be signi ican ly mo e. Low dose a e e ec s ha e
been cha ac e ized in dedica ed long e m X- ay, cobal sou ce and K 85 sou ce i adia ions [
40
] wi h
an e ec i e speed educ ion o a ac o 2–3 o he used digi al lib a y, as shown in igu e 65. This is
aken in o accoun in he RD53 design low using a speci ic ex eme iming co ne case. Ini ially a
dedica ed adia ion co ne o he used digi al lib a ies was de eloped in RD53. I was hen ealized
ha using a e y low ol age co ne p o ided by he ound y (0.9 V, wo s case p ocess and
−40 ◦
C) in
p ac ice esul s in simila iming and ha e been used o iming closu e o inal RD53C designs.
Full scale RD53B chips ha e in low dose a e i adia ion es s [
49
] indica ed a p ojec ed adia ion
ole ance o he G ad le el as shown in igu e 66. This demons a es ha app op ia e ga e delay
adia ion models ha e been used in he ull chip design low, o assu e long e m i adia ion ole ance
(low dose a e e ec s). In eg a ed on-chip analog and digi al adia ion e ec s moni o ing (see sec ion 8)
allows his o be moni o ed du ing ope a ion and can be used o p edic i an inne pixel laye needs o
be eplaced. The cu en p edic ion is ha inal RD53C chips will be capable o aking 1–1.5 G ad o e
10 yea s o ope a ion in an app op ia ely cooled and ope a ed pixel de ec o . Pixel assemblies made o
senso s and chip ha e been exposed o 10
16
had ons/cm
2
and ha e, as expec ed, no been seen o be
a ec ed by NIEL (Non Ionizing Ene gy Loss), as i is gene ally he case o CMOS p ocesses. Final
p oduc ion chips will be p oduced in he same ab as he p o o ypes, as he e ha e been indica ions
o di e ences be ween abs o he same echnology node. Radia ion ole ance es s o p oduc ion
ba ch samples will be necessa y o assu e ha equi ed adia ion ole ance is main ained du ing he
wa e p oduc ion pe iod. P oduc ion ba ches wi h indica ions o educed adia ion ole ance can
– 48 –
2025 JINST 20 P03024
Figu e 65. Ga e delay deg ada ion o D i e0 and D i e4 ga es a High Dose Ra e (HDR), uppe le , and Low
Dose Ra e (LDR), uppe igh . Rela i e delay deg ada ion be ween Low dose a e and High dose a e a di e en
dose a es. D i e4 uses same ansis o wid h as D i e1, bu wi h mul iple pa allel ou pu ansis o s o highe
d i e capabili y. They he e o e ha e simila ela i e adia ion deg ada ion.
i needed be used o ou e pixel laye s (
∼100
M ad and majo i y o chips needed). I is planned
o make u he i adia ion es s o inal pixel chips o ex emely high le els (mul iple G ad) un il
hey show signs o ailing because o TID.
Tole ance o SEU and SET e ec s is he o he c i ical equi emen o a chip wi h complex digi al
logic. A RD53 chip is es ima ed o ha e
∼100
SEU upse s pe second in inne pixel laye s, based
on he measu ed SEU c oss-sec ion o used memo y elemen s. SETs can be assumed o be o he
same o de o magni ude. This makes i a majo challenge o assu e su icien ly eliable ope a ion
o housands o chips. Sys ema ic use o well known gene al TMR (T iple Modula Redundancy)
schemes, and ela ed speci ic ools [
44
], can esol e his, bu a an excessi e cos in e ms o a ea
and powe o e head ( ac o 3).
In pa icula in he la ge and dense pixel a ay logic i is no easible o i TMR p o ec ion.
C i ical pixel con igu a ion bi s ha e iplica ed la ches, wi hou au o-co ec ion eedback. Con inuous
pixel e-con igu a ion can be done a a a e o up o 10 imes pe second wi h he a ailable con ol
– 49 –
2025 JINST 20 P03024
Figu e 66. P ojec ed low dose a e limi o RD53 chip based on low dose a e i adia ion o D i e4 (and D i e1)
ga es. Ga e delays ha e been measu ed wi h low dose a e adia ion cha ac e iza ion o ing oscilla o es
ci cui s. A maximum ole able ga e delay inc ease o 200 % has he e been de ined as he limi , as his is he
e ec i e iming ma gin ob ained wi h he used ga e iming models.
link bandwid h. P o ec ion om SEUs and SETs wi h TMR in emaining pixel a ay logic can no
i in he highly cons ained a ea. This has wi h simula ions been es ima ed o cause ake o los
hi s below 0.01 % o he ac ual hi a e.
The Digi al Chip Bo om (DCB) con ains c i ical chip unc ions ha can no be allowed o be
upse by SEU/SET, as he chip may hen ge in o a dead-locked s a e, lose sys em synch oniza ion o ge
mis-con igu ed. C i ical unc ions (global con igu a ion, T igge able, s a e machines, bu e poin e s
and c i ical e en in o ma ion) ha e ull TMR. Howe e , hi da a in da a bu e s and p ocessing pipelines
a e no p o ec ed. This s a egy has esul ed in
∼25
% o egis e s in he DCB o ha e TMR p o ec ion.
Wi h such a pa ial p o ec ion scheme i is c i ical no o o e look c i ical memo y elemen s ha equi e
p o ec ion. This is a delica e ask equi ing ca e ul e i ica ion wi h SEU simula ions (see sec ion 11).
I can also be men ioned ha RD53 chips speci ically use e en ags, included in igge commands, o
p e en e en de-synch oniza ion o occu because o SEUs in local chip e en ID coun e s.
TMR o selec ed egis e s can be done in di e en ashions ha mus be ca e ully chosen based on
he cha ac e is ics o he design and how bes o in eg a e his in o he chip design low. The selec i e
TMR p o ec ion has been made a ga e le el, a e RTL logic syn hesis. Based on egis e names,
wi h a speci ic name ex ension, single Flip-Flops (FF) ha e been eplaced wi h iplica ed lip- lops
wi h Majo i y Vo ing (MV). T iplica ed clocks a e in oduced in he design o TMR p o ec ed FFs
in app op ia e clock domains (40 MHz, 64 MHz, 160 MHz, 640 MHz, 1.28 GHz). SET il e ing o
TMR FFs is ob ained wi h a ime skew be ween he iplica ed clocks such ha sho SET gli ches
will only be seen by a single TMR FF and hen il e ed by he TMR majo i y o e as indica ed in
igu e 67 [
47
]. This app oach does no equi e iplica ion o TMR o e s and combina o ial logic
as i p e en s SET gli ches o p opaga e o mul iple TMR nodes. T iplica ed clock skew was o he
RD53B chips se o 300 ps, based on SET gli ch wid h measu ed wi h a dedica ed es chip [
48
]. I
– 50 –

2025 JINST 20 P03024
Figu e 67. SEU/SET p o ec ion used o c i ical s o age nodes in digi al chip bo om. C i ical lip- lops a e
iplica ed o esol e SEUs. SETs in logic, MVs (Majo i y Vo e ) and clock d i e s a e ime il e ed by using
iplica ed clocks wi h cen alized clock skews (d 0, d 1, d 2). This scheme does no equi e iplica ion o MVs
and logic, gi ing signi ican a ea sa ings.
has been measu ed ha he used pa ial TMR p o ec ion wi h iplica ed skewed clocks has educe
he e ec i e SEU c oss sec ion by a ac o o 400. The iplica ed clock skewing has in inal RD53C
chips been inc eased o 400 ps o u he diminish he SEU and SET c oss-sec ion (see sec ion 10).
Quick and e icien p oduc ion es ing o he implemen ed TMR p o ec ion can be done by disabling
one by one he iplica ed clocks, and check ha he chip con inues o wo k co ec ly.
Ex ensi e SEU/SET es s ha e been made o he RD53B chips [
45
,
46
]. Occu ences o ela i ely
long eadou link d opou s, as shown in igu e 68, we e seen in ion beam es s. I was con i med in
dedica ed lase injec ion es s o be caused by sho SET gli ches in he biasing gene a ing ci cui , being
ex ended o mul i mic osecond long biasing shi s o he PLL. The cause was con i med wi h de ailed
ci cui simula ions wi h a dedica ed analog simula ion se up o SET/SEU sensi i i y analysis. Biasing
ci cui opology changes ha e been implemen ed, based on de ailed SET simula ions a ansis o le el,
o esol e his in inal p oduc ion chips. A c i ical issue wi h he chip e en eadou ge ing s uck was
also iden i ied and esol ed based on ex ensi e SEU e i ica ion simula ions (see sec ion 11).
The c i ical (and sensi i e) PLL has been implemen ed in ull cus om layou wi h iplica ed
coun e s. Du ing i s no mal ope a ion i uses a simple bang-bang phase de ec o , whe e occasional
SEUs and SETs in he phase de ec o can only in oduce e y small ji e ( ew ps).
Recen ion and p o on beam es s wi h he RD53C chip ha e con i med ha inal p oduc ion chips
ha e signi ican ly lowe SEU and SET sensi i i y. Link d opou s a e no obse ed any mo e. When
ac i ely p ocessing high hi and igge a es, he RD53C chip is seen o ha e a HEH (High Ene gy
Had on) c oss sec ion a ac o
∼30
be e han he RD53B. The e ec i e HEH c oss sec ion o e en
eadou ge ing s uck has ecen ly been measu ed o be lowe han
3×10−13
cm
−2
. In inne pixel
laye s his will co espond o a pixel chip unning o an a e age pe iod o
∼1
hou be o e ha ing
eadou issues. This is conside ed accep able o a small numbe o inne laye pixel chips in such
a hos ile adia ion en i onmen . Regula sys em le el as bu e clea commands can be issued a
a es as high as se e al Hz, wi hou signi ican sys em dead- ime, when ha ing a DAQ sys em ha
– 51 –
2025 JINST 20 P03024
Figu e 68. Measu ed SET occu ence o long link d opou o RD53B chip in an ion es beam. A sudden PLL
equency jump occu s a he ime o he SET and i akes 18 μs o he PLL con ol loop o eco e equency
and phase lock. On he uppe ace i can be no iced ha he se ial link ou pu ampli ude is also a ec ed by he
SET in he cen al biasing ci cui and eco e s much slowe han he PLL, as no pa o an ac i e compensa ion
con ol loop.
can handle his app op ia ely. Fu he sys em le el s udies a e ongoing o de e mine how he DAQ
and con ol sys ems o he expe imen s can handle his e icien ly.
An unexpec ed small numbe o Single E en La chups (SEL) we e obse ed in he digi al pa
o he RD53B chip a an inc eased supply ol age o 1.3 V in a dedica ed ion es a highes Linea
Ene gy Loss (LET) and 45
◦
incidence angle wi h an equi alen LET
e
o 88 MeV
×
cm
2
/mg. This
has no been seen be o e in he used 65 nm CMOS echnology and came as a su p ise as a digi al
lib a y wi h subs a e and well aps in each ga e has speci ically been used o a oid possible la chup
issues. I has been e i ied ha e en s wi h so high LET
e
will no occu in p ac ice in he HL-LHC
en i onmen (e.g silicon ecoils om nuclea eac ions). I has also been e i ied ha SEL is no seen
in he ion beam when he digi al logic is powe ed a i s nominal ol age o 1.2 V (i is known ha
SEL is e y ol age dependen a low powe supply ol ages). I such a la chup would excep ionally
occu in inal sys ems, i is no expec ed o cause pe manen chip damage in a se ially powe ed
sys em, d i en by a cons an and limi ed cu en .
10 Implemen a ion
RD53 chips a e implemen ed in a 65 nm CMOS echnology wi h he maximum allowed me al s ack
consis ing o 7 hin, 1 hick and 1 ul a- hick me al laye s, and an addi ional op edis ibu ion laye
also used o powe dis ibu ion whe e app op ia e. The gene al loo plan is as shown in igu e 8, and
consis s o he la ge pixel ma ix o 150 k
50 ×50 μm2
pixels and he Digi al Chip Bo om (DCB),
he Analog Chip Bo om (ACB) and he IO pad ame wi h SLDO powe egula o s.
The pixel a ay is assembled om
8×8
pixel co es including six een analog islands o
2×2
on -ends embedded in a sea o digi al logic as shown in igu e 69. Analog and digi al ci cui s a e
– 52 –
2025 JINST 20 P03024
implemen ed in sepa a e iple wells o assu e bes possible noise isola ion. Pixel co es ha e embedded
powe , analog and digi al signal ou ing o make pixel co e columns om abu men o pixel co es,
and om his build he comple e pixel a ay. Pixel co es ha e buil -in digi al signal bu e s and skew
compensa ion o ime c i ical signals (clock and calib a ion injec ion) o gua an ee a max ime skew
ac oss he a ay o 1 ns (
∼2
ns a e 1 G ad). Skew compensa ion is implemen ed in he pixel co es as
shown on he igh o igu e 69 wi h a con igu able delay be o e he local clock dis ibu ion ne wo k.
The con igu able skew compensa ion delay is d i en by he pixel co e add ess (de ined by loca ion) o
ge well aligned pixel clocks o di e en p ocess, empe a u e and ol age co ne s as show in igu e 70.
I can be no iced ha he skew compensa ion delay is e ec i ely adjus ed o each ou pixel co es.
Pixel co e logic has been syn hesized wi h app op ia e conse a i e cons ain s o build a unc ional
pixel co e column wi hou iming cons ain s iola ions. A iming model o he pixel co e has been
ex ac ed by he Cadence Libe y ool o assu e accu a e pixel a ay iming used o ull chip assembly
and e i ica ion. The pixel co e has also been ex ensi ely simula ed a analog le el o assu e he bes
possible e i ica ion o AFEs oge he wi h he digi al pixel logic (see sec ion 11).
Figu e 69. Pixel chip implemen a ion wi h physical hie a chy used o build he pixel a ay. The pixel a ay is
assembled om pixel co e columns made om pixel co es wi h
8×8
pixels. Clock skew compensa ion along
he pixel co e column is buil in o he pixel co es, wi h i s local delay de e mined by posi ion along he column.
Figu e 70. Time skew along pixel column o clock and pixel cha ge injec ion o di e en p ocess co ne s and
es ima ed 1G ad i adia ion, om ga e le el iming models.
Logic syn hesis, place & ou e and iming op imiza ion o he DCB, wi h p e-placed analog
blocks in he ACB, has been pe o med wi h he pixel co e iming model wi h dedica ed conse a i e
– 53 –
2025 JINST 20 P03024
p ocess, ol age and empe a u e co ne s (e.g. supply ol age speci ically se o 0.9 V ins ead o 1.2 V,
as men ioned in sec ion 9) o ge he equi ed TID adia ion ole ance. As pa o he design low,
iplica ion o c i ical FFs is pe o med a he end o logic syn hesis wi h dedica ed iplica ed clocks
wi h s ic iming cons ain s (and ime skew as men ioned in sec ion 9). Placemen is en o ced o
keep a minimum spacing be ween TMRed FFs o p e en co ela ed mul i-bi SEU upse s o dis u b
co ec unc ion o he chip. A his og am o inal TMR FF dis ance is shown in igu e 71, whe e
i can be seen o ha e complied o he minimum dis ance cons ain o 15
μm
. This dis ance has
by he HEP elec onics communi y been seen o be gi e good assu ance ha mul i bi lips will
be unlikely. Figu e 72 shows ha an a e age TMR clock skewing o 400 ps has been ob ained
in he inal RD53C chips (was 300 ps in RD53B chips). Fo a small numbe o FFs he e ec i e
local clock skew be ween he h ee TMR FFs a e jus below 200 ps ( ypical case p ocess) which
is conside ed accep able. I was a emp ed o ge he place and ou e ools o educe he ails o
he clock skew dis ibu ion bu con e gence was no ob ained a e se e al days o unning and
he ools e en ually c ashed.
Figu e 71. Dis ibu ions o dis ance be ween pai s o iplica ed TMR lip- lops in inal RD53C chip.
Powe dis ibu ion in such a la ge complex mixed signal chip is c i ical and has been e i ied
wi h dedica ed Vol us powe simula ions as shown in igu e 73. De ailed ga e le el simula ions a e
equi ed o d i e dynamic powe dis ibu ion e i ica ion bu he RD53 chip is so la ge and complex
ha he a ailable ools o his c ashed. Dynamic powe e i ica ion has he e o e been made as a
combina ion o a de ailed single co e column simula ion and ull chip e i ica ion using a simpli ied
co e column. This is seen o be compa ible wi h he obse ed RD53B g ound (and VDD) ol age
d op measu emen s as shown in igu e 59. All me al laye s ha e been used o ge he bes possible
powe dis ibu ion, so i is in p ac ice no possible o imp o e his. The ull sized pixel chips wi h his
passi e on-chip powe dis ibu ion ha e demons a ed ha hey mee all equi emen s.
The wi e-bonding pad- ame, wi h 100
μm
pi ch, is iden ical o all RD53B and RD53C gene a ion
chips, enabling he use o common es ing in as uc u e consis ing o single chip es ca ds and wa e
p obing ca ds. A la ge majo i y o he wi e-bonding pads a e used o supply powe o he chip and
ha e low induc ance connec ions o ex e nal decoupling capaci o s, as shown in igu e 74.
The inal RD53 chip implemen a ions con ain 660 M ansis o s, 56 M s anda d cells and 12 M
memo y elemen s. 2.1 M memo y elemen s a e used o implemen 700 k TMR p o ec ed bi s, o
which 85 % a e pixel con igu a ion bi s and 15 % a e used in he DCB. O e all o he comple e
design 7 % o logical bi s ha e TMR p o ec ion.
– 54 –
2025 JINST 20 P03024
he o e all yield has been seen o be as good as
∼90
% in 50 p e-p oduc ion wa e s as shown in
igu e 82. A b eakdown o ypical chip ejec s pe wa e , o di e en es s, is shown in igu e 83.
Ex ac ed pe o mance and calib a ion pa ame e s a e s o ed in app op ia e da abases o be used o
con igu a ion and c oss checking wi h pixel module and sys em es s. Indi idual chips a e aced
du ing dicing, handling and moun ing on pixel modules wi h a chip ID bu ned in E- uses du ing wa e
p obing. This chip ID can hough no be gua an eed o be eadable a e i adia ion (
∼100
M ad).
A comple e es and cha ac e iza ion o a wa e wi h 131 chips akes 8–16 hou s, gi ing a wa e
h oughpu o 1–2 wa e s pe day pe p obing s a ion. Wa e p obing acili ies ha e been se up in
ins i u es o each expe imen o es all p oduc ion chips wi hin a yea .
Figu e 80. Example o wa e es ing selec ing c i e ia o measu ed e e ence cu en (I e ) and i s uning. Le :
un uned e e ence cu en , Middle: uned e e ence cu en , Righ : I e uning se ings dis ibu ion. G een is
accep ance c i e ia o pixel module p oduc ion, yellow is accep ance o p o o ype pixel modules and ed is
chip ejec . Igno ed label used o indica e ha measu ed pa ame e no used o inal chip selec ion (so in his
case only based on uned I e , and no on un uned I e and uning se ings.
1.0 1.1 1.2 1.3 1.4 1.5
V
0
250
500
750
1000
1250
1500
1750
# Chips
Yield
g een: 6445 (98.4%)
yellow: 16 (0.2%)
ed: 84 (1.3%)
blue: 5 (0.1%)
Mean: 1.198
S d: 0.008
VDDD a e imming
1.18 o 1.22
0.0 o 1.1
1.3 o 1.5
1.1 o 1.18
1.22 o 1.3
0 2 4 6 8 10 12 14
T im Bi
0
200
400
600
800
1000
1200
1400
# Chips
Yield
g een: 6463 (98.7%)
yellow: 86 (1.3%)
ed: 0 (0.0%)
blue: 1 (0.0%)
Mean: 8.19
S d: 1.784
VDDD T im Bi
1.9 o 13.1
-0.5 o 1.9
13.1 o 16.0
Figu e 81. Wa e le el es ing o uned SLDO ou pu ol age (VDDD). Le : uned SLDO ou pu ol age.
Righ : used VDDD imming bi s o ob ain na ow VDDD ol age dis ibu ion among chips on 50 wa e s.
Pixel module es s wi h di e en bump-bonded senso s (plana , 3D,
50×50 μ
m
2
,
25×100 μ
m
2
) and
di e en module con igu a ions (single, dual, quad chips) ha e been pe o med by he ATLAS and CMS
pixel de ec o g oups in es beams and wi h adioac i e sou ces wi h ully sa is ac o y esul s. Pixel mod-
ule in eg a ion issues ela ed o bump-bonding yield and mic o c acks om hinned chip dicing, close o
he ac i e chip ci cui s, ha e been encoun e ed. These will be esol ed wi h imp o ed chip dicing p oce-
du es (e.g. lase g oo ing ollowed by saw dicing), imp o ed p ocedu es o bump bonding and imp o ed
pixel module p oduc ion and quali y assu ance p ocedu es (e.g. gluing wi h adia ion ha d glues).
– 61 –

2025 JINST 20 P03024
Figu e 82. RD53C-ATLAS wa e yield map o 50 wa e s.
Figu e 83. RD53B-CMS chip ejec s o 8 wa e s o di e en es s. To be no ed ha ailing chips a e o en
ejec ed by mul iple es s, so ypically only 10-20 chip ejec s pe wa e . Ce ain es ailu es also excludes o he
es s o be pe o med (e.g. powe supply sho ).
– 62 –
2025 JINST 20 P03024
A measu ed gamma ay spec um o an Am-241 sou ce is shown in igu e 84. Finally a clea
beam spo can be seen in igu e 85 om a igge ed p o on beam es oge he wi h a X- ay omog aphy
o a quad pixel module, based on de ec ed pixel hi s in he module i sel .
Figu e 84. Am-241 gamma sou ce es o RD53B-ATLAS pa ially bump-bonded single chip module. Le :
spec um measu ed wi h he high p ecision TOT op ion and h eshold o 1000 e. Righ : hi map o pa ially
bump-bonded module wi h Sin e 3D senso . Unconnec ed pixel bumps clea ly seen as low hi coun pixels
(blue) wi h a ew noise hi s.
Sys em in eg a ion es s wi h se ial powe ing and concu en eadou , as shown in igu e 5ha e
demons a ed ully sa is ac o y chip, module and sys em pe o mance o use in he pixel de ec o s
o he wo expe imen s. Ex ensi e pixel module and sys em es s will con inue o be made in he
coming yea in he wo expe imen s wi h RD53C p oduc ion chips.
13 Conclusions
The RD53 collabo a ion has o e he las 10 yea s success ully de eloped wo la ge complex mixed
signal hyb id pixel de ec o chips o use in he ATLAS and CMS HL-LHC upg ades. I has been a
majo challenge o assu e equi ed li e ime (TID) and eliabili y (SEU/SET) o such an unp eceden ed
hos ile adia ion en i onmen a ew cm om he in e ac ion poin s a he hea o he ATLAS and CMS
expe imen s. A no el se ial powe ing concep has been de eloped o he on-chip powe egula o
ha has been quali ied and e i ied a sys em le el o low noise use wi h up o 64 pixel chips in a
se ial powe chain, gi ing majo ma e ial budge educ ions in he pixel de ec o s. Flexible con ol
and eadou in e aces enable he pixel chips o be employed e icien ly ac oss pixel de ec o sys ems
wi h highly a ying hi and eadou a es. Final p oduc ion chip e sions ha e ecen ly been submi ed
and a e cu en ly unde ho ough e i ica ion and es ing a pixel module and sys em le el in he
wo expe imen s, so he p oduc ion o ens o housands o pixel modules can ge s a ed o hei
in eg a ion in o he upg aded ATLAS and CMS pixel de ec o s.
I has been a majo e o o a la ge numbe o collabo a o s (s uden s, pos -docs, physicis s and
chip design enginee s) ac oss 24 ins i u es o ge o his poin a e 10 yea s o ex ensi e R&D. Many
expec ed challenges and unexpec ed p oblems ha e g adually been esol ed by a collec i e e o , ha
cons an ly had o be adap ed o an e ol ing design eam wi h egula depa u es o expe ienced eam
– 63 –
2025 JINST 20 P03024
Figu e 85. RD53B-CMS quad pixel module es s. Uppe : igge ed p o on beam p o ile wi h la ge pixels
be ween chips clea ly isible. Lowe le : X- ay omog aphy wi h X- ay hi coun as egis e ed by quad chip
pixel module. Lowe igh : 2D noise map o same quad chip pixel module.
membe s. I has been an addi ional challenge o handle wo sligh ly di e en chip e sions. Fo u u e
pixel chips o inc eased pe o mance and complexi y wi h signi ican ly inc eased IC echnology cos s,
i is ecommended o de elop common chips o use e icien ly a ailable HEP (High Ene gy Physics)
chip design esou ces. The RD53 design eam has wo ked e y well ac oss he wo expe imen s. I
has also been highly bene icial o he wo pixel de ec o communi ies o ha e an open in o ma ion
low on chip, module and sys em issues and sha ing app op ia e solu ions.
Acknowledgmen s
We would like o hank and acknowledge ou colleagues in he ATLAS and CMS pixel p ojec s o
hei help, pa ience and ex ensi e wo k ge ing o inal p oduc ion chips. A la ge numbe o people
ha e been in ol ed in de ining app op ia e chip speci ica ions and make ex ensi e chip and sys em
es s wi h se ially powe ed pixel modules wi h di e en pixel senso s.
We would also like o hank he CERN mic o elec onics g oup o hei ex ensi e echnology
suppo and handling communica ions wi h IMEC and he ound y o chip p o o yping and p oduc ion,
as suppo ed by he EU Eu op ac ice chip design p og am.
– 64 –
2025 JINST 20 P03024
The solid and long e m suppo om pa icipa ing RD53 ins i u es has been c i ical o us
o each a success ul end o 10 yea s o challenging R&D o hese pa icula ly di icul de ec o
applica ions in an unp eceden ed ha sh adia ion en i onmen . Funding has been p o ided by he
ollowing agencies: CERN; MEYS CR (Czech Republic); CEA and CNRS/IN2P3 (F ance); HGF and
MPG (Ge many); GSRI, G eece; INFN, P oge o Dipa imen o di Eccellenza, Uni e si y o To ino
(I aly); NWO (Ne he lands); RCN (No way); MCIN/AEI and PCTI (Spain); Swiss Funding Agencies
(Swi ze land); STFC (Uni ed Kingdom); Depa men o Ene gy (U.S.A.).
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