A 0.5µm CMOS Random Access Analog Memo y Chip o
Te aOPS Speed Mul imedia Video P ocessing
*Rica do Ca mona1, Se ando Espejo1, Ra ael Domínguez-Cas o1, Ángel Rod íguez-
Vázquez1, Tamás Roska2, Tibo Kozek3, Leon O. Chua3
1
Ins i u o de Mic oelec ónica de Se illa-CNM-CSIC-Uni e sidad de Se illa.
Edi icio CICA, A da. Reina Me cedes s/n, 41012-Se illa, Spain.
Ph. No.: 34+ 954 239923, Fax: 34+ 954 231832 E-mail: ca [email p o ec ed]
2
MTA-SZTAKI, Analogic & Neu al Compu ing Labo a o y,
Compu e and Au oma ion Ins i u e o he Hunga ian Academy o Science,
Budapes , H-1111, Hunga y.
3
Elec onics Resea ch Labo a o y, Uni e si y o Cali o nia, Be keley
258M Co y Hall, Be keley, CA 94720, USA.
Submi ed o e ision o he IEEE T ansac ions on Mul imedia
Sep embe 7, 1998
ABSTRACT
Da a comp essing and coding and communica ions in objec o ien ed mul imedia applica-
ions like elep esence, compu e -aided medical diagnosis o elesu ge y equi e an eno mous
compu ing powe − in he o de o T illion Ope a ions pe Second (Te aOPS). Compa ed wi h
con en ional digi al echnology, Cellula Neu al/Nonlinea Ne wo k (CNN) based compu ing is
capable o ealizing hese Te aOPS- ange image p ocessing asks in a cos -e ec i e implemen-
a ion. To exploi he compu ing powe o he CNN Uni e sal Machine (CNN-UM), he CNN
Chipse a chi ec u e has been de eloped − a mixed-signal ha dwa e pla o m o CNN-based
image p ocessing. One o he non-s anda d componen s o he chipse is he cache memo y o
he analog a ay p ocesso , he Analog Random Access Memo y (ARAM). This pape epo s
an ARAM chip ha has been designed and ab ica ed in a 0.5µm CMOS echnology. This chip
consis s o a ully add essable a ay o analog memo y egis e s and has a packing
densi y o 637 analog-memo y-cells/mm2. Random and non-des uc i e access o he memo y
con en s is a ailable. Bo om-pla e sampling echniques ha e been employed o elimina e ha -
monic dis o ion in oduced by signal-dependen eed h ough. Signal coupling and in e ac ion
ha e been minimized by p ope layou measu es, including he use o p o ec ion ings and sep-
a a ed powe supplies o he analog and he digi al ci cui y. The p o o ype ea u es an equi a-
len esolu ion o up o 7 bi s −measu ed by compa ing he econs uc ed wa e o m wi h he
o iginal inpu signal. Measu ed access imes o w i ing / eading o/ om he memo y egis e s
a e 200ns and 800ns, espec i ely. I/O a es ia he 16-line wide I/O bus exceed 10Msamples/s.
S o age ime a oom empe a u e is in he 80 o 100ms ange, wi hou accu acy loss.
EDICS: 2-CIRC, 2-EXTN
F on page oo no es12
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N00014-98-1-0052
2. Resea ch o he au ho s om IMSE-CNM (CSIC) has been suppo ed by he spanish CICYT (P ojec
TIC96-1392-C0202 SIVA) and he EU (P ojec ESPRIT IV 27077-DICTAM).
32 256×
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 3
I. INTRODUCTION
Cellula Neu al Ne wo ks (CNNs) a e analog nonlinea dynamic p ocesso a ays in which
di ec in e connec ions among he basic p ocessing uni s a e es ic ed o a ini e local neighbo -
hood [1]. Thei po en ial o image p ocessing applica ions was ad anced sho ly a e hei
in en ion [2] and is based on he ac ha many image p ocessing asks can be ealized by means
o weigh ed local in e ac ions be ween neighbou ing pixels [1][3]. Because o hei inhe en ly
pa allel p ocessing a chi ec u e, CNNs achie e a high compu a ion speed in he ealiza ion o
hese asks. Besides, hei uni o mi y and local connec i i y make hem especially sui ed o
VLSI implemen a ion [4][5][6][7][8].
The CNN pa adigm p o ides he amewo k o he de ini ion o an algo i hmically p o-
g ammable analog a ay compu e wi h supe compu e powe on a chip: he CNN Uni e sal
Machine (CNN-UM) [9]. I s dual-compu ing p ope y enables he ealiza ion o highly complex
image p ocessing asks by means o an on-chip analogic − analog and logic − s o ed p og am,
and ende s i a highly compe i i e al e na i e o he con en ional digi al app oach o pa allel
image p ocessing [3]. Fo example, almos 104 Pen ium® a e equi ed o he Te aFLOPS a ay
compu e shipped by In el® in 1997 [10]. Whene e accu acy in he compu a ion is no a c i ical
issue, as i ac ually happens in ea ly- ision asks [11], CNN-UM analogic chips a e ad an a-
geous in e ms o powe consump ion and compu a ion speed as compa ed o hese digi al coun-
e pa s [12].
The wo king CNN-UM chips epo ed o da e, wi h up o [5], [6] and
[7] cells, espec i ely, con ain a much smalle numbe o pixels han p ac ical image
sizes. Fo ins ance, con en ional ele ision applica ions equi e pixels pe ame −
no including he necessa y scanning o e head in ol ed in any display sys em [13]. Al hough
la ge chips will be a ailable in he nea u u e − [8] − p ocessing o p ac ical size
images equi es he adop ion o sys em-le el solu ions o o e come echnology limi a ions on
he numbe o pa allel p ocessing cells [14]. Pa icula ly, mul iplexing he CNN-UM p ocesso s,
i.e. making hem ope a e on o a ac ion o he comple e inpu image a a ime, appea s some-
imes he only way o ope a ion.
One possible s a egy is using space-mul iplexed, o mul ichip, CNN ha dwa e [15]. In a
mul ichip CNN, la ge a ays a e buil by in e connec ing chips wi h a smalle numbe o cells.
Each module ope a es simul aneously on o a ac ion o he inpu image which is, in his way,
p ocessed in pa allel. One d awback o his app oach a e he andom luc ua ions o he p ocess
20 22×16 16×
48 48×
644 483×
64 64×
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 4
pa ame e s among he di e en p ocesso s. This may cause inco ec o inaccu a e ope a ion
and, hus, equi es he inco po a ion o di e en co ec ion s a egies; o ins ance, using uning
o co ec pa ame e de ia ions du ing he gene a ion o he analog weigh s [16]. Howe e , he
majo d awback o mul ichip CNNs is he e y la ge numbe o chip modules and, specially, o -
chip in e connec ions needed. Fo ins ance, a ound chips and connec ions a e
equi ed o p ocess a pixels ideo ame using he CNN module epo ed in
[17]. And a ound chips and connec ions a e needed using he las gene a ion
p ocesso epo ed in [8].
A di e en app oach o using small size CNN chips o la ge images is ime-mul iplexing.
By aking ad an age o he compu ing powe o he CNN-UM, a single chip can be used o p oc-
ess a comple e ideo ame by ope a ing on a ac ion o he image a a ime. A ame a e o
− adequa e o high quali y ideo applica ions [13] − ep esen s a da a low o
pixels pe second. Real- ime p ocessing o such a e demands p ocessing ime pe pixel.
Thus, by allowing o a 2-pixel wide o e lap be ween image subse s in each scan di ec ion −
equi ed o co ec p ocessing o he bo de pixels [18] −, a CNN chip should be capa-
ble o p ocess each subimage in abou ; and o a chip. Because he ime
cons an o CNN-UM chips is in he ange o [4][8] we can conclude ha he ime-mul i-
plexed app oach is easible and, hence, cons i u es a mo e cos -e ec i e solu ion han he mul-
ichip one.
The ime-mul iplexed app oach equi es he de ini ion and de elopmen o an app op ia e
ha dwa e pla o m o he CNN p ocesso : he CNN chipse [19]. I is designed o suppo high
speed da a ansmission and in e acing o he analogic p ocesso o he senso y de ices and he
digi al hos ci cui y. The Analog RAM (ARAM) is one o he non-s anda d pa s o his chipse .
I is a high-speed sho - e m memo y bu e ha ope a es as he cache memo y [20] o he CNN
p ocesso . A s aigh o wa d ealiza ion o he equi ed unc ionali y would be he use o a con-
en ional digi al RAM in e aced wi h A/D and D/A con e e s. Howe e , he esul ing I/O a es
be ween he memo y and he p ocesso would ende his solu ion imp ac ical. In o de o ealize
a di ec da a in e change be ween he memo y and he p ocesso , a oiding da a con e sion, he
implemen a ion o a uly analog RAM chip is p oposed. Fo ull compa ibili y wi h he digi al
hos en i onmen and educed ab ica ion cos , his ARAM should be designed using s anda d
CMOS.
The p oblem o on-chip analog signal s o age has been aced by di e en au ho s in con-
nec ion o qui e di e se applica ions. Pa icula ly, CMOS ealiza ions o scanning delay-lines
8E3 4.1E5
644 483×66×
75 3.8E4 64 64×
40Hz 12.3E6
81ns
32 32×
73.8µs 320µs6464×
1µs
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 5
o ideo p ocessing a e p esen ed in [21] and a high-speed SC sampling ci cui is epo ed in
[22] o cap u e analog wa e o ms om an a ay o senso y de ices. Howe e , no andom access
o non-des uc i e eading o he memo y con en s can be done. An ARAM o ea ly ision
applica ions was epo ed in [23]. Howe e , i s accu acy elays on misma ch compensa ion and
no swi ching e o educ ion s a egies a e adop ed. In his pape an imp o ed e sion o a well-
known Sample-and-Hold (S/H) ci cui is p oposed o implemen a ully add essable analog
memo y chip. I is ealized in a CMOS single-poly iple-me al echnology and allows
non-des uc i e eading and andom access o memo y loca ions wi h a cell densi y o
637 cells/mm2. I ea u es a ound 7 bi s equi alen esolu ion wi h w i ing/ eading access imes
o 200ns/800ns, espec i ely, and s o age ime a oom empe a u e in he 80 o 100ms ange.
Besides, i s powe consump ion is o only 73mW om a 3.3V powe supply − achie ed h ough
mul iplexing o he ac i e S/H ci cui y.
In he nex sec ion, a b ie e iew o ideo signal p ocessing wi h CNNs is gi en oge he
wi h he speci ica ions o he ARAM in he CNN chipse . The, Sec . III epo s he de ails o he
ARAM p o o ype chip a chi ec u e and ci cui design. Tes esul s a e displayed and discussed
in Sec . IV. And inally, a summa y o concluding ema ks is gi en.
II. VIDEO SIGNAL PROCESSING WITH CNNs
A. CNN based image p ocessing and ARAM chip speci ica ions
In he CNN Uni e sal Machine − which has been demons a ed o be uni e sal in he Tu -
ing sense [24] − p og ammable nonlinea analog dynamics a e combined wi h p og ammable
logic ope a ions and analog and logic dis ibu ed memo ies. Complex image p ocessing asks
a e desc ibed by an analogic p og am [25], consis ing o a sequence o analog and logic ope a-
ions. This analogic p og am has o be compiled in o a pla o m-dependen machine code o be
execu ed by a pa icula ha dwa e implemen a ion. Fig. 1 depic s a diag am o he CNN-UM
and i s p incipal building blocks: he basic p ocessing uni s (cells), and he Global Analogic P o-
g amming Uni (GAPU). The GAPU s o es he analogic p og am and con ols i s execu ion. Fo
his pu pose, i is di ided in o wo main unc ional blocks. Fi s , he s o age uni consis ing o
he Analog P og am Regis e (APR), he Logic P og am Regis e (LPR) and he Swi ch Con ig-
u a ion Regis e (SCR). They con ain he machine code ins uc ions o he analog and logic
ope a ions and he swi ch con igu a ion, espec i ely. Second, he Global Analogic Con ol Uni
(GACU) ha decodes hese ins uc ions in o a mic ocode ha is ansmi ed o he cells. Inside
0.5µm
32 256×
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 6
he basic cell, h ee pa s can be dis inguished which a e esponsible o signal p ocessing, s o -
age and con ol o he ope a ion − Fig. 1. Fo he implemen a ion o he p og ammable analog
dynamics, he CNN co e con ains he in eg a o and he limi e blocks. Synap ic ope a o s can
be conside ed as a pa o he analog p ocessing uni . A Local Logic Uni (LLU) ealizes p o-
g ammable logic ope a ions be ween s o ed bina y magni udes. Sho - e m s o age o in e me-
dia e signals is ealized by Local Analog and Logic Memo ies (LAMs and LLMs). Signal
ans e ence and ope a ion con ol is pe o med by he Local Communica ion and Con ol Uni
(LCCU). And, inally, da a exchange be ween he cell a ay and he ex e nal ci cui y is ealized
ia he Local Analog Ou pu Uni (LAOU).
In o de o exploi he compu ing powe o his a chi ec u e, The CNN chipse o Fig. 2
has been de eloped o in e ace he CNN-UM p ocesso o he senso s and he digi al en i on-
men . Da a ansmission is suppo ed by h ee di e en buses. A high-speed analog bus connec s
he p ocesso , he ARAM and he ideo signal sou ces. The wid h o his analog bus is de e -
mined by he I/O bus o he CNN-UM chip, o he wise i will limi he o al h oughpu o he
GAPU
Fig. 1: CNN Uni e sal Machine a chi ec u e, basic p ocessing cell and global analog-and-logic p og am-
ing uni .
CNN Uni e sal Machine
LAM
LLM LLU
CNN
co e
LCCU
LAOU
GAPU APR
LPR
SCR
GACU
p ocessing
s o age
con ol
con ol

A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 7
sys em. Digi al da a a e ansmi ed ia he digi al bus, which is in e aced o he analog bus
h ough A/D and D/A con e e s. In addi ion, he e is a digi al ins uc ion bus. The equi ed s o -
age capaci ies and local h oughpu alues ha e o be e alua ed o de e mine he speci ica ions
o he non-s anda d pa s, i. e. he CNN-UM and he ARAM.
Assume an inpu image composed o -pixels (Fig. 2). I has o be decomposed in o
-pixel subse s ha a e empo a ily s o ed one-by-one in he analog RAM chip o hei
p ocessing. Howe e , pixels in he bo de o his window will no be p ope ly p oc-
essed unless a ce ain o e lap be ween he image ac ions is allowed. The e o e, and
pixel o e laps in he e ical and he ho izon al di ec ion, espec i ely, a e conside ed. Taking
his in o accoun , a s aigh o wa d calcula ion shows ha ,
(1)
subimages a e needed o co e he whole image. Each o hese subimages has o be cap u ed,
p ocessed and downloaded, hus esul ing in o he ollowing o al p ocessing ime o he
inpu ame,
Fig. 2: Diag am o he CNN chipse a chi ec u e.
Analog RAM
1
Analog bus
Digi al bus
Ins uc ion bus
A/DD/A
DRAM
VRAM
µp ocesso
CCD Image
CNN-UC
MiNi
×MaNa
×MpNp
×
Bai Bao Bpi Bpo
MiNi
×
MaNa
×
MaNa
×
mono
kMimo
–()Nino
–()×
Mamo
–()Nano
–()×
-------------------------------------------------------=
Ti
MiNi
×
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 8
(2)
whe e , and a e he imes equi ed o acqui e, download and p ocess each subim-
age, espec i ely. Fo he o me wo imes, and assuming ha and a e he wid hs o
he inpu and ou pu buses o he ARAM, he ollowing is ob ained,
(3)
whe e and a e he imes equi ed o w i ing and eading, espec i ely, an analog egis e
o he ARAM chip.
Wi h ega ds o he p ocessing ime in (2) we ha e o ake in o accoun ha , in he
mo e gene al case, he p ocesso size is smalle han he ARAM size. Hence, he necessi y a ises
o ano he mul iplexa ion. Assume he size o he p ocesso is and ha each analogic
p og am con ain da a acquisi ion s eps, analog p ocessing s eps, logic p ocessing
ope a ions, and da a downloads. Thus, he ime needed o pe o m he analogic algo i hm
on each subse is gi en by,
(4)
whe e,
, (5)
and and a e he imes equi ed o he analog and he digi al ci cui y o he CNN-
UM o se le and comple e he logic ope a ion, espec i ely. These pa ame e s a e pa o he
iming specs o he CNN-UM chip. and in he exp ession abo e ep esen s I/O imes
which a e gi en by,
(6)
whe e and a e he wid hs o he inpu and ou pu buses o he CNN-UM, espec i ely,
and and a e he imes equi ed o upda ing and downloading analog da a om one cell
Ti
Mimo
–()Nino
–()×
Mamo
–()Nano
–()×
-------------------------------------------------------Tai Tap
+Tao
+()⋅=
Tai Tao Tap
Bai Bao
Tai
MaNa
×
Bai
---------------------τai
⋅=
Tao
MaNa
×
Bao
---------------------τao
⋅=
τai τao
Tap
MpNp
×
ninap nlp
nd
MaNa
×
Tap
Mamo
–()Nano
–()×
Mpmo
–()Npno
–()×
------------------------------------------------------- Tpp
⋅=
Tpp niTpi napTpap
+nlpTplp ndTpo
++=
Tpap Tplp
Tpi Tpo
Tpi
MpNp
×
Bpi
--------------------- τpi
⋅=
Tpo
MpNp
×
Bpo
--------------------- τpo
⋅=
Bpi Bpo
τpi τpo
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 9
o he CNN a ay − also de ined as empo al specs o he p ocessing chip.
Assume a ame a e o ames pe second. The ollowing mus be accomplished in
o de o p ocess he whole inpu image ( ) in eal- ime:
(7)
Thus, om he ma hema ics abo e, he ollowing design equa ion can be ob ained,
(8)
We ind con enien o illus a e his design equa ion using ypical alues. Fo ins ance,
conside a ame a e o 40 ames pe second, an inpu image o pixels, an analog
RAM bu e o egis e s and a CNN a ay o cells. Conside as well a 2-pixel
wide o e lap in bo h, e ical and ho izon al, scan di ec ions and 16-line wide I/O buses. Then,
o a ypical I/O ime o 500ns pe memo y cell, he CNN-UM chip should be capable o com-
ple e he analogic algo i hm o e each subimage in less han 26µs− well wi hin he
specs o CMOS CNN-UM chips [4][8]. The la ge he CNN p ocesso size he as e he sys em
is. Besides, pipelined a chi ec u es and some in e lea ing o he memo y blocks can be used o
a mo e elaxed cons ain on he p ocessing ime.
Le us now de i e he speci ica ions o he ARAM block. I mus exhibi he ollowing
ea u es o p ope usage wi hin he CNN chipse a chi ec u e,
•Non- ola ili y. The analog in o ma ion con ained in he memo y egis e s should be
main ained o a su icien ly long ime. In his case, and because o he high-speed o
he compu a ion, a s o age ime o 100-200ms should be enough. Being a cache mem-
o y, powe -o non- ola ili y is no necessa y.
•Resolu ion. Accu acy le els o a wide ange o ea ly- ision asks a e in he 0.8-1.5%
ange. I ep esen s an equi alen esolu ion o 6-7 bi s. Coope a i e phenomena
de i ed om he pa allel p ocessing na u e o CNNs, like hype acui y [26], allow o a
mode a e esolu ion equi emen .
•Random access. Some analogic algo i hms designed o he CNN Uni e sal Machine
[27] equi e epea ed eading and w i ing o a speci ic loca ion o he memo y. Thus,
andom access o any memo y egis e should be p o ided.
•Non-des uc i e eading. Fo he same eason, eading any memo y loca ion should no
a ec he con en s, because access o hen migh be equi ed se e al imes in an ana-
N
MiNi
×
Ti1
N
-------
≤
1
N
-------MaNaMimo
–()Nino
–()
Mamo
–()Nano
–()
-------------------------------------------------------------- τai
Bai
------- τao
Bao
--------+


Mimo
–()Nino
–()
Mpmo
–()Npno
–()
------------------------------------------------- Tpp
+≥
512 512×
32 256×32 32×
MpNp
×
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 10
logic p og am.
•High-speed. Na ow access imes o he memo y allow a as e ope a ion. Al hough di -
icul o achie e, access imes smalle han 100ns will be equi ed o ealize complex
image p ocessing asks in eal- ime.
•Inpu /Ou pu . On he one hand, a se ial analog inpu channel is needed o in e ace he
image acquisi ion de ices − CCD image , composi e- ideo signal sou ce, ... On he
o he , he communica ion wi h he CNN-UM p ocesso is accele a ed by he use o pa -
allel analog channels o wid h and − see Fig. 2.
Ob iously, he memo y cell should be he smalles possible o allow ob aining he la ge
possible memo y a ays wi hou impo an yield p oblems. Besides, compa ibili y wi h digi al
CMOS ol age le els is implici ly assumed o in eg a ion wi h a digi al en i onmen a he sys-
em le el ia he ins uc ion and digi al da a buses.
B. Video signal in e ace o he CNN chipse
A s anda d composi e- ideo signal has a limi ed bandwid h o 5MHz and mus , hence, be
sampled a a minimum a e o 10Msamples/s. The maximum ime in e al be ween consecu i e-
samples is hence 100ns. In addi ion, he composi e- ideo signal ca ies in o ma ion on he lumi-
nance and ch ominance o each pixel, and a synch oniza ion pulse gene a ed by he as e
scanning o he objec pic u e. Fig. 3 displays he en elope spec um o a NTSC coded signal
and he wa e o m o a scan line. Al hough NTSC is a colo encoding s anda d, i is also com-
monly used o e e o i s associa ed scanning s anda d 525/59.94. A simple implemen a ion o
a ideo-signal in e ace o he CNN chipse is po ayed in Fig. 4. I can be buil up by using o -
he-shel componen s. He e, he incoming ideo signal (NTSC coded in his case) is ed in o a
ideo decode chip. I is decomposed in o i s luminance (Y) and ch ominance (C) componen s
plus he eco e ed iming signals. By now, only he luminance componen will be o in e es as
we a e no conside ing colo in o ma ion p ocessing. A e some ampli ica ion and le el shi -
ing, i equi ed, he ARAM chip ake samples o he inpu ia he se ial inpu channel. Con ol
signals and memo y add ess codes a e gene a ed by some p og ammable logic de ice om he
synch oniza ion pulses ex ac ed om he aw inpu by he NTSC decode . Time equi emen s
o he ARAM in his ideo in e ace can be easily de i ed. Using a squa e pixel g id -- equal
ho izon al and e ical sample pi ch, each ame in he 525/59.94 scanning s anda d is composed
o pixels, his includes he equi ed blanking in e als. I means ha each line o he
image, con aining 780 pixels, will be ansmi ed in 64µs app oxima ely. Acquisi ion o his
Bpi Bpo
780 525×
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 17
a he end o he sampling phase. I is con olled by he signal ha alls sligh ly be o e .
In his way, he eed h ough e o is in oduced ia he bo om-pla e o , which is main-
ained a a cons an ol age by he opamp. Now, is independen o he inpu and, he e-
o e, i s de i a i es wi h espec o a e equal o ze o. Consequen ly, no ha monic dis o ion
due o clock eed h ough will be p esen a he ou pu . The s o ed ol age is only a ec ed by an
addi ional ol age o se . A small pedes al e o o magni ude
(18)
I he ini e DC gain and he pa asi ic capaci o a e accoun ed o , he ou pu ol age is an
a enua ed copy o he inpu and an o se e m appea s,
(19)
Fig. 10 shows he opamp schema ics, which has been ealized h ough a olded cascode
a chi ec u e o be e i he 3.3V powe supply ol age. Fo 7 bi s equi alen esolu ion o he S/
H c cui , and assuming ha a 16mV e o is allowed o each sample, he opamp ou pu swing
has o be la ge han 2V. O he opamp speci ica ions a e: o 20MHz − equi ed o ollow
he inpu du ing he acking phase; and Slew-Ra e (SR) o 8V/µs− equi ed o sample 4MHz
band limi ed signals wi h up o 2V ampli ude (peak- o-peak).
Le be he small-signal ansconduc ance o he ansis o s in he inpu di e en ial-
pai o he opamp, and he ail-cu en . A ela ion be ween he ansis o s aspec a io and
can be de i ed om he speci ica ions. Because and assuming
φ1
*φ1
Cmem
VREF
ε
Vi
ε
Cgds
Cmem Cgds
+
------------------------------–VREF VTVREF VSS
–()VSS
–+[
]
⋅=
Vo11
A0
------1Cp
Ck
------+


+1– Vi1
A0
------1Cp
Ck
------+


Vos
+≈
Fig. 9: Opamp schema ic.
IB
Vi+ Vi- VO
VB2
VB1
M1M2
M3
M4M5
M6
M7
M10
M9
M8
VBp
VBn
IB
IB
Table I: T ansis o sizes
M1−M224/1.2
M316/1.2
M4−M548/2.4
M6−M748/1.2
M8−M924/2.4
M10 24/0.6
GBW
gm1
IBIB
GBW GBW gm12πCL
()⁄=

A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 18
ope a ion wi hin sa u a ion egion in s ong in e sion, one ob ains,
(20)
whe e is he in insic ansconduc ance o he MOS ansis o . On he o he hand, he neces-
sa y ail-cu en is ixed by he slew- a e,
(21)
This cu en de e mines he app op ia e aspec a io o he inpu di e en ial-pai o a con-
s an o 20MHz. The olded-cascode ou pu s age is speci ied by he DC gain. By p o id-
ing a leas 60dB o he DC gain −− he e o in oduced by he pa asi ic
capaci ance is educed o 0.1%. As is now ixed, he ou pu s age has o be designed so as
o achie e he necessa y ou pu impedance. Final comp omises a e esol ed by phase ma gin
and ma ching conside a ions.
C. Leakage cu en s and s o age ime
Du ing he hold pe iod, se e al leakage cu en s a emp o discha ge he s o age capaci o ,
con ibu ing o deg ade he sampled ol age alue. In he i s place, he e e se-biased junc ion
o med by he n-di usion a ea, co esponding o he sou ce e minal o he pass ansis o and
he subs a e pumps ou o he uppe pla e o he capaci o a cu en ha can be app oxima ed
by he e e se-biased sa u a ion cu en o he pa asi ic diode. Ano he leakage is due o he sub-
h eshold d ain- o-sou ce cu en o he pass MOS ansis o . These e ec s add up esul ing in a
o al cu en in he ange o he pA. In his occasion, capaci o s a e implemen ed by a poly-o e -
di usion s uc u e lying on op o a weakly-doped n-well (Fig. 10). Then, he n-well/p-subs a e
junc ion is e e se-biased and he cu en ha lows ou o he bo om pla e o he capaci o co -
espond o he associa ed e e se-bias sa u a ion cu en . Since i is in he A ange, i limi s he
e ec o he uppe pla e leakage. S o ed ol age deg ada ion in ime du ing he hold pe iod is
now gi en by
(22)
whe e is he capaci ance pe uni a ea o he poly-o e -di usion s uc u e. In hese condi-
ions, a sel -discha ge a e, independen o he capaci o size, is de ined:
W
L
-----2πCLGBW()
2
2knIB
------------------------------------=
kn
IBSR CL
⋅=
GBW
A
0gm1Ro
=
gm1
d
dVc1
Cmem
-------------– d
dq-
⋅Isel
CaA
----------–≈=
Ca
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 19
, (23)
whe e is he cha ge o an elec on, and a e he di usion coe icien s o holes and
elec ons, and hei di usion lengh s and and a e he mino i y-ca ie concen-
a ions in each side o he junc ion. In his echnology is 50mV/s. Then, he ol age a he
capaci o decays linea ly in ime du ing he hold pe iod. A maximum s o age ime can be
de ined in e ms o he accu acy equi emen s. Fo an equi alen esolu ion o bi s and a ull
scale ange o he inpu signal gi en by , he maximum s o age ime ( ) is he pe iod in
which he di e ence be ween and he ini ially s o ed ol age does no exceed , ha
is 1/2 LSB. Tha is
(24)
which is in he 200ms ange o a 10mV e o . These igu es, howe e , mus be unde s ood only
as o ien a i e because o he s ong sensi i i y o he leakage cu en s o he ope a ing empe a-
u e. Also, incidence o ligh on he ci cui su ace can se iously deg ade he con en s o he
memo y because o he ligh induced gene a ion o an ex a amoun o ca ie s.
sel q
Ca
------ Dppn0
Lp
----------------Dnnp0
Ln
---------------+


=
qD
pDn
LpLnpn0np0
sel
N
A
s o
VcA2N1+
⁄
Fig. 10:Polysilicon o e n-di usion capaci o .
A’A
B
B’
AA’
B’
B
p-subs a e
n-well
n-di usion
polysilicon
me al-1
oxide
VC+
VC-
s o A
sel 2N1+
⋅
----------------------------=
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 20
D. ARAM chip loo plan
This CMOS ARAM chip is composed o an a ay o analog memo y cells. Each
one con ains a capaci o , a pass ansis o and some local logic o add ess decoding. The sys em
includes as well some digi al con ol ci cui y and an I/O in e ace consis ing in an analog MUX/
DEMUX and 16 ou pu bu e s. Fig. 11 shows a pic u e o he ARAM chip loo plan. The mem-
o y ma ix is a anged in o 32 S/H lines wi h 256 capaci o s each. Random access o any mem-
o y loca ion is a ailable wi h he help o wo bina y- o-one-ho add ess decode s. A code o 5
bi s ac i a es one ou o he 32 ow selec ion lines, by means o he ow add ess decode . Simi-
la ly, each one o he 256 columns is selec ed by an 8-bi code. Di e en access schedules can
be implemen ed by an adequa e p og amming o he add ess codes. In o de o a oid he selec-
ion o mo e han one capaci o pe ow a a ime, wha would se iously deg ade he ope a ion,
a global clock con ols he du y cycle o he access signals lea ing a unable gua d ime in e al
o add ess codes o change. Now, wi h espec o he I/O in e ace, he 32 da a lines o he a ay
a e mul iplexed ei he o he 16-line wide I/O bus o he se ial I/O channel. A digi al con ol sig-
nal se s he se ial o pa allel I/O mode. Row selec ion signals a e employed o scan he 32 da a
lines wi h ei he he I/O se ial channel o he 16-line wide I/O bus. Some es pads ha e been
added o cha ac e ize he ou pu bu e s o a be e analysis o he es esul s.
32 256×
bias s age
Fig. 11:Sys em a chi ec u e o he ARAM chip.
column add ess decode (8:256)
I/O mux/demux (32:1/16)
o
ou pu
ou pu
bu e s
Analog memo y cells a ay
pads
om
inpu
pads
(32 x 256)
ow decode (5:32)
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 21
Guidelines conce ning signal in e ac ion p e en ion in mixed-signal IC’s ha e been ol-
lowed in he de elopmen o he p o o ype. I is a well-known ac ha he in eg a ion o a sig-
ni ican amoun o digi al ci cui y along wi h analog signal p ocessing in he same subs a e can
po en ially deg ade sys em pe o mance. A conse a i e layou s yle, wi h an ex ensi e use o
g ounded gua d ings, educes signal coupling by opening al e na i e e u n pa hs o he cu en s
induced in o he subs a e [30]. This is ein o ced by he implemen a ion o sepa a ed powe sup-
ply and g ound connec ions o he analog and digi al ci cui y and gua d ings [31]. Digi al lines
swi ching a highe a es ha e been ou ed o e insensi i e a eas and c i ical c ossings ha e been
shielded wi h a g ounded me al in e media e laye . Also, analog bus lines a e made wide and
a e sepa a ed o a la ge dis ance han ecommended by echnology ules, in o de o educe
c oss- alk a highe equencies.
IV. EXPERIMENTAL RESULTS
The i s p o o ype o his ARAM chip has been in eg a ed in he Hewle -Packa d 0.5µm
CMOS p ocess o e ed by he MOSIS se ice. The 24 a ailable samples o he chip has been
es ed and p o ed o be unc ional. No majo disc epancies ha e been ound du ing he es o
he di e en samples. Fi s o all, a unc ional cha ac e iza ion es has been de eloped. Se e al
inpu sine wa es o di e en equencies ha e been sampled a di e en a es. Fig. 12 shows a
plo o he measu ed oo -mean-squa e e o du ing he econs uc ion o he inpu wa e o m. I
has been compu ed by aking he squa e oo o he a e age o he squa ed di e ence be ween
he inpu signal and he eco e ed wa e o m o e he samples o he inpu wa e:
Fig. 12:Measu ed RMS e o in he econs uc ed wa e o m
Chip sample No.
RMSE (mV)
100Hz @10Ks/s
1Kz @10Ks/s
1Kz @100Ks/s
10Kz @100Ks/s
2 4 6 8 10 12 14
0
10
20
30
40
50
60
115
N
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 22
(25)
I is impo an o men ion ha no co ec ion o he ou pu bu e o se o he eed h ough
induced pedes al e o has been made. Fig. 13 displays a econs uc ed iangula wa e sampled
a 10KHz and a eco e ed sine wa e sampled a 100KHz. The compu ed absolu e RMSE is in
he 13-25mV ange, which means a ela i e e o o 0.7-1.4% o a 1.8V ou pu swing.
A e ealing pic u e o he es esul s is ob ained by compu ing he FFT o he ou pu sig-
nal. In his case, a 10KHz sine wa e has been sampled a 250Ksamples/s. I has been ed o he
ARAM chip h ough he se ial inpu channel, he e o e, 8192 samples o he inpu wa e o m
Fig. 13:Reco e ed iangula and sine wa e o ms
0.5 1 1.5 2 2.5 x 10-3
0.5
1
1.5
2
2.5
3
Inpu Signal F eq. 100Hz
Sampling F eq. 10KHz
RMSE abs: 11.9mV
Ou pu swing 1.668V
Time (seconds)
Ou pu wa e o m ( ol s)
0.5 1 1.5 2 2.5 x 10-3
0.5
1
1.5
2
2.5
3
Time (seconds)
Ou pu wa e o m ( ol s)
el: 0.71%
Inpu Signal F eq. 1KHz
Sampling F eq. 100KHz
RMSE abs: 22.3mV
Ou pu swing 1.725V
el: 1.29%
RMSE 1
N
----VikVok
–()
2
k1=
N
∑
⋅=

A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 23
ha e been aken. Fig. 14 shows he spec um o he ou pu signal, di ec ly measu ed om he
ou pu o he chip wi hou elimina ing i ele an in o ma ion o il e ing o he digi ize ead-
ings. I means ha no only he s o ed ol age samples bu also he ol age peaks occu ing du -
ing add ess changes a e cap u ed. The magni ude o he single- one a 10KHz is nea ly 80dB
abo e he backg ound le el. The ollowing peak in magni ude, ha akes place a he sampling
a e, is app oxima ely 30dB below he sine wa e one. Fig. 15 displays he inpu and he ou pu
signals as -pixel images using a linea 256-le els g ayscale (8 bi s deep). Each pixel in
he image ep esen s he ol age a a memo y capaci o in he a ay. The absolu e alue o he
di e ence be ween he inpu and ou pu images is ep esen ed in he same g ayscale.
Besides, some eal images ha e been loaded o he chip a 200ns pe pixel and downloaded
a 800ns. Fig. 16 displays he inpu and ou pu pic u es oge he wi h a g ayscale ep esen a ion
o he absolu e di e ence be ween hem. The i s wo examples a e -pixel pic u es in
a 256-le el g ayscale. The las one is a colo pic u e. They ha e been p ocessed in
-pixel pieces because o es equipmen equi emen s. Some spa ial noise can be
de ec ed in he ou pu pic u e. I is pa ly due o image pa i ioning and, on he o he side, due o
an imp ope acking o he inpu a he beginning o each pixel g oup -- e ical lines a he 1s ,
129 h, 257 h and 385 h pixels. Because o he clocking scheme adop ed o a oid he selec ion o
mo e han one memo y egis e a a ime, he eedback loop o he opamp in he S/H s age is le
open o a ce ain pe iod. Consequen ly, he ol age o he ou pu node goes up o he powe sup-
ply ol age o down o he nega i e ail. In hese condi ions, he slew- a e o he opamp is insu -
icien o ca ch up wi h he inpu in he equi ed acquisi ion ime.
Fig. 14:Spec um o he ou pu sinewa e a 10KHz (no il e ing o he eadings)
0 1 2 3 4 5 x 105
-120
-100
-80
-60
-40
-20
0
F equency (Hz)
Magni ude (dB)
32 256×
512 512×
256 256×
32 128×
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 24
Finally, s o age ime has been measu ed o andomly selec ed cells o he a ay. Fig. 17
shows he di e ence be ween he ini ially s o ed ol age and he ins an alue h ough ime.
These da a ep esen 24 cells in he 24 di e en samples o he chip. S o ed ol age deg ada ion
exceeds he equi ed accu acy le els a e 80-100ms. Recu si e eading o he same memo y
spo does no ha e a no iceable in luence on he s o ed ol age.
Finally, Fig. 18 shows a pho og aph o he p o o ype ci cui and Table II p o ides a su ey
o da a ex ac ed om he es s esul s.
V. CONCLUSIONS
The only missing pa o he CNN chipse a chi ec u e has been implemen ed. A andom
access analog memo y chip has been designed and in eg a ed in a s anda d 0.5 µm CMOS sin-
gle-poly iple-me al echnology. Measu ed equi alen esolu ion is a ound 7 bi s. S o age ime
is la ge han 80ms. DC powe dissipa ion emains 73mW o a 3.3V powe supply. Access
imes o 200ns ha e been ob ained, while eading ime is 800ns. Highe sampling and ou pu
a es can be achie ed using he 16-line wide analog I/O bus. In u u e gene a ions o he CNN
Fig. 15:Inpu and ou pu images (256 g ay le els)
inpu
ou pu
abs(di e ence)
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 25
Fig. 16:Tes inpu and ou pu images
inpu
ou pu
abs(di )
A 0.5 µm CMOS Random Access Analog Memo y Chip o Te aOPS Speed Mul imedia Video P ocessing 26
inpu
ou pu
abs(di )
Figu e 16: (Con inued)