280 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998
A High-P ecision Cu en -Mode WTA-MAX Ci cui wi h Mul ichip Capabili y
Te esa Se ano-Go a edona and Be nab´
e Lina es-Ba anco
Abs ac —This pape p esen s a ci cui design echnique sui -
able o he ealiza ion o winne - ake-all (WTA), maximum
(MAX), loose - ake-all (LTA), and minimum (MIN) ci cui s. The
echnique p esen ed is based on cu en eplica ion and com-
pa ison. T adi ional echniques ely on he ma ching o an
N
ansis o s a ay, whe e
N
is he numbe o sys em inpu s. This
implies ha when
N
inc eases, as he size o he ci cui and
he dis ance be ween ansis o s will also inc ease, ansis o
ma ching deg ada ion and loss o p ecision in he o e all sys em
pe o mance will esul . Fu he mo e, when mul ichip sys ems
a e equi ed, he ansis o ma ching is e en wo se and pe o -
mance is d as ically deg aded. The echnique p esen ed in his
pape does no ely on he p ope ma ching o
N
ansis o s, bu
on he p ecise eplica ion and compa ison o cu en s. This can be
pe o med by cu en mi o s wi h a limi ed numbe o ou pu s.
Thus,
N
can inc ease wi hou deg ading he p ecision, e en i
he sys em is dis ibu ed among se e al chips. Also, he di e en
chips cons i u ing he sys em can be o di e en ound ies wi hou
deg ading he o e all sys em p ecision. Expe imen al esul s ha
a es hese ac s a e p esen ed.
Index Te ms— Analog ci cui s, analog compu a ion, cu en -
mode ci cui s, maximum ci cui s, ansis o misma ch, winne -
ake-all.
I. INTRODUCTION
WINNER-TAKE-ALL (o loose - ake-all) and MAX (o
MIN) ci cui s a e o en undamen al building blocks
in neu al and/o uzzy ha dwa e sys ems [3]–[5]. Gi en a se
o ex e nal inpu s , hei ope a ion
consis s in de e mining which inpu p esen s he la ges (o
smalles ) alue, o wha is his maximum (o minimum) alue,
espec i ely. I a winne - ake-all (WTA) o MAX ci cui is
a ailable, a loose - ake-all (LTA) o MIN ci cui is ob ained
by simply in e ing he inpu .1
Hence, his pape will only concen a e on WTA and MAX
ci cui s.
In li e a u e, he physical implemen a ion o hese sys ems
has been ackled h ough wo main app oaches: 1) sys ems o
complexi y: hei connec i i y inc eases quad a ically
wi h he numbe o inpu s [6]–[10] and 2) sys ems o
complexi y: hei connec i i y inc eases linea ly wi h he num-
be o inpu s [1], [2]. In a sys em o complexi y, as
shown in Fig. 1(a), he e is one cell pe inpu ; each cell has
an inhibi o y connec ion (black iangle) o he es o he
cells and an exci a o y connec ion (whi e iangle) o i sel .
The e o e, he sys em has connec ions. Each cell ecei es
an ex e nal inpu . The cell ha ecei es he maximum inpu
will u n all o he cells OFF and will emain ON. I he sys em
Manusc ip ecei ed Ma ch 4, 1996; e ised July 1, 1997.
The au ho s a e wi h he Na ional Mic oelec onics Cen e (CNM), Ed.
CICA, 41012 Se illa, Spain.
Publishe I em Iden i ie S 0018-9200(98)00728-8.
1Op ionally, a common o se e m may be added.
is a WTA ci cui , each cell has a bina y ou pu ha indica es
whe he he cell is ON o OFF. In a MAX ci cui , he winning
cell will copy i s inpu o a common ou pu . Unde some
ci cums ances2i is possible o con e he opology
o Fig. 1(a) in o an one, as shown in Fig. 1(b). In
hese cases, a global inhibi ion e m is compu ed. Each cell
con ibu es o his global inhibi ion, and each cell ecei es he
same global inhibi ion. No e ha now, each cell con ibu es
o inhibi i sel . Consequen ly, he exci a o y connec ion ha
each cell has o i sel mus be inc eased o compensa e o
his ac . Typical WTA ci cui s epo ed in li e a u e
[1], [2]3co espond o he opology shown in Fig. 1(c). In
such ci cui s he e a e also cells, each ecei ing an ex e nal
inpu . Each cell connec s o a common node, h ough which
a global p ope y ( o example, a cu en ) is sha ed be ween
all cells. The amoun o ha global p ope y aken by each cell
depends (nonlinea ly) on how much i s inpu de ia es om
an “a e age” o all inpu s. Usually his “a e age” is no an
exac linea a e age, bu is somehow nonlinea ly dependen on
all inpu s. The cell wi h he maximum inpu akes mos (o
all) o he common global p ope y, lea ing he es wi h li le
o no hing. Due o he way his global p ope y is sha ed and
how he “a e age” is compu ed, he ope a ion o hese ci cui s
elies on he ma ching o ansis o h eshold ol ages o an
a ay o ansis o s [1] and/o o he ansis o pa ame e s. The
numbe o ansis o s in he a ay equals, a leas , he numbe
o inpu s o he sys em. I he WTA o MAX ci cui has such
a la ge numbe o inpu s so ha i mus be dis ibu ed among
di e en chips, he ma ching o h eshold ol ages (and/o
o he ansis o pa ame e s) will deg ade signi ican ly, and he
o e all sys em will lose p ecision in i s ope a ion.
This pape p esen s an complexi y ci cui echnique
[which can be ep esen ed by he opology in Fig. 1(b)] o
implemen ing ei he WTA and/o MAX ci cui s, based on
cu en -mode p inciples. The esul ing ci cui does no ely
on he ma ching o an -size ansis o a ay, bu on p ecise
local cu en eplica ion and compa ison. The ci cui can be
dis ibu ed among se e al chips, as is some imes demanded
by neu al and/o uzzy sys ems [11], while no deg ading i s
p ecision, as shown in he sec ion on expe imen al esul s.
II. CURRENT-MODE IMPLEMENTATION
OF WTA-MAX OPERATION
A ma hema ical model ha ealizes he WTA-MAX ope a-
ion and which is sui able o an cu en -mode-based
ci cui implemen a ion is p esen ed as ollows. Conside a
sys em o cells, such ha each cell p oduces an ou pu
2I he inhibi ion ha goes om cell
i
o cell
j
does no depend on
j
.
3The ci cui in [2] p ocesses ol age inpu signals, while he ci cui in [1]
and in his pape p ocesses cu en inpu signals.
0018–9200/98$10.00 1998 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 281
(a) (b) (c)
Fig. 1. WTA opologies. (a) WTA o
O
(
N
2
)
complexi y, (b) ans o ma ion o
O
(
N
)
complexi y, and (c) ypical opology o
O
(
N
)
WTA ha dwa e
implemen a ion. Black iangles ep esen inhibi o y connec ions, whi e iangles exci a o y connec ions, and shaded ci cles a e gene ally nonlinea
ime-dependen p ocessing elemen s whose ou pu s become (a e a ansien ) ei he “0” o “1.”
cu en wi h is he
s ep unc ion, is he ex e nal inpu o he h cell, and
(1)
Fig. 2 g aphically ep esen s unc ions
and . Thei in e sec ion p o ides he solu ion
o (1). I , (1) has a unique equilib ium poin
. Fu he mo e, i , he alue o a he
equilib ium poin is and he cell ha d i es
a nonze o ou pu is he winne . I each inpu is
changed o , whe e is an uppe bound o all inpu ,
, an LTA and/o MIN ci cui esul s. Fig. 3(a)
shows a cu en -mode ci cui ha implemen s he ope a ion o
one cell o he case . I consis s o a wo-ou pu
cu en mi o , a digi al in e e , and a MOS ansis o . Each
cell ecei es wo inpu cu en s, and , and deli e s one
ou pu cu en . The in e e ac s as a cu en compa a o .
I , he in e e ou pu is low, he MOS ansis o
is OFF, and is ze o. I , he in e e ou pu
is high, he MOS ansis o is ON, and . Fig. 3(b)
depic s he ans e cu e o his uni cell. Fig. 3(c) and (d)
shows he de ailed schema ic o he ab ica ed cells, one in he
double-poly MIETEC 2.4- m echnology and he o he in he
single-poly ES2 1.0- m echnology, espec i ely. Fig. 4 shows
he comple e WTA o MAX ci cui . I consis s o uni cells
and an addi ional -ou pu cu en mi o . The unc ion o
he -ou pu cu en mi o is o deli e he sum o cu en s
o each o he uni cells. Replica ion o cu en
mus be e y p ecise. I he numbe o uni cells is
oo la ge, o i he ci cui has o be dis ibu ed among se e al
chips, high p ecision in eplica ion canno be gua an eed by
a single cu en mi o wi h ou pu s. In his case, eplica ion
o cu en mus ely on se e al mi o s wi h a smalle
numbe o ou pu s bu wi h gua an eed p ecise eplica ion.
Fig. 5 shows an a angemen o dis ibu e he ci cui o Fig. 4
Fig. 2. G aphic ep esen a ion o he solu ion o (1).
among se e al chips. The ac ha cu en can be eplica ed
many imes wi hou elying on he ma ching o a la ge a ay
o ansis o s is he main ad an age o his WTA and MAX (o
LTA and MIN) ci cui echnique o e o he implemen a ions.
III. SYSTEM STABILITY ANALYSIS
Le us assume ha he dynamics o each cell [see Fig. 3(a)]
can be modeled by he ollowing i s -o de nonlinea di e -
en ial equa ion:
(2)
whe e is he o al capaci ance a ailable a node
is he o al conduc ance a his node, and is he in e e
282 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998
(a) (b)
(c) (d)
Fig. 3. WTA uni cell: (a) simpli ied schema ic, (b) ans e cu e, (c) ci cui
diag am o cell ab ica ed in he MIETEC 2.4-

m echnology, and (d) ci cui
diag am o cell ab ica ed in he ES2 1.0-

m echnology.
Fig. 4. Diag am o he WTA ci cui .
ip ol age. Le us also assume ha he ou pu cu en o a
cell is gi en by
(3)
whe e is a con inuous and di e en iable app oxima ion
o he s ep unc ion. Fo example, we can de ine as he
sigmoidal unc ion whe e is posi i e
and nonze o bu close o ze o. Now conside (2) o wo nodes,
and . Le be he node ha e en ually should become he
winne . I we sub ac (2) o he wo nodes and , hen
(4)
Fig. 5. S a egy o assemble se e al chips.
Equa ion (4) has he ollowing solu ion:
(5)
A e a ew ime cons an s , he di e ence be ween he
wo node ol ages will emain cons an and equal o hei
di e ence a he equilib ium poin . The e o e, i we can ob ain
he exp ession o , applying (5) would ob ain
o he es o he nodes.
Conside now (2) o node , and subs i u e (3) in o i
(6)
Since is gi en by (5), a e a ew ime cons an s (6)
becomes
(7)
This i s -o de di e en ial equa ion has s able equilib ium
poin s i . De i ing (7) wi h
espec o esul s in
(8)
Since , and a e always posi i e, (8) is always
nega i e o all possible alues o (including i s unique
equilib ium poin ). Consequen ly, (7) ep esen s he dynamics
o a s able sys em.4This discussion assumes ha he -ou pu
cu en mi o p esen s no delay. This is no e y ealis ic,
howe e i can be shown [12] ha he ci cui is s ill s able
4The s abili y p oo gi en in [20] o his sys em is no co ec because
i implici ly assumes symme ic in e connec ion weigh s be ween he cells,
which is no ue.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 283
when assuming he -ou pu cu en mi o p esen s a delay
modeled by i s -o de dynamics.
Pe o ming elec ical simula ions o he ci cui in Fig. 4
e eals ha he p e ious s abili y analysis is a good app ox-
ima ion as long as he equilib ium poin does no lie in he
ansi ion egion o any o he sigmoidal unc ions .
This can only be gua an eed i and he wo la ges
inpu s and a e su icien ly di e en . I o (wi h
) i wo o mo e inpu s a e maximum and e y
simila , he equilib ium poin o he sys em (see Fig. 2) will
be in he ansi ion egion o some sigmoids . In hese
cases, ansis o pa asi ic elemen s ha ha e been neglec ed
in he analysis o Sec ion IV may ende uns able beha -
io . Consequen ly, some kind o compensa ion is necessa y.
Unde uns able condi ions he sys em exhibi s he ollowing
cha ac e is ics (obse ed h ough elec ical simula ions wi h
HSPICE).
a) Only he cells whose sigmoid unc ions mus be
in hei ansi ion egion a he equilib ium poin a e
uns able. The es o he cells beha e as i he sys em
had eached i s equilib ium poin .
b) The uns able cells p esen oscilla ions (p esence o com-
plex conjuga e poles).
c) In he case o and wi h wo o mo e equal
maximum inpu s, he s eady-s a e oscilla ing wa e o ms
a hese cells become he same, ega dless o hei ini ial
condi ions.
This las obse a ion sugges s ha a s abili y analysis could
be pe o med by simply conside ing one cell in he sys em,
which ep esen s he pa allel connec ion o all uns able cells,
as shown in Fig. 6(a). On he o he hand, since he uns able
cells ha e he equilib ium poin in he ansi ion egion o hei
sigmoid , we can linea ize hese sigmoids o he s abili y
analysis. The e o e, le us conside he small signal equi alen
ci cui shown in Fig. 6(b), whe e he ci cui y comp ised by
dashed lines ep esen s he pa allel o all cells wi h equal
and maximum inpu . The es o he ci cui y models he -
ou pu cu en mi o (o se o cu en mi o s) esponsible
o dis ibu ing he global cu en among he cells. The
minimum se o dynamic elemen s needed o he sys em o
p esen uns able oscilla ing beha io a e pa asi ic capaci o s
, and (obse ed h ough elec ical simula ion).
Pe o ming small signal analysis on he ci cui in Fig. 6(b),
i can be shown ha he s abili y condi ion o his ci cui is
app oxima ely [12]–[13]
(9)
whe e is he numbe o cells wi h equal and maximum
inpu . This condi ion is no easy o sa is y since mus be
la ge o p ope ope a ion, may become la ge, and i is no
i ial o make he igh hand side o (9) e y la ge. S abili y
compensa ion can be achie ed by in oducing capaci o ,as
shown in Fig. 6(c). By small signal analysis o his ci cui , i
can be shown ha he s abili y condi ion o his ci cui is [12]
(10)
(a) (b)
(c)
Fig. 6. (a) Pa allel connec ion o uns able cells, (b) uncompensa ed small
signal equi alen ci cui , and (c) compensa ed small signal equi alen ci cui .
No e ha now he s abili y condi ion does no depend on
gain and is easie o ul ill. Howe e , now capaci o
deg ades he se ling speed o he sys em. Capaci o ac s
as a Mille capaci ance. Since he dc gain om node o
node is app oxima ely (i.e., he nega i e o he slope
o ), he e will be an e ec i e Mille capaci ance o alue
in pa allel wi h he o iginal capaci o . I he
sigmoid is no in i s ansi ion egion, , bu i he sigmoid
is in i s ansi ion egion, can be e y la ge. The e o e, o
compensa ed cells, (7) mus be changed o
(11)
I he winning cell is in i s ansi ion egion,
and a la ge capaci ance is p esen a node .
O he wise, and he e ec i e capaci ance
is only .
IV. EXPERIMENTAL RESULTS
A WTA-MAX sys em wi h compe ing cells
has been designed and ab ica ed in wo di e en CMOS
echnologies. The i s p o o ype has been in eg a ed in a
double-me al single-poly 1.0- m CMOS echnology (ES2),
and he o he in a double-me al double-poly 2.4- m CMOS
p ocess (MIETEC). Bo h echnologies we e a ailable h ough
he Eu opean silicon ound y se ice, EUROCHIP. Ci cui
schema ics and ansis o sizes o he uni cells a e shown
in Fig. 3(c) and (d) o he MIETEC 2.4- m and ES2 1.0- m
CMOS p ocesses, espec i ely. Sizes o he PMOS cu en
mi o ing ansis o s we e 175 m 4 m and 151 m 2.5
m o he MIETEC and ES2 p o o ypes, espec i ely.
I he ci cui is going o be used as a MAX ci cui , all cu en
mi o s mus p o ide good eplica ion p ecision. They need
o ha e small sys ema ic e o s and small andom de ia ions
284 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998
TABLE I
CURRENT-MODE WTA PRECISION MEASUREMENTS
[14], so ha he esul ing alue o cu en esembles he
maximum among all inpu s as close as possible. Howe e , i
he ci cui is going o be used as a WTA ci cui , equi emen s
a e no ha se e e. I inside one single chip, a WTA pe -
o ms he same e en i he cu en mi o s ha e app eciable
sys ema ic e o s. Since sys ema ic e o s a e common wi h
espec o all inpu s, he sys em can s ill de e mine which
inpu is maximum. On he o he hand, andom misma ch
e o s in he cu en mi o s mus be kep small because hese
e o s change andomly om one inpu o ano he . Reducing
andom e o s implies using la ge ansis o sizes. Reducing
sys ema ic e o s implies using mo e elabo a e cu en mi o
opologies ha ei he educe hei ou pu conduc ance (using
cascode [15], egula ed cascode [16], o gain-boos ing [17]
echniques), dec ease hei inpu impedance [18], o bo h [19].
The applica ion we had in mind when we de eloped his ci cui
was a WTA o a mul ichip eal ime clus e ing sys em [11].
Consequen ly, i was no c i ical ha he inal alue o be an
exac eplica o he maximum o he inpu s. The e o e, we used
a simple h ee- ansis o cu en mi o (wi hou any ou pu
conduc ance o inpu impedance dec easing echnique) o
he wo-ou pu NMOS cu en mi o o each cell. Howe e ,
we used ac i e inpu cu en mi o s [18] o he -ou pu
PMOS cu en mi o and o he ex a NMOS assembling
cu en mi o (see Fig. 5). These cu en mi o s assu e ixed
ol ages a hei inpu nodes. This was necessa y because i
he sys em is dis ibu ed among se e al chips, he p esence
o he assembling cu en mi o would b eak he symme y
be ween some o he inpu s, making sys ema ic e o s a ec
hese inpu s di e en ly. The ollowing p esen s p ope sys em
ope a ion o a WTA ci cui in one single chip, in wo chips
o he same echnology, and in wo chips each o a di e en
echnology. As will be shown, he dc beha io o he sys em
is no deg aded when he ope a ion is dis ibu ed among
se e al chips. In he emainde o his sec ion we will de ail
expe imen al measu emen s ela ed o he p ecision o a WTA
and i s speed esponse.
A. Ope a ion P ecision
The dc ans e cu es o he sys em ha e been measu ed
o di e en inpu cu en le els and o di e en sys em
con igu a ions. Fig. 7 shows 30 ans e cu es when he
compe ing cells a e inside he same chip. Each cu e is
ob ained by andomly selec ing a pai o inpu cells and
applying a cons an inpu cu en o he i s , and
Fig. 7. T ans e cu es o he WTA implemen ed in a ES2 1.0-

m chip o
an inpu cu en le el o 100

A.
sweeping he inpu cu en o he second om 0.9
o 1.1 . The igu e ep esen s he wo in e e ou pu
ol ages and e sus he cu en . Fo each pai o
cells and , we measu ed he alue o a he poin whe e
. Le us call his alue . Thi y cu es we e
measu ed o each alue o , esul ing in 30 alues o .
The di e ence be ween he mean o hese 30 alues and
is a measu e o he sys ema ic e o o . Le us call i .
The a iance o he 30 alues ep esen s he andom e o
o . Le us call i . In he case o Fig. 7, co esponding
o a WTA inside one single chip ab ica ed in he ES2 1.0-
m CMOS echnology wi h A, we measu ed a
andom de ia ion o % and a sys ema ic e o
o %.
Table I con ains he measu ed o al e o (de ined as
) o h ee decades o change in . The able shows
esul s o he cases o WTA’s inside one chip, assembled
using wo chips o he same echnology, and assembled wi h
wo chips o di e en echnologies. No e ha he p ecision
deg ada ion is e y small when he sys em is dis ibu ed among
wo chips, ega dless o whe he he chips a e o he same ech-
nology o no . This is he main ad an age o his WTA-MAX
ci cui wi h espec o o he s epo ed in li e a u e [1], [2].
B. Ope a ion Speed
Delay measu emen s we e pe o med as ollows. Only wo
inpu signals we e made nonze o. Le us call hem and .
Cu en was made cons an and equal o , while cu en

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998 285
TABLE II
MEASURED DELAY TIMES FOR ONE-CHIP WTA’s
Fig. 8. T ans e cu es when wo ES2 1.0-

m chips a e assembled and o
an inpu cu en le el o 10

A.
changed in a pulse be ween alues and
, as shown in Fig. 8(a). The pulse s a s a
ime and ends a ime . Wa e o ms and ha e
he shape depic ed in Fig. 8(b). Fou di e en delay imes
we e measu ed. Fo he sys em esponse caused by a ising
edge in , ime is he delay be ween ime and he
ins an a which ol age c osses he 50% alue o i s
ange. Delay is he same o ou pu ol age . Fo he
sys em esponse caused by a alling edge in , ime is
he delay be ween ime and he ins an a which ol age
c osses he 50% alue o i s ange. Delay is he same
o ou pu ol age . Measu emen s we e pe o med o
alues o 10 A, 100 A, and 500 A, and o equal
o 0.2 and . Table II shows he measu ed delay imes
o hose cases whe e he sys em is inside one single chip.
Table III shows he delay imes measu ed when a WTA is
assembled using wo chips o he ES2 1.0- m p ocess. No e
ha , in gene al, speed is deg aded o a wo-chip WTA. When
he sys em is scaled up (inc easing he numbe o inpu s and
chips) i s speed will be u he dec eased. Howe e , as long
as cu en le els a e main ained, i s p ecision is p ese ed.
No e ha when inc easing he numbe o inpu s, he cu en
le els can be main ained, because in he s eady s a e ( o one
single winne ) he e is only one wo-ou pu NMOS mi o ON
TABLE III
MEASURED DELAY TIMES FOR A TWO-CHIP WTA
and he PMOS mi o (s) d i e i s co esponding inpu cu en .
On he o he hand, o s abili y, (10) has o be sa is ied: by
inc easing he numbe o chips, capaci ance will inc ease;
howe e i ins ead o (10) he ollowing condi ion is imposed:
(12)
he sys em will emain s able no ma e how la ge is.
V. CONCLUSION
A WTA-MAX ci cui design echnique based on cu en -
mode signal p ocessing has been p oposed. The p ecision o
he ci cui elies on he p ope eplica ion and compa ison o
cu en s. This main ains good p ecision o ci cui s wi h a la ge
numbe o inpu s and when he ci cui is dis ibu ed among
se e al chips. S abili y analysis o he p oposed ci cui has
been add essed and s abili y condi ions de i ed. A s abili y
compensa ion scheme has been p oposed. Two p o o ypes, o
wo di e en echnologies, ha e been designed, ab ica ed, and
es ed. P ope pe o mance has been expe imen ally e i ied
o bo h p o o ypes, as well as o ci cui s assembled wi h
di e en chips, e en i each chip is o a di e en echnology.
The pe o mance o his WTA-MAX ci cui as compa ed o
p e ious implemen a ions [1], [2] is simila o bo h p ecision
and speed. Ac ually, o speed pe o mance, wo s esul s
would be expec ed wi h he p oposed ci cui since i needs
s abili y compensa ion. The ad an age o he p esen ci cui is
ha i does no loose p ecision when used in mul ichip sys ems.
In o de o achie e his wi h p e ious implemen a ions [1],
286 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 2, FEBRUARY 1998
[2], some on-chip calib a ion schemes would be needed o
compensa e o in e chip sys ema ic ansis o misma ch e o s.
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