Current-mode piecewise-linear function generators

Current-Mode Piecewise-Linear Function Generators Manuel Delgado-Restituto, Joaquin Ceballos-Chceres, and Angel Rodriguez-Vhzquez Centro Nacional de Microelectr6nica (CNM) Ed. CICA, Avda. Reina Mercedes s/n 41012 - Seville, SPAIN. Abstract - We present a systematic design technique for current-mode piecewise-linear (PWL) function generators. It uses two building blocks: a high-reso- lution current rectifier, and a programmable current amplifier. We show how to arrange these blocks to obtain basic non-linearities from which generic characteristics are built through aggregations. Measurements from a l.Op.m CMOS prototype chip show lOpA resolution in the rectification operation and 0.6% non-linearity errors in the programmable scaling operation for 2p.A input current range. 1.Introduction Function generators realize parametrizable nonlinear functions for given input signal range [1]-[3]. The parameterization may be determined by component ratios (non-programmable generators); or through external control signals and electrically-ad- justable circuits (programmable generators). Operators 1 I I Interconnec- Approximation tion Law Techniques I I Circuit Problem FIGURE 1. Hierarchical decomposition for the synthesis of function generators. II.Piecewise Linear Representations -- - Regardless of the programmability issue, the design of electronic function generators encompasses several subproblems (shown conceptually in Fig. 1): . Realization of nonlinear operators though the interconnection of primitive components. Realization of elementaryfunctions as the interconnection of circuit blocks which synthesize nonlinear operators. of the target as a combination Of elementary functions and its realization as the interconnection of the circuit blocks associated to these functions. A number of reported solutions to these problems employ piecewise-linear (PWL) approximant functions [4]. Their main advantage is simplicity of representation, which eases the calculation of the adjustment parameters. PWL functions are also easily realized at a circuit level. In fact, diverse solution have been proposed parting from different primitive components and assuming distinct physical represen- This paper presents a methodology for PWL approximation of arbitrary unidimensional functions (including those with finite jump discontinuities) us- Many of the circuit schemes proposed for the implementation of PWL function generators are based on the concept of extension operator presented in PI. Let us consider that the function y =f(x) is defined inside a real interval [&,, &+,] and described by a collection of data measured at the knots of a given The basic idea behind the concept of an extension operator is to build the approximate function, g(x), following an iterative procedure. At each iteration, the procedure from a previous approximation for a off(x) , and then adds new terms to fit the data associated with the adjacent subintervals. Generally, some pieces are adjusted to the left and others to the right, to yield, A = {60, a,, %,,..,jM sN+, 1. 1=1 I = -N where, + tations for the electrical variables [5]-[ 101. A g(X) = WU+(X-@ GW(X-~).Y~~(X-~) A-g (x) = wu- (x - 6) 3 w (x-6) sgn (6-x) (2) ing current mode techniques. Section 11 discusses some PWL representation techniques, and present the 0 g (x) = ax+b basic non-linearities involved. Section 111 presents the building blocks for the basic functions and describes some examples where the global topology of the generator can be simplified by taking advantage of symmetries. section IV shows experimental obtained from a chip which has been fabricated in a rameters of the circuit are electrically controllable to enable fully programmable operation. and sgn(*) denotes the sign function, Fig.2(a) shows an example of this procedure. Based on the extension operator, Chua and Kang have developed a canonical representation for unidimensional pm functions given by 1pm standard digital CMOS technology. All the pa- N i= 1 g(x) = ax+b+ (3) 0-7803-3073-0/96/$5 .OO @I996 IEEE 469 I \ I (a) 8 @) FIGURE 2. Piecewise linear decomposition of a function (a) using the extension operator concept, and @) using basic linear functions. which involves only one non-linearity, the absolute value function, with the additional advantage that it requires a minimal number of fitting parameters [9]. A different approach for the representation of nonlinear functions is to express the transfer characteristic as a linear combination of basis functions, each having compact support over a corresponding subinterval of the partition. In the case of PWL functions, basis functions are called linear basis functions (LBF), and lead to the following expression, (4) Fig.3 shows the shape of the ith LBF, which equals 1 at 6i and decreases to 0 at Fig.2(b) illustrates the representation technique based on LBFs, using the same function f(x) used to describe the extension operator. Note that the LBF representation is more modular than the approximation based on the extension operator. However, this modularity is not for free; their implementation is not the cheapest in terms of components and consequently, may not be optimal for applications in which the target function is fixed. On the contrary, the representation (4) is an excellent option in the design of fully programmable function generators. and Si+*. In. Current-Mode Linear Basis Functions The proposed design technique for linear basis functions is based on the interconnection of two basic building blocks: currenr switches and programmable current ampli8ers. Current Switch Fig.4(a) and (b) show respectively the symbol and schematic of the current switch proposed in [IO]. This block routes the input current to either the upper or the lower terminal depending on its sign. Besides, it generates a logical signal V, which codifies the current sign (V, = '1 ' for Zi, > 0, and V, = '0' otherwise). The circuit exhibits very high resolution (around IOpA), and is insensitive to transistor mismatch. Thus, it can be realized through minimum size devic- (C) FIGURE 4. (a) Current switch symbol; (b) Proposal in [lo]; (c) Alternative design using current mirrors and inverters. es. Additionally, the feedback loop created by the inverter Invl allows significant reduction of the dead zone non-linearity shown by the input driving-point characteristic, which alleviate loading errors of the circuit with the environment. An alternative design for the current switch is shown in Fig.4(c). As opposed to the previous case, positive (negative) currents are now routed to the lower (upper) terminal, as a consequence of the mirrors included in the current path. Simulation results show that the circuit is especially suited for low voltage operation (correct performance has been noted for supply voltages of less than 2 V). The main drawback of this structure is that currents I+ and I- are affected by the mismatch of the transistors making up the current mirrors. Programmable Current Amplifer Fig.S(a) shows the conceptual block diagram of a programmable current amplifier. It is formed by the series connection of a grounded resistor and a tunable linearized transconductor. The schematics in Fig.S(b) (output stage) and Fig.S(c) (core block) form the complete circuit amplifier. The grounded resistor is realized through a pair of p channel transistors in diode configuration, connected in cascode with the external nodes connected to the rails. As shown in FigS(c), the linear I-V conversion is done in the core block. The configuration described in [ 1 13 has been chosen for the linearized transconductor, introducing some modifications to increase the gain adjustment range. First, the input PMOS differential pair in [ 1 I] has been replaced by a NMOS pair and two p-channel cascode mirrors to increase the variation range of voltages VI and V,. Next, the common-source node of the output differential pair has been connected to a voltage follower of very low output resistance to supply a fairly constant voltage drop, V,. On one hand, this obtains low current gain values. On the other, gives an increased efficiency for the current flowing through the output stage. Finally a set of analog switches driven by the binary signal V,y has been included in the output pair to determine the sign of the output current, Using the quadratic law of a MOS transistor in saturation, the gain of the amplifier reads as: 470 p-mirror p-mirror W$W p-channel cascode mirror p-channel cascode mirror FIGURE 5. Programmable current amplifier: (a) Concept; (b) Amplifier output stage; (c) Core block. where the sign is defined by the binary signal V,. As it is seen, the gain depends linearly on the control voltage V,. Correct performance enforces the following conditions on the electrical variables: Current-Mode Basic Functions Fig.6(a) shows the block diagram for a LBF formed by three current switches, two current amplifiers, and four analog switches in the output stage. Note that the central current switch supplies the binary signal that determines the sign of the current amplifiers and the output branch through which I,,, flows. The combination of current switches and voltage amplifiers also enables implementing the elementary functions for the other approximation techniques cited in Section 11. Thus, Fig.6(b) shows an example of extension operator construction and Fig.6(c), the realization of the absolute value function. Fig.6(d) shows the realization of a trapezoidal function, frequently used as a membership+function in fuzzy logic. Note that instead of using two linear basis function like those in Fig.6(a), the function symmetry enables reducing the number of circuit components. Finally, Fig.6(e) shows an example of construction of functions with finite jump discontinuity, taking advantage of the binary signal generated by the current switches, together with the logic gates. IV.Experimenta1 Results Fig.7 presents a microphotograph of the integrated prototype of a programmable linear basis function fabricated in single poly 1 .Opm CMOS technology. The current switches used in the design are shown in Fig,4(b). Fig,8(a) shows the transfer characteristics of 16 'in -e*= I*" SI s2 (e) FIGURE 6. Block diagrams of: (a) linear basis function; (b) extension operator; (c) absolute value; (d) trapezoidal function, and (e) discontinuous function. 400 pm FIGURE 7. Microphotograph of the circuit. the implemented current amplifier. The amplifier gain ranges from 0 to 25 for input linearity between flpAmP. This gain variation is given by the control signal adjustment, Vc, whose valid range is between - 0.5 V and 1.3 V. Voltage VF and bias current were set at -1.8 'V and15 pAmps, respectively. Fig.8(b) shows the deviations of the linear behavior of the current amplifier for different values of control voltage Vc. The relative error in all cases was less than 0.6%. Fig.9 shows a group of experimental curves for the transfer function of the whole circuit, obtained through individual variation of each of the Hermite 471 TI -i . 000 (a) 0.5 w 0.3 bo h 9-9 E y 0.1 2 -0.1 > .“ I - -0.3 0.0 0.2 0.4 0.6 0.8 1.0 v, = -0.5 v, = 0.2 V, = 1.3 Input Current @Amp) (b) FIGURE 8. Experimental response of a programable current amplifier. (a) Transfer characteristic; (b) Nonlinearity error for different values of the control variable. operator parameters. Fig.9(a) represents the variation of the height of the basis function for different positive and negative values of I,. Fig.9(b) shows the curve family obtained through variation of 18, maintaining the rest of the parameters constant. Fig.B(c) and (d) show the variation of the linear basis function slopes obtaining by adjusting the gain of the corresponding current amplifiers. V.References Khachab, N.I. and Ismail, M., 1991, “Linearization Techniques for nth-Order Sensor Models in MOS VLSI Technology”. IEEE Transactions on Circuits and Systems, vol. 38 (December), pp. 1439- 1449. Fattaruso, J.W. and Meyer, R.G., 1987. “MOS Analog Function Synthesis”. IEEE Journal of Solid-state Circuits, vol. 22 (December), pp. 1059-1063. Fattaruso, J.W. and Meyer, R.G., 1985. “Triangle-to-Sine Wave Conversion with MOS Technology”. IEEE Journal of Solid-state Circuits, Watson, G.A., 1980. “Approximation Theory and Numerical Methods”. Wiley, New York. Sheingold, D.H., 1976. “Nonlinear Circuits Handbook”. Analog Devices Inc., Norwood. Sanchez-Sinencio, E., Ramirez-Angulo, J., Linares-Barranco, B. and Rodriguez-Vtizquez, A., 1989. “Operational Transconductance Amplifier-Based Nonlinear Function Synthesis”. IEEE Journal of Solid-state Circuits, vol. 24 (December), pp. 1576-1586. Liu, S.-I., Wu, D.-S., Tsao, H.-W., Wu J. and Tsay, J.-H., 1993. “Nonlinear Circuit Application with Current Conveyor”. IEE Proceedings- G, vol. 140 (February), pp. 1-6. Rodriguez-VBzquez, A., Delgado-Restituto, M., Huertas, J.L. and Vidal, F., 1995. “Synthesis and Design of Nonlinear Circuits”. chapter 32 in The vol. 20 (April), pp. 623-631. Circuits and Filters Handbook (W.K. Chen), CRC Press - IEEE Press, Boca Ratbn. [9] Chua, L.O. and Kang, S.M., 1977. “Section- Wise Piecewise-Linear Functions: Canonical Representation, Properties and Applications”. Proceedings of the IEEE, vol. 67 (June), pp. 915- 929. [ 10]A. Rodriguez-VBzquez and M. Delgado-Restitu- to, 1994. “Generation of Chaotic Signals Using Current-Mode Techniques”. Journal of Intelligent & Fuzzy Systems, vol. 2, No. 1, pp. 15-37. [llIKlumperink, E., Zwan, E. v.d. and Seevinck, E., 1989. “CMOS Variable Transconductance Circuit with Constant Bandwidth”. Electronic Letters, vol. 25 (May), pp. 675-676. (a) f““c:u u.00 P . 000 fdlv 0 -2.000 -5.0 000 (b) roY:, 7.000 1.000 /dlV 0 GOO -s. 000 -1.0 (C) :OUT ILIA) 7.000 i 000 ?dlV 0 -a. ooo IINPLJT !Z?OOO/aiv IUAI l.ooo -1.000 (d) FIGURE 9. Experimental results obtained from the integrated prototype: (a) Variation with I,; (b) Variation with Is; (c) and (d) Variation with slopes. 472