High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 9, SEPTEMBER 2005 1795 High-Level Synthesis of Switched-Capacitor, Switched-Current and Continuous-Time 61 Modulators Using SIMULINK-Based Time-Domain Behavioral Models Jesús Ruiz-Amaya, José M. de la Rosa, Member, IEEE, Francisco V. Fernández, Fernando Medeiro, Member, IEEE, Rocío del Río, Member, IEEE, Belén Pérez-Verdú, and Angel Rodríguez-Vázquez, Fellow, IEEE Abstract—This paper presents a high-level synthesis tool for 61 modulators ( 61 s) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for 61 synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of 61 s using both discrete-time and continuous-time circuit techniques. Index Terms—Analog-to-digital, behavioral modeling, continuous-time circuits, sigma–delta modulator, synthesis, swithced capacitor, switched current. I. INTRODUCTION NOWADAYS there is a trend toward integrating complete mixed-signal systems onto a single chip. Together with reduced price, size and power consumption, these systems-onchip are prompting the development of a new generation of electronic systems that feature larger functionality through the closer interaction between the real world and the digital processing circuitry. In many of these systems, sigma-delta modulators ( s) have demonstrated to be very well suited for the implementation of the analog-to-digital (A/D) interface. This type of A/D converters (ADCs), composed of a low-resolution Manuscript received June 25, 2004; revised December 2, 2004. This work was supported by the EU IST Project 2001-34283/TAMES-2 and by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under Contract TIC2001-0929 ADAVERE and TEC200401752/MIC. This paper was recommended by Associate Editor T. B. Tarim. The authors are with the Institute of Microelectronics of Seville-Centro Nacional de Microelectrónica (IMSE-CNM), 41012 Seville, Spain (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2005.852479 quantizer embedded in a feedback loop, uses oversampling (a sampling frequency much larger than the Nyquist frequency) to reduce the quantization noise and modulation to push this noise out of the signal band [1]. The combined use of redundant temporal data (oversampling) and filtering ( modulation) results in high-resolution, robust ADCs, which have lower sensitivity to circuit parasitics and tolerances, and are more suitable for the implementation of A/D interfaces in modern standard CMOS technologies [2]–[5]. However, the need to design high-performance ADCs in adverse digital technologies together with the vertiginous rate imposed by the technology evolution has motivated the interest for CAD tools which can optimize the design procedure of the analog interface—traditionally the design bottleneck—in terms of efficiency and short time-to-market. For this purpose, several tools for the synthesis of oversampling ADCs have been reported [3], [6]–[9]. These tools use different synthesis strategies that can be roughly classified into two main categories [3], [10]. •Knowledge-based synthesis tools, which are based on capturing the knowledge of experienced designers [6], [7]. Although the execution times are very short, the results still must be optimized because design procedures are usually based on approximate equations and very simple models. Additionally, they are closed tools, i.e., they are limited to a reduced number of topologies and the addition of new ones is a very costly process, and usually restricted to the tool developers. •Optimization-based synthesis tools [3], [8], [9], which are based on an iterative optimization procedure in which the synthesis problem is formulated as a cost function minimization problem that can be evaluated through numerical methods. The evaluation of the cost function can be performed by means of equations or simulations. In the former case, relatively short computation times are required, though the accuracy of the results depends on that of the equations. Furthermore, in this case the tool is closed because equations must be changed every time the topology is changed. These problems can be eliminated by using simulations for performance evaluation. In this case, the characteristics of the simulator determine the accuracy and flexibility of the tool. 1057-7122/$20.00 © 2005 IEEE 1796 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 9, SEPTEMBER 2005 Fig. 1. Conceptual block diagram of an optimization-based 61 M synthesis tool. Most modern approaches for the synthesis of s use optimization-based strategies, usually combining an optimization core for design parameter selection with a simulator for performance evaluation [3], [8], [9]. Conceptually speaking, a conventional optimization-based synthesis tool follows the block diagram shown in Fig. 1. The high-level design process of a starts from the modulator specifications (resolution, signal bandwidth, etc.). The objective is to get the design parameters that optimize the performance of the modulator; that is, those block specifications which satisfy the modulator specifications with the minimum power consumption and silicon area. At each iteration of the optimization procedure, circuit performances are evaluated at a given point of the design parameter space. According to such an evaluation, a movement in the design parameter space is generated and the process is repeated again. There are two alternatives for the implementation of such an iterative procedure. •Deterministic techniques, where parameter updating requires information on the cost function and on their derivatives. Only changes of design parameters that make the cost function to decrease are allowed. Therefore, the optimization process may be quickly trapped in a local minimum of the cost function. So, the usefulness of these techniques concentrates on the fine tuning of suboptimal designs. •Statistical techniques, where design parameters are changed randomly and, hence, information on the derivatives of the cost function is not required. The main advantage of the statistical techniques with respect to the deterministic ones is the capability to avoid local minima thanks to a nonzero probability of accepting movements that increase the cost function. Therefore, these techniques are appropriate for global optimization, that is, cases in which no good initial design point in Fig. 1. is available. The price to pay is a larger computational cost. In this paper, an integrated approach is applied: statistical techniques are applied for wide design space exploration whereas deterministic techniques are used for fine-tuning of best solutions found by the previous techniques. Besides, the addition of knowledge about specific architectures has been enabled. Such knowledge can be coded using a standard programming language: C or C++, which is compiled at run-time and incorporated into the optimization process. This makes the proposed synthesis toolbox an optimization-based synthesis tool but with the appealing features of knowledge-based systems. The iterative nature of the optimization procedure—normally requiring hundreds or even thousands of iterations to find out an optimum solution—demands a very efficient simulation engine capable of providing a fast and precise performance evaluation. s are strongly nonlinear sampled-data circuits, and hence, simulation of their main performance specifications has to be carried out in the time domain. Due to their oversampling nature, this means that long transient simulations—involving thousands or millions of clock cycles—are necessary to evaluate their main figures of merit. Therefore, transistor-level simulations using SPICE-like simulators yield excessively long CPU times—typically several days, or even weeks [11]. To cope with this problem, different alternatives of -dedicated simulators have been developed, which at the price of sacrifying some accuracy in their models, reduce the simulation time [8], [9], [12], [13]. One of the best accuracy-speed trade-offs is achieved by using the so-called behavioral simulation technique [12], [13]. In this approach the modulator is broken up into a set of subcircuits, often called building blocks or basic blocks. These blocks are described by equations that express their outputs in terms of their inputs and their internal state variables. Thus, the accuracy of the simulation depends on how precisely those equations describe the actual behavior of each building block. Because of these advantages, previously reported optimization-based synthesis tools used event-driven behavioral simulation techniques [3], [8], [9]. In these tools, the simulation engine and the models are implemented using a conventional programming language like C. Modulator libraries are usually available, containing a limited number of architectures. Although a text or graphical interface is usually provided to create new architectures, block models cannot be easily modified. On the other hand, the possible circuit techniques used to implement the modulators are constrained by the capabilities of the simulation engine and the available block models. For that reason, the synthesis tools reported in the open literature are limited to switched-capacitor (SC) s [3], [8], [9]. To overcome these problems, the synthesis tool proposed in this paper has been implemented by using the MATLAB/SIMULINK platform [14], [15]. The embedded behavioral simulator is able to efficiently evaluate the performances of low-pass (LP) or bandpass (BP) s implemented using either SC , switched-current (SI) or continuous-time (CT) circuit techniques. This enables the synthesis tool to deal with all those types of s. The implementation on the MATLAB/SIMULINK platform provides a number of advantages. •It is a widely used platform, familiar to a large number of engineers, whereas special-purpose tools [8], [9] require dedicated training on a proprietary text-based or graphical interface. •It has direct access to very powerful tools for signal processing and data manipulation. RUIZ-AMAYA: CONTINUOUS-TIME USING SIMULINK-BASED TIME-DOMAIN BEHAVIORAL MODELS 1797 Fig. 2. Illustrating the GUI for editing modulator topologies of the 61 M synthesis toolbox. •It has full flexibility to create new architectures, and even to include different blocks, either of CT or discrete-time (DT) type. •It enables a high flexibility for the extension of the block library whereas the addition of new blocks or models to existing libraries in previous tools requires the qualified contribution of a programmer. Modeling and simulation of s in the MATLAB/SIMULINK platform was first reported in [16] and [17], albeit limited to SC architectures. Although very intuitive, the implementation of the behavioral models of each basic building block requires several sets of elementary SIMULINK blocks using MATLAB functions. This means a penalty in computation time which may become critical in an optimization-based synthesis process in which hundreds or thousands of simulations must be executed. This paper solves these problems by using the so-called S-functions [18] to implement the behavioral models in SIMULINK. The use of these functions allows to decrease the computational cost to acceptable figures for synthesis purposes. Thus, the CPU time for the time-domain simulation of a DT/CT involving 65 536 samples and considering the most complex nonlinear behavioral models (see Section III) is typically a few seconds,1which is comparable with the simulation times obtained with hard-coded dedicated simulators [8], [9], [13]. Besides, the proposed toolbox is able to deal with any 1All simulations shown in this paper were done using a PC with an AMD XP2400 CPU@2 GHz @512 MB-RAM. circuit technique: SC, SI, or CT. For this purpose, a complete list of building blocks (integrators, resonators, quantizers, etc.) including their main nonidealities for all circuit techniques has been included [3]–[5]. The accuracy of the behavioral models has been verified by electrical simulation using HSPICE, at the block level, and even by experimental measurements taken from silicon prototypes, at the modulator level [19], [20]. This paper is organized as follows. Section II describes the proposed synthesis methodology and summarizes the major features of the embedded tools, namely: the optimization core and the behavioral simulator, together with the relevant aspects of the implementation in the MATLAB/SIMULINK framework. Section III presents a detailed description of the behavioral models used. Finally, Section IV gives several simulation and synthesis examples of the synthesis toolbox. II. PROPOSED SYNTHESIS TOOLBOX As stated earlier, the presented synthesis tool uses an advanced optimization core for design parameter selection and a time-domain behavioral simulator for performance evaluation. The proposed tool has been conceived as a MATLAB toolbox for the simulation and synthesis of s. Fig. 2. shows some parts of the toolbox comprising a Graphical User Interface (GUI) to allow the designer browse through all steps of the simulation, synthesis and post-processing of results. High-level synthesis is started from the synthesis menu, where constraints, performance specifications, design parameters, optimization algorithms, etc., can be specified. Then, the optimization core 1798 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 9, SEPTEMBER 2005 Fig. 3. Operation flow of the optimization core. starts the exploration of the design space to find out the optimum solution by using the simulation results for performance evaluation. A. Optimization Core The MATLAB standard distribution includes a number of optimization methods [14]. However, all these methods are based on deterministic optimization strategies. They are very fast but they evolve toward the closest local minimum. Therefore, the quality of the results strongly depends on the initial conditions. This makes these methods appropriate for local optimization of an already good design. Global optimization algorithms include a variety of evolutionary and simulated annealing algorithms with all their derivatives. The optimization core used in this paper combines an adaptive statistical optimization algorithm inspired in simulated annealing, in which local minima of the cost function can be efficiently avoided, with a design-oriented formulation of the cost function, which accounts for the modulator performances [3]. Unlike conventional simulated annealing procedures, in which the control parameter—commonly named temperature—follows a predefined temporal evolution pattern, the implemented global optimization algorithm dynamically adapts this temperature to approximate a predefined evolution pattern of the acceptance ratio (accepted movements/total number of iterations). This idea prevents excessively high temperatures which will make convergence difficult and inappropriately low temperatures which can make the algorithm to become stuck on a local minimum. The amplitude of parameter movements through the design space is also synchronized with the temperature for improved convergence. Fig. 3. shows the flow diagram of the optimization core. The starting point is the modulator topology whose design parameters (building block specifications) are not known. Considering arbitrary initial conditions, a set of perturbations of the design parameters is generated. With the new design parameters, the appropriate simulations are performed to evaluate the modulator performance. From the simulation results, the optimization core automatically builds a cost function, that has to be minimized. The type and value of the perturbations as well as the iteration acceptance or rejection criteria depend on the selected optimization method. The optimization process is divided into two steps: •The first step explores the design space by dividing it into a multidimensional grid, resulting in a mesh of hypercubes (main optimization). A statistical method is applied in this step to escape from local minima, as there is a nonzero probability of accepting movements that increase the cost function [3]. •Once the optimum hypercube has been obtained, a final optimization is performed inside this hypercube (local optimization). A deterministic method is usually applied in this step, where the calculation of the design parameter perturbations requires information on the cost function and on their derivatives. In addition, the optimization core is very flexible, in so far as the cost function formulation is very versatile: multiple targets with several weights, constraints, dependent variables, and logarithmic grids are permitted. This optimization procedure has been extensively tested with design problems involving behavioral simulators as well as electrical simulators [3], [9]. For efficiency reasons, this optimization core has been conceived as an independent application whereas the behavioral simulator runs in MATLAB/SIMULINK. In order to integrate both processes, a special-purpose application has been developed by using the MATLAB engine library [14]. This application is responsible for the communication between the optimization core and the behavioral simulator so that the optimization core runs in background while MATLAB acts as a computation engine. B. Time-Domain Behavioral Simulator The proposed synthesis tool uses a time-domain behavioral simulator as a performance evaluator. The simulator, called SIMSIDES (SIMulink-based SIgma-DElta Simulator), has been implemented as a toolbox in the MATLAB/SIMULINK environment, thus taking advantage of a friendly GUI, high flexibility for the extension of the subcircuit library and huge signal processing capabilities [21]. Recently, a set of SIMULINK block models were proposed for the behavioral simulation of SC s [16], [17]. The models included—based on the interconnection of SIMULINK standard library blocks—are very useful for system-level evaluation. However, they have some limitations. •The block library is limited to SC circuits, and use relatively simple models which do not take into account some limitations like, for instance, nonlinearities associated to the open-loop opamp dc gain and capacitors. In addition, as models are implemented in the -domain, the circuit behavior during different clock phases is not considered, thus leading to not very accurate modeling of some errors like the incomplete settling. •Block models are realized by using MATLAB functions. This causes the MATLAB interpreter to be called at each time step, dramatically slowing down the simulation. This problem is aggravated as the model complexity increases, yielding to excessive CPU times as compared to dedicated RUIZ-AMAYA: CONTINUOUS-TIME USING SIMULINK-BASED TIME-DOMAIN BEHAVIORAL MODELS 1799 Fig. 4. Illustrating some blocks of the 61 M block libraries included in the simulator SIMSIDES. (a) SC integrators. (b) CT resonators. (c) Quantizers and comparators. (d) DACs. (e) Second-order SC LP 61 M . (f) Second-order CT LP 61 M . simulators. This is true even using the SIMULINK accelerator [15]. The proposed simulator, SIMSIDES, is able to simulate not only SC but also SI and CT s. The toolbox includes different sublibraries which are classified according to the modulator hierarchy level [integrators, quantizers, flash sub-ADCs, digital-to-analog converters (DACs)] and the circuit technique (SC, SI, and CT). As an illustration, Fig. 4. shows some of the most representative sublibraries showing different types of integrators, resonators (basic building blocks used in BP s), quantizers and DACs. There are also several libraries including the most usual architectures of both LP and BP s using SC, SI, and CT circuits. For each building block, the block library provides models with a different abstraction level. High-level (lower accuracy) models are suitable for system-level simulation, design space exploration and initial transmission of specifications to the block level. Low-level (higher accuracy) models, which take into account 1800 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 9, SEPTEMBER 2005 Fig. 5. Architecture of the proposed behavioral simulator, SIMSIDES. the main circuit parasitics, are suited for fine-tuning the specs transmission and circuit validation. Simulation efficiency is a critical factor in synthesis applications. For this reason, SIMULINK S-functions [18] have been used as implementation platform for the behavioral models of the different building blocks. These functions are special-purpose source files which allow to add computation algorithms written in C to SIMULINK models. The outcome is a notable saving of simulation time as compared to using MATLAB functions or M-files to code the models, even when the accelerator utility is used [15]. For example, the simulation over 65 536 clock periods of a cascade 2-1-1 SC considering the most complex models, i.e., including all nonidealities and nonlinearities of the building blocks,2takes 3 s using the proposed simulator. If analogous models are implemented by using M-files, the simulation time rises to 141 s, i.e., about 50 times slower than the approach in this paper. Fig. 5. shows the general structure of SIMSIDES. First, the modulator architecture is defined by appropriately interconnecting the building blocks included in SIMSIDES libraries (see Fig. 4.). After the circuit diagram is created, the user sets some parameters and options which are taken into account by the tool to perform the time-domain simulation. Monte Carlo simulations as well as parametric analysis are also possible. Output data generated by the simulator consists of time-domain series which can be processed to get different figures of merit. Thus, histograms and output spectra are computed using the routines provided by the signal processing toolbox of MATLAB. Other analyses such as signal-to-noise ratio (SNR), harmonic or intermodulation distortion (IMD), are done using a collection of functions specifically developed for SIMSIDES. C. Model Implementation Procedure Model implementation follows a set of steps, which are illustrated in Fig. 6. •Definition of a computation model. Given a set of nonidealities of the building blocks, a computation model which 2The models include finite open-loop opamp dc gain, incomplete settling error, mismatch capacitor ratio error, thermal noise; and main nonlinear effects, namely: nonlinear sampling switch-on resistance, nonlinear open-loop opamp dc gain, slew rate and nonlinear capacitors. allows to calculate the output samples including the effect of all those nonidealities must be defined. For illustration’s sake, let us consider the SC Forward-Euler (FE) integrator in Fig. 6(a). The construction of a behavioral model which takes into account the effect of the finite and nonlinear dc gain of the amplifier requires a computation model shown in Fig. 6(b). An iterative procedure3 is needed because the output voltage of the integrator depends on the amplifier gain but due to the nonlinearities, such gain also changes with the output voltage. When more nonidealities are to be considered, a more complex computation model, which appropriately takes all nonidealities into account in the right sequence, is needed. •Implementation of the computation model into an S-function. For this purpose, SIMULINK provides different S-function templates which can accommodate the C-coded computation model of both DT and CT systems. These templates are composed of several routines that perform different tasks required at each simulation stage [18]. Among others, these tasks include: variable initialization, computation of output variables, update of state variables, etc. For illustration purposes, Fig. 6(c) shows some significant sections of the S-function file associated to the SC integrator with nonlinear amplifier dc gain. It includes model parameters, clock phase diagram, computation model code, etc. •Compilation of the S-function. This is done by using the mex utility provided by MATLAB [18]. The resulting object files are dynamically linked into SIMULINK when needed. •Incorporation of the model into the SIMULINK environment. This can be done by using the S-function block of the SIMULINK libraries [15]. Fig. 6(d) illustrates this process for the SC integrator of Fig. 6(a). A block diagram containing the S-function block is created including the input/output pins. The dialogue box is used to specify the name of the underlying S-function. In addition, model parameters are also included in this box, which can be used to modify the parameter values. III. ACCURATE AND EFFICIENT MODELING OF BUILDING BLOCKS USING SIMULINK Behavioral models included in SIMSIDES can be grouped into two main categories: DT and CT circuits. The former, describing SC and SI subcircuits, are based on a set of finite-difference equations. In this case, the value of signals is important only at specific time points. Therefore, the simulation process consists of computing the node voltages and branch currents of the circuit consecutively at the end of each clock phase. This can 3The convergence criterion used in the iterative procedure of the behavioral models is: abs[(New param value 0 Old param value) = New param value] < thrs , where thrs is the threshold value chosen for convergence (normally thrs = 0 : 01 ), abs( x ) stands for the absolute value of x , and New_param_value and Old_param_value are, respectively, the old and new values of the parameter to be solved—for instance A in the example of Fig. 6. Using this criterion, convergence is reached normally in 3 or 4 iterations, which does not result in excessively costly CPU time. RUIZ-AMAYA: CONTINUOUS-TIME USING SIMULINK-BASED TIME-DOMAIN BEHAVIORAL MODELS 1801 Fig. 6. Steps to incorporate a behavioral model in SIMSIDES. (a) Modeled nonideality. (b) Computation model. (c) Excerpt of S-function code. (d) S-function block. be done very efficiently because analytical integration of block model equations can be performed over one clock period and modulator simulation reduces to evaluation of the solved model equations. Only a few seconds are typically needed for the evaluation of an output spectrum. Behavioral models of the second category, corresponding to CT building blocks, are described by a set of continuous-time state-space equations which are integrated by SIMULINK solvers [15]. A promising analytical integration method has also been recently published for CT s, reporting comparable efficiency to the DT case [22]. This approach has not been adopted in our implementation of the toolbox due to some limiting restrictions: feedback loops within the continuous-time filter are not allowed (therefore, precluding the simulation of a significant number of modulator topologies) and difficulties in the implementation of some nonidealities. The basic building blocks modeled in SIMSIDES, as well as its nonidealities are summarized in Table I.4A complete description of each of these nonidealities is beyond the scope of this paper. However, since the efficiency of the proposed synthesis 4In the case of multibit DACs, a common method to reduce the effect of random component mismatches consists of using the so-called dynamic element matching (DEM) techniques. For this purpose, an additional subblock has been included that models those techniques. In particular, scrambling of the DAC element errors is implemented by a rotate data weigh averaging (RDWA) algorithm that provides noise-shaping of DAC element mismatches [23]. TABLE I BASIC BUILDING BLOCKS AND NONIDEALITIES MODELED IN SIMSIDES tool strongly depends on how accurately the models describe the real behavior of the corresponding subcircuits, this section describes the behavioral models of most critical building blocks—the integrators—with special emphasis on those aspects related to their implementation in the presented toolbox. 1802 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 9, SEPTEMBER 2005 Fig. 7. Conceptual SC FE integrator. (a) Schematic. (b) Clock phases. Fig. 8. Computation model for the SC FE integrator model. A. Behavioral Modeling of SC Building Blocks Fig. 7. shows the conceptual schematic5of a SC FE integrator together with the clock phases, where stands for the sampling period. The ideal behavior of this circuit can be described by the following difference equation:6 (1) where and are the integration and sampling capacitors, respectively. In practice, the ideal behavior described by (1) is degraded by the error mechanisms listed in Table I. These errors are computed in the proposed behavioral models by following the iterative procedure shown in the flow graph of Fig. 8. Note that there are two branches corresponding to the two clock phases. During the sampling phase, the final value of the voltage stored in the sampling capacitor , is calculated by considering the effect of incomplete settling and adding the total input-referred noise power-spectral density (PSD) of the integrator . This gives [3] (2) where stands for a random number in the range and (3) is the settling error caused by the finite time constant, with being the switch-on resistance. In practice, switches are realized with MOS transistors and hence, the value of strongly depends on the input signal. 5For simplicity, schematics are shown in its single-ended version, although actually the fully-differential structures have been modeled. 6In this paper, the notation v will be used to represent v ( nT ) . Fig. 9. Algorithm used to model the influence of finite and nonlinear switch-on resistance. Fig. 10. SC integrator—followed by a similar one for modeling purposes—and clock phases. This nonlinear behavior causes harmonic distortion, which increases with the ratio between the input frequency and the sampling frequency [24], thus being especially critical at the input node of broad-band s. Fig. 9. shows the algorithm used in SIMSIDES to model the nonlinear switch-on error. The sampling phase is divided into a number of time intervals in which the value of the switch-on resistance is evaluated by using a polynomial dependence of the input voltage, , at the end of each time interval.7 Once the sampling voltage is computed, the output voltage is calculated by considering the amplifier dynamics, capacitor errors,8finite (nonlinear) opamp dc gain and output saturation. For this purpose, the generic scheme shown in Fig. 10 is solved in the behavioral model [25]. This scheme includes: •a number of input branches, each of them formed by a sampling capacitor and four switches—controlled by two nonoverlapping phases, and —which commute the sampling capacitor between voltages and ; 7The coefficients of this polynomial function can be used with a double purpose. On the one hand, in a synthesis process they are used to evaluate the maximum nonlinearity tolerated for a given specification. On the other hand, a look-up table approach can also be used for verification of a given design. 8Mismatch errors and voltage dependencies have been included in the capacitor models. RUIZ-AMAYA: CONTINUOUS-TIME USING SIMULINK-BASED TIME-DOMAIN BEHAVIORAL MODELS 1803 Fig. 11. Transient response of an SC integrator: comparison between HSPICE and SIMSIDES. •a second integrator (load) whose input branches are assumed to be connected to the integrator output during the sampling phase. The th branch of the second integrator is connected to a voltage during the integration phase; •the model used for the amplifier (depicted in Fig. 10.) includes: a one-pole dynamics and a nonlinear characteristic, with maximum output current . This model of the SC integrator takes into account the amplifier and limitations, as well as the parasitic capacitors associated to its input and output nodes . Moreover, the capacitive load at the integrator output is assumed to change from the integration to the sampling phase, reflecting the actual situation in most SC s. The equivalent circuits in Fig. 10 are evaluated during both clock phases: sampling and integration , considering all the possibilities of the amplifier in operation: either linearly or in slew . An iterative procedure (see Fig. 8) is needed in order to solve the transient response since the opamp dc gain depends on the output voltage. This dependence is modeled as (4) where is the zero-bias dc gain and stands for the th nonlinear coefficient.9 The iterative procedure in Fig. 8 converges typically in a few iterations, providing very precise results. As an illustration, Fig. 11 compares the model simulation results versus HSPICE electrical simulation. This figure shows the transient response of a series connection of a single-branch SC FE integrator and a two-branch SC FE integrator when a constant input voltage is applied. It can be seen that both electrical and behavioral simulations agree. 9It is important to note that nonlinear coefficients (avnl ) can be used either in a top-down (synthesis) approach or a bottom-up (verification) approach. In the former case, avnl are design variables that are solved by the optimization procedure for given modulator specifications. In the latter case, i.e., for verification, coefficients avnl can be obtained from a curve fitting process of a real dc gain characteristic from an electrical simulation, or even from measurements. In this case, a look-up table approach can be also used, which is also supported by the behavioral models included in SIMSIDES. B. Behavioral Modeling of SI Building Blocks A large number of topologies of SI building blocks have been modeled in the proposed toolbox. As an illustration, Fig. 12(a) shows a fully differential regulated folded cascode (RFC) SI lossless direct integrator (LDI). Similarly to the case of SC circuits, the model evaluates the state and output variables at the end of each sampling phase by following the flow graph shown in Fig. 12(b). During clock phase, —corresponding to the sampling phase for memory cell 2 and the hold phase for memory cell 1—the differential-mode drain current of memory cell 2, is computed. The first step consists in determining the steady state of , represented as . For this purpose, the equivalent circuit shown in Fig. 12(c) is used in the model. In this circuit, memory cell 1 is modeled by its Norton equivalent, i.e., a current source of value in parallel with the output conductance of the memory cell represented by . The steering switch is modeled as a finite (nonlinear) switch-on resistance, . On the other hand, the model of memory cell 2 consists of the parallel connection of its output conductance with its input impedance. This impedance is modeled as a nonlinear function of . This function, , can be included in the model either by using a look-up table approach or by a parametric function which depends on the topology of the cell. In the particular case of a RFC memory cell (5) where is the bias current, represents the small-signal transconductance of the memory transistor at the operating point, and stands for the voltage gain of the stage used to increase the input conductance. The solution of the circuit in Fig. 12(c) is computed through an iterative procedure which typically converges in two or three iterations. The second step of Fig. 12(b) is to compute the effect of the settling error. This error—caused because the gate-source capacitance charging is not completed at the end of clock phase —is calculated by using the equivalent circuit shown in Fig. 12(d), where (6) and (alternatively ) is the gate voltage of the memory transistor (alternatively ). During the transition between both clock phases the charge injected by memory switches on the differential gate-source capacitor causes an additional error in the differential gate-source voltage of memory cell 2 which is added in the model to the thermal noise . During clock phase —sampling phase for memory cell 1 and hold phase for memory cell 2—the output current, 1810 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 9, SEPTEMBER 2005 [21] J. Moreno Reina, J. M. de la Rosa, F. Medeiro, R. Romay, R. del Río, B. Pérez-Verdú, and A. Rodríguez-V ´zquez, “A SIMULINK-based approach for fast and precise simulation of switched-capacitor, switchedcurrent and continuous-time 61 modulator,”in Proc. IEEE Int. Symp. Circuits Syst., May 2003, pp. IV.620–IV.623. [22] G. Gielen, K. Francken, E. Martens, and M. Vogels, “An analytical integration method for the simulation of continuous-time 61 modulators,” IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst., vol. 23, no. 3, pp. 389–399, Mar. 2004. [23] R. E. Radke, A. Eshraghi, and T. S. Fiez, “A 14-bit current-mode 61 DAC based upon rotated data weighted averaging,”IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1074–1084, Aug. 2000. [24] W. Yu, S. Sen, and B. H. Leung, “Distortion analysis of MOS track-and-hold sampling mixers using time-varying volterra series,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 2, pp. 101–113, Feb. 1999. [25] R. del Río, F. Medeiro, B. Pérez Verdú, and A. Rodríguez Vázquez, “Reliable analysis of settling errors in SC integrators—application to the design of high-speed 61 modulators,”in Proc. IEEE Int. Symp. Circuits Syst., vol. 4, May 2000, pp. 417–420. Jesús Ruiz-Amaya received the “Ingeniero de Telecomunicación”(telecommunication engineering) degree in 2003 from the University of Seville, Seville, Spain. He is currently pursuing the Ph.D. degree at the same university. Since 2003, he has been with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC). His main research interests are in analog–digital converters, especially pipelined and sigma–delta converters, and current steering digital–analog converters including modeling, behavioral simulation, and design automation. JoséM. de la Rosa (M’00) received the “Licenciado en Física Electrónica”(electronics physics) degree in 1993 and the “Doctor en Ciencias Físicas”(Ph.D.) degree in 2000, both from the University of Seville, Seville, Spain. Since 1994, he has been with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC), of the Spanish Microelectronics Center. He is also with the Department of Electronics and Electromagnetism, School of Engineering, University of Seville, where he is an Associate Professor. His main research interests are in the field of mixed-signal integrated circuits, especially pipeline and sigma-delta analog-to-digital converters including analysis, behavioral modeling and design automation of such circuits. He has participated in several National and European R&D projects and has coauthored more than 70 international scientific publications, including journal and conference papers, book chapters and the book Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips (Boston, MA: Kluwer, 2002). Francisco V. Fernández received the physics degree in electronics in 1988 and the Ph.D. degree in 1992, both from the University of Seville, Seville, Spain. In 1988 he joined the Department of Electronics and Electromagnetism, University of Seville, and in 1991 he was appointed as an assistant professor. During 1993 he was with the ESAT Laboratory of the Katholieke Universiteit Leuven, Belgium, as a Senior Researcher. Since 1995 he has been an Associate Professor with the University of Seville. He is also with the Institute of Microelectronics of Seville, which is part of the National Research Council. He has been editor of one book and has authored more than 90 papers in books, journals, and conference proceedings. His research interests include design and modeling of analog integrated circuits and analog design automation. Fernando Medeiro (M’98) was born in Higuera de Vargas, Badajoz, Spain. He received the “Licenciado en Física Electrónica”degree in 1990 and the “Doctor en Física”(Ph.D.) degree with honors in 1997, both from the University of Seville, Seville, Spain. Since 1991 he has been with the Microelectronics Institute of Seville (IMSE, C.S.I.C.). He is also with the Department of Electronics and Electromagnetism, “Escuela Superior de Ingenieros,”University of Seville, where he is an Associate Professor. His research interest are in the field of Sigma-Delta converters, including modeling, behavioral, simulation, and design automation. In this topic, he has participated as a Lecturer in several international courses and has coauthored the book Top-Down Design of High-Performance Sigma-Delta Modulators (Boston, MA: Kluwer, 1999). Rocío del Río(M’04) received the “Licenciado en Física Electrónica”degree in 1996 and the Ph.D. degree in 2004, both from the University of Seville, Seville, Spain. She joined the Department of Electronics and Electromagnetism, University of Seville, in 1995, where she is currently an Assistant Professor. Since 1995 she has also been with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC). Her main research interests are in ADCs, especially sigma-delta converters, including modeling, behavioral simulation, and design automation. BelénPérez-Verdúwas born in Monóvar, Spain. She received the Licenciado en física degree and the Doctor en Ciencias físicas degree from the University of Seville, Seville, Spain, in 1979 and 1985, respectively She is an Associate Professor with the University of Seville, Seville, Spain, since 1987. She is also with the Institute de Microelectronics of Seville (IMSE-CNM). Her research activities are in the field of mixed-signal integrated circuit design, in particular, sigma-delta modulators; computer-aided design, and modeling of analog integrated circuits. She has published two books and more than 70 papers including journal and conference papers. She has participated in several European ESPRIT projects and Spanish CICYT projects. Angel Rodríguez-Vázquez (M’80–SM’95–F’96) received the Liceniado en física electrónica and the Ph.D. degrees from the University of Seville, Seville, Spain, in 1977 and 1983, respectively. He is a Professor of Electronics with the Department of Electronics and Electromagnetism, University of Seville. He is also a member of the research staff of the Institute of Microelectronics of Seville-Centro Nacional de Microelectrónica (IMSE-CNM)—where he heads a research group on analog and mixed-signal VLSI. His research interests are in the design of analog interfaces for mixed-signal VLSI circuits, CMOS imagers and vision chips, neuro-fuzzy controllers, symbolic analysis of analog integrated circuits, and optimization of analog integrated circuits. Dr. Rodríguez-Vázquez served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS from 1993 to 1995., as Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS Special Issue on Low-Voltage and Low-Power Analog and Mixed-Signal Circuits and Systems (1995), as Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG DIGITAL SIGNAL PROCESSING Special Issue on Advances in Nonlinear Electronic Circuits (1999), and as chair of the IEEE-CAS Analog Signal Processing Committee (1996). He was corecipient of the 1995 Guillemin–Cauer award of the IEEE Circuits and Systems Society, and the Best Paper Award of the 1995 European Conference on Circuit Theory and Design. In 1992, he received the Young Scientist Award of the Seville Academy of Science. In 1996, he was elected a Fellow of the IEEE for “contributions to the design and applications of analog/digital nonlinear ICs”.