A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology

A 5.3mW, 2.4GHz ESD Protected Low-Noise Amplifier in a 0.13μm RFCMOS Technology Davide Brandano, Manuel Delgado-Restituto, Jesús Ruiz-Amaya and Angel Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC) Edif.CICA-CNM, Avda. Reina Mercedes s/n, 41012 - Sevilla, SPAIN Phone: +34 955 05 6666, Fax: +34 955 05 6686, E-mails: [brandano|mandel|ruiz|angel]@imse.cnm.es Abstract—An Electrostatic Discharge (ESD) protected LowNoise Amplifier (LNA) for the 2.4GHz ISM band designed in a 0.13μm standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8dB power gain, reflexion coeffcients S11, S22 < -30dB over the 2.4GHz ISM band, a peak noise figure of 1.8 dB, and an IIP3 of 1dBm, while drawing less than 4.5mA dc biasing current from the 1.2V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to ±2.0kV, by means of the additional custom protection circuitry. Index Terms—LNA, Electrostatic discharge (ESD) protection, Noise figure, RF CMOS. I. INTRODUCTION This paper presents the design of a 1.2V CMOS LNA, implemented in a 0.13μm RF process, for short range communications in the 2.4GHz unlicensed ISM (Industrial, Scientific and Medical) band, as defined by the standards Bluetooth, IEEE 802.11b/g or IEEE 802.15.4. The amplifier uses an inductively degenerated common-source topology and includes pads with ESD protection for reliability reasons. The influence on the amplifier performance of the parasitics from the ESD protection circuit, input and output pads, bondwires and package leads has been considered during design. The LNA achieves 16.8dB power gain with an input match of S11<-30dB over the ISM band, a peak noise figure lower than 1.8 dB, and an IIP3 of 1dBm, while drawing less than 4.5mA dc biasing current. Additionally, the protection circuits at the RF pads provide HBM ESD withstand voltages of ±2.0kV. The paper is organized as follows. In Section II, details on the design of the LNA are given. Section III describes the ESD protection circuitry and its influence on the LNA performance. Section IV summarizes the main characteristics of the amplifier, obtained from electrical simulations of the extracted layout. Finally, Section V gives some conclusions. II. LNA DESIGN Fig.1 shows a simplified schematic of the designed CMOS LNA. It uses an inductively degenerated commonsource cascoded topology, in which the source inductance is implemented by five paralleled low-loss bond wires. Fig.2(a) shows the equivalent small-signal circuit for the input stage of the LNA. The off-chip L-type network composed by and is designed to match a known source impedance to a smaller resistance value, , at the resonance frequency, 1. Sizing of and must also consider the parasitics of the selected QFN package. The inductance contributed by the series gate bondwire is represented by and denotes the sum of the parasitic capacitances due to the pad, , and the ESD protection circuit, . The integrated spiral coil has been modelled by an inductance in series with a resistance which accounts with its ohmic losses. The common source transistor M0 of Fig.1 has a transconductance , a gate-to-source capacitance and a gate resistance . The impedance at the drain of M0 is assumed to be negligible small by the effect of the cascode transistor M1. Also it is assumed that the Miller effect arising from the gate1. If is sufficiently large compared to the of the LNA input device, the impedance level at the LNA input becomes too low to be matched 50Ω only by employing a series inductance [1], [2]. For this reason, similar to other designs [2], the input impedance level of the proposed LNA exhibits a value lower than 50Ω (about 20Ω). Lead-frame Pad with ESD protection Off-chip matching network M0 M1 MB Bondwire Pad Figure 1. Schematic of the packaged LNA circuit with ESD Protection. Dec Cap 5X14 14x5 x4 x5 Lm Cm Lg Lbw Ld + Lead-parasitics Off-chip matching network + Lead-parasitics MCL Cm LmRs Rp ω0CmLm CpCgs Lbw Cp CPAD CESD Lg Rg gmCgs rg 1-4244-1342-7/07/$25.00 ©2007 IEEE 72 to-drain capacitance of M0 can be ignored. Finally, represents the degenerative source inductance, implemented by five paralleled bondwires – therefore, . Due to the low loss of the bondwires, no parasitic resistance is considered. The impedance seen at the left of the reference plane of Fig.2(a) can be written as , where and are given by, (1) where it is assumed that the impedance at the reference plane is purely resistive with resistance, (2) Combining with the integrated inductor and the parasitic resistances at the gate of M0, the simplified schematic of Fig.2(b) is obtained where (3) From Fig.2(b), the power matching condition at the input of the LNA can be found to be [3], (4) where denotes the cut-off angular frequency of the transistor. Note that since for the 0.13μm process is high, a low value of is required for input matching – this justifies the use of five bondwires in parallel. On the other hand, the resonance condition at the input stage of the LNA reads as [3]-[5], (5) which can be recursively solved to obtain in terms of (in this design, is set to 2.44Ghz). Taking advantage of the equivalent simplified schematic of Fig.2(a) and Fig.2(b), the magnitude of the output current of the input stage can be calculated, making use (4) and (5), as (6) which can be written as (7) where is given by Eq. (8), at the bottom of this page. Using (7), the transconductance of the LNA input stage is given by, (9) and the LNA voltage gain at the nominal operation frequency by (10) where is the impedance of the LC resonator circuit at the drain of M1 (see Fig.1). In the proposed design, the inductance of this tank circuit has been optimized to maximize the voltage gain of the LNA. Then, the capacitance has been tuned so that the tank resonates at the nominal operation frequency. Fig.3 depicts a small-signal circuit for the noise analysis of the proposed LNA. In this circuit, represents the noise power contribution of the source, is the noise contribuCgd Ls LsLbw 5⁄≈ Figure 2. (a) Small-signal circuit for the input stage of the LNA. (b) Equivalent simplified schematic. Ls Cgs Cp Cm Lbw Rgrg + gmvgs vin iout Zin Lg Lm Rs Rm Ls Lgeq,Cgs Rgeq, gmvgs iout vp (a) (b) 1 2 Zp Zp 2Req jω0Leq +Req Leq Req Rm ω0 2Cp 2Rm 21ω0 2CpLbw –() 2 + -------------------------------------------------------------------- = Leq Lbw Cpω0 2Lbw 2Rm 2 +()– ω0 2Cp 2Rm 21ω0 2CpLbw –() 2 + -------------------------------------------------------------------- = 1 Rm Rs 1ω0CmRs () 2 + ------------------------------------- = Zp Rgeq,Req RgrgReq ≈++= Lgeq,Leq Lg += Rgeq, gmLs Cgs ------------ωTLs ≡≈ ωTωT Ls ω0 1 Lgeq,Ls +()Cgs ------------------------------------------ = Lgω0 f 0 iout iout gmvgs gmvp 2jω0Rgeq,Cgs ------------------------------------- vp 2jω0Ls ----------------- == = iout vin 2ω0Ls --------------- ζRsLbw CpCm ,,,()= ζRsLbw CpCm ,,,() Gm iout vin -------- ζRsLbw CpCm ,,,() 2ω0Ls ---------------------------------------------- == AvGmZdjω0 ()= Zdjω0 () Cp Lg Lrg Ls Cgs gmvgs iout id 2 ig 2 vrg 2 Figure 3. Small Signal Circuit for Noise Figure Analysis of the proposed LNA with ESD Protection vRg 2 Rs vs 2 Rg Cm vs 2 vRg 2 (8)ζRsLbw CpCm ,,,()ω 0 21 ω0 ------ ω0CmLbw CpRsRm –()– ⎝⎠ ⎛⎞ 2ω0 2CmLbwRsCpCpRmRsCm ++() 2 + ⎩⎭ ⎨⎬ ⎧⎫ 1– ξ ω0 ------ ≡= 73 tion from the ohmic losses of the integrated coil, is the noise power due to the gate parasitic resistance of transistor M0, is the noise contribution of its channel and the underneath substrate resistance , and is the gate-induced current noise power. For the sake of simplicity, the noise contribution from the cascode stage has been neglected – it has low impact on the overall noise performance of the LNA. Assuming perfect power matching, the noise power contributions from the above sources to the LNA output current, can be calculated at the resonance frequency, (11) where and , , and are bias dependent parameters [3]. If the parasitic losses of the tank circuit at the drain of M1 are modelled by a parallel resistor at the frequency operation, its noise contribution to the LNA output noise current is, (12) From (11)- (12), the noise factor of the LNA is found by adding up the different noise power contributions (taking into account the correlation between the drain and gate-induced noise contributions [4]), and normalizing by the noise current due to . This gives, (13) where and is the correlation coefficient of the gate and drain noise sources [3]. III. ESD PROTECTION CIRCUITRY DESIGN In the LNA, the input and output terminals have been ESD-protected by means of dual-diode arrays as shown in Fig.1 [5]. Each array consists of 5 rows and 14 columns of diodes. Major issues on the design of this protection circuit have been the added shunt capacitance, , and the tolerable ESD current. At RF, capacitance becomes a low impedance path that will short the signal to ground, thus affecting the power gain and the noise figure of the LNA. Additionally, ESD protection structures, being extra devices to the circuit core, will cause noise coupling to the substrate through . Therefore, must be reduced as much as possible. In this design, the ratio is about 0.4 and the total shunt capacitance of the protection circuit is , giving an overall parasitic capacitance , including bond pads effects. Reducing the shunt capacitance runs against the need to sustain large ESD currents, as this improves with the size of the diodes. In this design, the sizing of diode arrays has been accomplished by exciting the LNA with HBM discharges as defined by the standard MIL-STD-883G [6]. As an example, Fig.4 shows the discharge current and the gate voltage of M0 when the LNA is stressed by a +2kV HBM signal. The breakdown voltage for this transistor is 2.7V, higher than the peak voltage at the gate of M0. Similar tests have been also applied for negative peak values and other voltages ranging from 0.5kV to 2kV. Table 1 summarizes the HBM ESD characteristics of the LNA, indicating the different satisfied classes. Together with the ESD protections, a low on-resistance grounded gate NMOS (ggNMOS) device, in the Fig. 1, is used for power clamping the supply node. IV. LNA PERFORMANCE Fig.5 shows the layout of the LNA which occupies and area of 0.7mm2, including pads, in a 0.13μm CMOS technology. The size of the input device M0 was chosen according to vrg 2 id 2 Rsub ig 2 inR s , 2Gm 2vs 2 4 ------------- Gm 2kBTRs == inR g , 2kBTRggm 2 ω0 2Cgs 2Rgeq,RgωTLs ++() 2 -------------------------------------------------------------------- = inr g , 2kBTrggm 2 ω0 2Cgs 2Rgeq,rgωTLs ++() 2 ------------------------------------------------------------------- = ind, 2γ α --- kBTgmkBTgmbs 2Rsub += ing, 21gmω0Ls () 2 + ω0Ls () 2 ------------------------------------kBTαδ 5gm ----------------- ⋅= gmbs ηgm =ηα δ γ Rd inR d , 24kBTR d ⁄= Rs F1Rgeq, 2 Rsξ2 -------------ω0 ωT ------ ⎝⎠ ⎛⎞ 24ωT 2Rg Rgeq,RgωTLs ++() 2 --------------------------------------------------- …++≈ 4ωT 2rg Rgeq,rgωTLs ++() 2 -------------------------------------------------- γ α --- ω0 2gmΨ…+++ ω0 2gmbs 2Rsub 1 Gm 2RdRs -------------------- ++ Ψ12cδ 5γ ----- α2δ 5γ --------- ++=c 5.999 5.9995 66. 0005 6.001 6.0015 6.002 6.0025 6.003 6.0035 6.004 x 10 -3 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Discharge Current [A] 5.999 5.9995 66. 0005 6.001 6.0015 6.002 6.0025 6.003 6.0035 6.004 x 10 -3 -1 -0.5 0 0.5 1 1.5 2 M0 G ate Voltage [V] time [sec] 2000V HBM TEST M0 GATE VOLTAGE HBM DISCHARGE CURRENT Figure 4. Discharge Current and Breakdown Voltage from 2kV HBM Test CESD CESD CESD CESD CESD Cgs ⁄ CESD 95fF= Cp240fF= TABLE 1. Human Body Model Tests HBM Voltage level Peak Current Rise Time Decay Time SatisfiedClass 500 V 315 mA 3.5 ns 150 ns Class Ib 1000 V 622 mA 2.5 ns 160 ns Class Ic 2000 V 1280 mA 2.5 ns 160 ns Class II MCL 74 [3] and employs a finger structure to reduce as much as possible its gate resistance. The size of M1 has been chosen to be the same as M0 and, in the layout, they have been placed next to each other [2]. This choice adequately reduces the Miller effect and also facilitates merging of the drain of M0 and source of M1, reducing the cascode node capacitance. Critical nodes of the circuit (including input and output pads) have been shielded from the substrate by metal plates to ground – this prevents the parasitic substrate resistance from degrading the . The layout includes metal-sandwich decoupling capacitors between the power supply and ground to stabilize the LNA biasing. Figs.6-7 have been obtained using electrical simulations from extracted layout, including foundry-provided estimations of the package parasitics and bondwire electrical characteristics. The input and output terminals of the LNA have been 50Ω matched with reflection coefficients S11 < -30dB and S22 = -30dB over the 2.4GHz ISM band. The measured power gain of the amplifier is shown in Fig.6. The gain has a peak value of 16.8dB at 2.46GHz and remains above 16.5dB over the ISM band. Fig.7 shows the noise figure of the LNA, revealing that it remains around 1.8dB in the band of interest. The proposed LNA achieves a reverse isolation value lower than -29dB and a stability factor of about 1.8. Finally, as Fig.8 shows, the achieved IIP3 is 1dBm, obtained by a two-tone test with 2MHz beat frequency in the 2.4GHz ISM band. V. CONCLUSIONS A 1.2V 2.4GHz 0.13μm CMOS LNA has been presented. The LNA is HBM ESD-protected ±2.0kV and achieves less than 1.8dB noise figure. The circuit uses 15 pins of a QFN24 package and occupies 0.7mm2. The current consumption of the LNA is about 4.4mA and obtains almost 17dB power gain. ACKNOWLEDGMENTS This work has been supported by the TIC2003-02355 and the TEC2006-03022 Projects. REFERENCES [1] P. Sivonen and A. Pärssinen, “Analysis and Optimization of Packaged Inductively Degeneration Common-Source Low-Noise Amplifier With ESD Protection,” IEEE Trans. On Microwave Theory and Techniques, vol. 53, No. 4, pp. 1304-1313, Apr.2005. [2] V. Chandrasekhar, C. M. Hung, Y. C. Ho, and K. Mayaram, "A packaged 2.4 GHz LNA in a 0.15um CMOS process with 2kV HBM ESD protection," presented at the 28th European Solid-State Circuits Conference, 2002 (ESSCIRC 2002). [3] T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits (2nd Edition),” Cambridge University Press, Cambridge (UK), 2004. [4] J. Janssens and M. Steyaert, “CMOS Cellular Receiver Front-Ends, from Specification to Realization,” Kluwer Academic Publisher, Dordrecht (The Netherlands), 2002. [5] P. Leroux and M. Steyaert, “LNA-ESD Co-Design for Fully Integrated CMOS Wireless Receivers”, Springer, Dordrecht (The Netherlands), 2005. [6] Department of Defense, ”MIL-std-883g Test Method Standard - Microcircuits,” Feb. 2006. Fi g ure 5. La y out of the LNA. NF Fi g ure 6. Power Gain. 11.5 22.5 33.5 4 x 10 9 0 2 4 6 8 10 12 14 16 18 [dB ] Frequency [Hz] Power Gain 11.5 22.5 33.5 4 x 10 9 1 2 3 4 5 6 7 8 [dB] Frequency [Hz] Noise Figure -30 -25 -20 -15 -10 -5 0 5 -80 -60 -40 -20 0 20 40 Input Power [dBm] Output Power [dBm] 3rd Order Input Referred Intercept Point 1dB/dB 1st Order Harmonic 3dB/dB 3rd Order Harmonic Figure 7. Noise Figure. Figure 8. Two-Tone IIP3 measure. 75