On he Sui abili y and De elopmen o Layou Templa es o
Analog Layou Reuse and Layou -Awa e Syn hesis
Ra ael Cas o-López, F ancisco V. Fe nández, and Ángel Rod íguez Vázquez
Ins i u o de Mic oelec ónica de Se illa, Cen o Nacional de Mic oelec ónica
Edi icio CICA. A da. Reina Me cedes s/n, E-41012- Se illa, Spain
Tel.: +34 955 056 666. Fax: +34 955 056 686
E-mail: Ra ael.Cas[email p o ec ed]
ABSTRACT
Accele a ing he syn hesis o inc easingly complex analog in eg a ed ci cui s is key o b idge he widening gap be ween
wha we can in eg a e and wha we can design while mee ing e e - igh ening ime- o-ma ke cons ain s. I is a well-known
ac in he semiconduc o indus y ha such goal can only be a ained by means o adequa e CAD me hodologies,
echniques, and accompanying ools. This is pa icula ly impo an in analog physical syn hesis (a.k.a. layou gene a ion),
whe e la ge sensi i i ies o he ci cui pe o mances o he many sub le de ails o layou implemen a ion (de ice ma ching,
loading and coupling e ec s, eliabili y, and a ea ea u es a e o u mos impo ance o analog designe s), ende comple e
au oma ion a uly challenging ask. To app oach he p oblem, wo di ec ions ha e been adi ionally conside ed,
knowledge-based and op imiza ion-based, bo h wi h hei own p os and cons. Besides, ecen ly epo ed solu ions o ien ed
o speed up he o e all design low by means o euse-based p ac ices o by cu ing o ime-consuming, e o -p one spins
be ween elec ical and layou syn hesis (a echnique known as layou -awa e syn hesis), ely on a ou s andingly apid ye
e icien layou gene a ion me hod. This pape analyses he sui abili y o p ocedu al layou gene a ion based on empla es
(a knowledge-based app oach) by examining he equi emen s ha bo h layou euse and layou -awa e solu ions impose,
and how layou empla es ace hem. The abili y o cap u e he know-how o expe ienced layou designe s and he
u na ound imes o layou ins ancing a e conside ed main compa a i e aspec s in ela ion o o he layou gene a ion
app oaches. A discussion on he bene i -cos ade-o o using layou empla es is also included. In addi ion o his analysis,
he pape del es deepe in o sys ema ic echniques o de elop ully eusable layou empla es o analog ci cui s, ei he o
a change o he ci cui sizing (i.e., layou e a ge ing) o a change o he ab ica ion p ocess (i.e., layou mig a ion). Se e al
examples implemen ed wi h he Cadence’s Vi uoso ool sui e a e p o ided as demons a ion o he pape ’s con ibu ions.
Keywo ds: Physical Syn hesis, Design Reuse, Layou -Awa e Syn hesis, P ocedu al Layou Gene a ion.
1. INTRODUCTION
Elec onic Design Au oma ion (EDA) is a key ac o o as and e icien de elopmen o complex elec onic designs.
Nowadays, when a educ ion o he design p oduc i i y –d opping behind he a ailable capaci y o in eg a e due o
inc easingly igh p oduc - o-ma ke equi emen s and design complexi y– is jeopa dizing he phenomenal e olu ion o he
semiconduc o indus y [1], EDA is, p obably, mo e u gen ly equi ed han e e . Unlike digi al ci cui s, whe e, e en hough
being a om he ‘push- he-bu on-and- o ge -i ’ e a, he e is a conside able s eam o EDA esou ces a all s ages o
design, he analog domain is pa icula ly impac ed by a lack o EDA ools and me hodologies ha may help closing he gap
be ween p oduc i i y and complexi y. The e y na u e o analog ci cui s (much mo e he e ogeneous, hie a chically loose,
and ex emely sensi i e o di e en sou ces o ‘noise’, o name bu a ew di e ences wi h digi al ci cui s) make design a
nea ly handic a p ocess and au oma ion, he e o e, becomes much mo e di icul .
Keeping he ack o digi al design au oma ion, he pa adigm o euse-based design has been ecen ly p oposed as a
complemen a y solu ion o speed up he analog design p ocess [2]. Reuse, in his con ex , is he abili y o using p e ious
design knowledge, expe iences, and da abases o implemen a di e en design, pe haps in a di e en ab ica ion p ocess.
Analog euse, howe e , needs a di e ing se o solu ions han hose applied in he digi al domain, jus o he same easons
ha digi al and analog au oma ion ma u i y le els di e . Pa icula ly impo an is he c ea ion o uly eusable ci cui
layou s, o his is one o he mos in ensi e and ime-consuming design asks.
VLSI Ci cui s and Sys ems II, edi ed by José Fco. López, F ancisco V. Fe nández,
José Ma ía López-Villegas, José M. de la Rosa, P oceedings o SPIE Vol. 5837
(SPIE, Bellingham, WA, 2005) 0277-786X/05/$15 · doi: 10.1117/12.607932
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Ano he complemen a y, no el app oach o boos he analog design p ocess ocuses he issue o a oiding o comple ely
emo ing any i e a ions be ween elec ical and physical syn hesis. Such i e a ions do adi ionally ake place when, a e
he pe o mance o he ci cui , including he una oidable layou -induced pa asi ics, is e i ied, one o mo e unaccep able
de ia ions om he ini ially expec ed pe o mance ha e been ound. This modus ope andi has been so a conside ed as a
s anda d in analog design. The no el app oach, known as pa asi ic-awa e syn hesis [3] [4], consis s in ully o pa ially
embedding layou syn hesis in elec ical syn hesis (also known as ci cui sizing), so ha de ailed physical in o ma ion can
be conside ed a in e media e s eps o said elec ical syn hesis. A much mo e comple e app oach conside s no also he
inclusion o pa asi ic de ails, bu also he in oduc ion o geome ic de ails. By doing so, geome ic aspec s o he ci cui ’s
layou , such as he occupied a ea, can be eliably op imized du ing he elec ical syn hesis. This app oach is e e ed he e
as geome ically-cons ained elec ical syn hesis. On he o he hand, as geome ic ea u es ha e in luence upon he alue
o he layou -induced pa asi ics (e.g., a ying he numbe o olds o a ansis o s changes he alue o he di usion a eas
and, he e o e, al e he alue o he di usion pa asi ic capaci ances), bo h echniques should simul aneously be applied;
elec ical syn hesis is hen known as layou -awa e syn hesis [5].
These wo design me hodologies, layou euse and layou -awa e syn hesis, impose i s own se o equi emen s on layou
gene a ion. This pape add esses he issue o inding ou which is he mos app op ia e physical syn hesis me hod ha bes
deals wi h layou euse and layou -awa e syn hesis. The pape is o ganized as ollows. Sec ion 2 and Sec ion 3 analyze he
equi emen s ha he euse-based design pa adigm and he layou -awa e syn hesis me hodology espec i ely impose on
physical syn hesis. Sec ion 4 e iews exis ing app oaches o layou syn hesis and explo es he sui abili y o layou
empla es in he ligh o such e iew. A me hodology o layou empla e de elopmen is desc ibed in Sec ion 5 and se e al
examples a e p esen ed in Sec ion 6. A summa y discussion on he bene i s and d awbacks o layou empla es is gi en in
Sec ion 7. Las , conclusions a e d awn in Sec ion 8.
2. THE REQUIREMENTS OF ANALOG LAYOUT REUSE
F om he layou poin o iew, design euse implies wo di e en scena ios:
(a) Reuse o he ci cui layou da abase o changes in he ci cui pe o mance speci ica ions. This concep o design
euse has one limi a ion: he speci ica ions changes mus be such ha he new speci ica ions can be add essed by
using he same ci cui a chi ec u e/ opology. This does no mean, howe e , ha he equi ed changes ansla e in o
mino adjus men s a he layou le el a all [6]. Qui e he opposi e, speci ica ions changes, hough wi hin he ci cui ’s
achie able beha io , may ansla e in o d as ic modi ica ions o he ci cui de ice sizes and biasing condi ions, and,
he eby, in he ci cui layou . Wha e e he layou gene a ion app oach is used, i has o sol e he p oblem o how
o accommoda e hese speci ica ion changes. In his scena io, layou euse is called layou e a ge ing as he ci cui
a ge pe o mance is modi ied and he p e ious wo king ci cui a chi ec u e/ opology is eused.
(b) Reuse o he ci cui layou da abase o a change o he ab ica ion echnology. In his case, layou euse is known
as layou mig a ion, as he layou da abase is mo ed om he echnology i was designed o , o a di e en goal
echnology, pe haps om a di e en ound y1.
To euse a ci cui layou manually, ei he o a change in he de ice sizes o o a change o he ab ica ion p ocess, could
become a qui e labo ious and slow ask. Ac ually, he g ea speci ici y o analog designs is he main ac o ha makes di ec
layou euse u e ly un easible. To ac ually unde s and how a eusable layou can be c ea ed, i is i s essen ial o g asp he
implica ions ha e a ge ing and mig a ion ha e on au oma ed layou syn hesis.
2.1 Layou e a ge ing
Layou e a ge ing, pe o med when any o he ci cui de ices and/o any o he biasing condi ions need o be modi ied o
add ess he changes in he ci cui pe o mance speci ica ions, en ails he ollowing wo di e en aspec s: i s , se e al
cha ac e is ics o analog layou quali y may esul spoiled, so hey ha e o be ca e ully ea ed and main ained; second, he
layou has o emain complian wi h he p ocess design ules. This la e aspec is co e ed in Sec ion 2.2. The ollowing
analyzes he o me aspec in mo e de ail.
1. In a sense, layou e a ge ing can be seen as a componen o layou mig a ion, as changing he ab ica ion p ocess, while y-
ing o ob ain he same ci cui beha io , would likely equi e o adap he layou o new de ice sizes as well (ac ually wha lay-
ou e a ge ing aims a ). Ne e heless, layou mig a ion will be conside ed he e, o he sake o simplici y, as a s and-alone
aspec o analog layou euse, meaning only he adap a ion p ocess o he layou da abase (i.e., da abase mig a ion), and no
o he ci cui de ice sizes, o ano he ab ica ion p ocess, wi h di e en design ules and mask laye s.
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The analog layou cha ac e is ics ha need close a en ion du ing he cou se o layou e a ge ing a e:
1. De ice misma ch. All de ices in an IC occupy he same piece o silicon, he e o e su e ing om he same
manu ac u ing impe ec ions. The e a e de ices which a e speci ically cons uc ed o keep a known cons an a io
be ween hem and hey a e hus called ma ched de ices. Six majo layou geome ic ac o s can a ec he ma ching
o iden ical de ices [7]-[12]: size, shape, symme y, sepa a ion, o ien a ion, and bounda y. To minimize he e ec
o de ice misma ch, he layou designe ypically ollow se e al guidelines [7] [10], such as he use o common-
cen oid s uc u es, which should be p ese ed as layou e a ge ing is pe o med.
2. Loading and coupling e ec s. The physical na u e o ma e ials used in he ab ica ion p ocess in oduces
capaci i e and esis i e pa asi ic elemen s2. Howe e , he amoun o e o needed o con ol hese pa asi ic e ec s
is indeed conside able since ex emely low-le el geome ic de ails o he layou o indi idual de ices can ha e a
majo impac on he ci cui pe o mance. Fu he mo e, pa asi ic elemen s canno be ully p edic ed ea ly in he
design p ocess, because he layou is no comple e ye . O e -es ima ion o he pa asi ics esul s in was ed a ea and
powe , and unde -es ima ion leads o speci ica ion non- ul illmen . I is hen c ucial ha pa asi ic e ec s ha e o be
aken in o accoun du ing he design p ocess3 and ha he selec ed layou syn hesis me hod p o ides ways o
minimize hei impac . Layou can also in oduce unexpec ed signal coupling be ween he ci cui nodes, which may
injec unwan ed elec ical noise and e en des oy he ci cui s abili y due o unin ended eedback [7]. This capaci i e
coupling e ec , known as c oss alk, may appea be ween wo wi es unning in pa allel o e a long dis ance, o in
wo wi es c ossing a di e en le els. Capaci i e and esis i e coupling can also appea by means o subs a e
coupling [13].
3. Reliabili y. This cha ac e is ic e e s o he o al ime ha an IC can p o ide pe ec ope a ion and depends, a a high
ex en , on he quali y o he IC layou . Fo ins ance, p e en ing a se ious sou ce o eliabili y loss like
elec omig a ion om occu ing, can be a ained by p ope ly adjus ing he wi e wid h. Con ac and ia holes,
making he cu en low om geome ies on di e en laye s, should also be adjus ed o minimize he esis ance o
such cu en low, and so mus done be du ing layou e a ge ing.
4. A ea occupa ion. Minimizing he a ea occupa ion is usually a design conce n in analog ci cui design since i may
lead o mo e in eg a ed unc ionali y and o e en ually lowe chip ab ica ion cos s. A aining a compac layou wi h
minimal unused a ea can also imp o e he chip a ea usage. The e o e, when layou e a ge ing is equi ed and
changes in he ci cui pa ame e s esul in changes in he ci cui layou (small o la ge), bo h a ea and unused a ea
should be kep as small as possible. Ano he impo an ac o o make he assembly o se e al ci cui layou s easie ,
is he aspec a io (i.e., ) o he ci cui layou .
All he cha ac e is ics desc ibed abo e a e c i ical o analog layou design and, in his sense, a se o ules and guidelines
should be ollowed o enhance he quali y o he layou . The ele an conclusion is, ac ually, ha wha e e he me hod
selec ed o c ea e he layou - eusable analog block, i has o e icien ly cope wi h all hese no ewo hy issues.
2.2 Layou mig a ion
Ci cui layou s a e c ea ed by a anging a se o geome ic shapes, each shape made o a pa icula mask laye (e.g.,
polysilicon o di e en me al le els), o o m he de ices (e.g., ansis o s, esis o s, capaci o s) p esen in he ci cui
de ice-le el desc ip ion. Each ab ica ion p ocess s ipula es i s own se o mask laye s and i s own se o layou design
ules, acco ding o which all he ci cui ’s de ices and in e connec ions ha e o be laid ou . Suppose a ci cui layou made
on one echnology, . The main p oblems a ising when ying o po a layou om said echnology o a di e en , goal
echnology, , a e [14]:
1. Va ia ion o he geome ic p ocess pa ame e s. Found ies p o ide se s o design ules and guidelines which
encapsula e he ab ica ion geome ic cons ain s (e.g., like he minimum ea u e size), and which he ci cui layou
mus comply wi h. When he echnology changes o e en when he same echnology e ol es, hese ules and
guidelines may also change. A iola ion o any o hese ules may lead o comple e in alidi y o he ci cui layou .
2. Va ia ion o he elec ical p ocess pa ame e s. Elec ical p ocess pa ame e s de ine he elec ical cha ac e is ic
o he p ocess laye ma e ials. Typical examples a e he a ea and pe ime e capaci ance o poly-insula o -poly
2. A su icien ly high equencies, induc i e e ec s a ise as well.
3. A ce ain phases o he design p ocess i is possible o oughly es ima e he pa asi ic elemen s ( ia a ea and pe ime e meas-
u emen s) bu his es ima ion is no su icien . Tha is why pa asi ic-awa e syn hesis has been p oposed.
wid h heigh ⁄
T1
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capaci o s, he shee esis ance o he poly mask laye , he maximum cu en densi y o me al laye s, e c.
Calcula ions made in echnology may be o ally imp ac ical in echnology .
3. Va ia ion o mask laye s. The se o a ailable mask laye s may a y om o . Typical p oblems a e:
•Numbe o ou ing laye s: i is qui e common ha and ha e a di e en numbe o me al ou ing laye s
(me al-one, me al- wo, me al- h ee, and so on). The e a e no se ious p oblems when has less ou ing laye s
han , since e e y wi e in has a coun e pa in . On he o he hand, i.e., when has less ou ing lay-
e s, i becomes impossible o pe o m he layou mig a ion, unless he o iginal layou does no exhaus all he
ou ing laye s, and i uses as many (i no less) ou ing laye s as hose a ailable in .
•De ice mask s uc u e: om one echnology o ano he , he way o s yle a omic de ices a e laid ou may also
change. Fo ins ance, NMOS ansis o s in CMOS p ocesses ypically need a P+ di usion mask laye . In many
p ocesses, i is no necessa y o explici ly d aw his laye , whe eas, in o he p ocesses, i is equi ed. The p ob-
lem hen a ises when mo ing he NMOS layou om he o me o he la e p ocess.
As wi h he layou e a ge ing issues, he layou - eusable analog block mus be c ea ed so ha layou mig a ion can be
seamlessly and apidly pe o med.
3. THE REQUIREMENTS OF LAYOUT-AWARE SYNTHESIS
As explained ea lie , he unde lying idea behind layou -awa e syn hesis is o b ing layou gene a ion in o he e y sizing
p ocess, so ha ci cui au oma ed sizing is ca ied ou wi h enough in o ma ion abou layou -induced pa asi ics and
geome ic ea u es (such as a ea occupa ion) o he e en ually implemen ed layou . In his way, ci cui sizing yields a
solu ion ha is obus agains layou -induced deg ada ion e ec s and ha ul ils a numbe o use -de ined geome ic goals,
among hem a ea minimiza ion being he mos impo an .
The low o layou -awa e syn hesis is depic ed in Fig.1.
The sizing p ocess, ca ied ou ei he by means o a
knowledge-based o an op imiza ion-based app oach
[6], begins wi h he ci cui pe o mance speci ica ions
(de ined he e as es ic ions, in ol ing inequali ies,
such as o , and objec i es, such as powe
consump ion minimiza ion). Then, ei he h ough a
mapping o he pe o mance speci ica ions o de ice
sizes (knowledge-based sizing) o h ough an i e a i e
explo a ion o a p e-de ined design space
(op imiza ion-based sizing), he sizing engine p o ides
an in e media e ci cui sizing. A e wa ds, geome ic
pa ame e s (e.g., he pa ame e con olling he numbe o inge s o a olded MOS ansis o s o one o he sides o a
ec angula capaci o whose capaci y has been gi en by he sizing engine) mus be decided conside ing bo h a ea
minimiza ion and a se o use -de ined geome ic objec i es such as he aspec a io o he maximum layou wid h o
heigh 4. This decision-making p ocess equi es ha he a angemen o he componen s o he layou (known as
loo planing) as well as he implemen a ion s yle in which each componen will be laid ou , mus be known be o ehand.
Wi h such in o ma ion, he ask o inding adequa e geome ic pa ame e alues o minimize a unc ion o he ci cui wid h
and heigh , known as loo plan sizing p oblem can be ackled [15]. Di e en app oaches exis o sol e his p oblem, bu
all ealizable choices a e based on a slicing-s yle layou loo plan. O he wise, he ime equi ed o sol e he p oblem can
be una o dable, since i becomes a NP-comple e p oblem [15].
Once geome ic pa ame e s ha e been decided, he inclusion o pa asi ics can be ca ied ou ei he h ough pa asi ic
modeling o h ough layou gene a ion and subsequen layou ex ac ion. Accu a e es ima ion o pa asi ics equi es
knowing he ci cui layou in ull de ail, which in ol es ob aining in o ma ion on he implemen a ion s yle o each de ice,
he in e connec s uc u e, as well on hei ela i e posi ioning (placemen ). Fu he mo e, his layou knowledge may be
equi ed o be gene a ed o e ie ed a each i e a ion o an op imiza ion-based sizing p ocess. The e o e, whiche e he
me hod used o ob ain his knowledge, i mus be apid enough o p e en ci cui sizing om being p ohibi i ely long. Wi h
4. I he ask o inding which alues o he geome ic pa ame e s bes op imize hese geome ic ea u es is comple ely le o he
sizing engine, he mapping o explo a ion may become o e -cons ained and will possibly ake much longe .
T1T2
T1T2
T1T2
T1
T2T1T2T2
T2
Figu e 1: Layou -awa e sizing low.
SIZING ENGINE
PARASITIC
ESTIMATION
LAYOUT TEMPLATE
INSTANCING
ADD
PARASITICS
DECIDE
GEOMETRIC
PARAMETERS
PERFORMANCE
SPECS
GEOMETRIC
SPECS
INTERMEDIATE
CIRCUIT SIZING
PERFORMANCE
EVALUATOR
< ≥
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pa asi ics accu a ely es ima ed and added o he ci cui ne lis , an e alua ion o he ci cui pe o mance is ca ied ou o
quan i y how he ci cui deals wi h ini ial speci ica ions. In case he esul ing pe o mance is no accep able, he sizing
p ocess is e-en e ed, ei he guided wi h con e gence c i e ia [3] o by simply mo ing o ano he poin o he design space
i using op imiza ion-based sizing [14].
Se ing aside he ac ha he op imiza ion engine has o be able o inco po a e design knowledge and use i du ing he sizing
p ocess, wo equi emen s can be d awn om he p e ious analysis. Fi s , de ailed in o ma ion on he ci cui layou
implemen a ion mus be equi ed ea ly in he sizing p ocess. Second, layou gene a ion mus be a he apidly accomplished
wi h espec o he sizing p ocess i sel .
4. ANALYSIS OF LAYOUT SYNTHESIS APPROACHES
The ollowing e iew is by no means in ended o be exhaus i e ( he in e es ed
eade is e e ed o excellen e iews on analog layou gene a ion in [6] and [7]).
I s sole objec i e is o ind ou which o he ull-cus om layou me hods is bes sui ed
o deal wi h he equi emen s o analog layou euse and layou -awa e syn hesis
explained abo e.
A ypical low o he ull-cus om layou p ocess o analog ci cui s is depic ed in
Fig.2. The inpu o he layou p ocess is a ci cui desc ip ion, ypically a comple ely
sized ne lis , wi h all de ice sizes and geome ical pa ame e alues. Technological
in o ma ion is also used all h oughou he layou gene a ion.
The i s s ep consis s in he gene a ion o all he componen s o he ci cui . A he
cell le el (e.g., an ope a ional ampli ie ), hese componen s a e g oups o one o
mo e de ices (e.g., mi o o cascode CMOS s uc u es) known in he li e a u e as
modules, s uc u al en i ies, o mac o-cells. Each mac o-cell can be gene a ed in
se e al ways, all elec ically equi alen , called geome ic a ian s (e.g., a ansis o
di e en ial pai may be laid ou in a 1-dimensional o 2-dimensional common-
cen oid s yle) [17]. A highe le els, he layou componen s can be unc ional
blocks as well, which ha e also been gene a ed by using de ice g oupings a he cell le el. The nex s ep is he placemen
o e e y componen , conside ing a wide se o analog cons ain s o ob ain a be e esul . Then, in he ou ing phase, he
placed componen s a e in e connec ed, in acco dance wi h he ci cui connec i i y p o ided ea lie in he low. A e all
componen s ha en been ou ed, a compac ion o he whole layou may ake place, bu i also can be ega ded as an in eg al
pa o he placemen and ou ing phases.
Me hods o gene a ion o ull-cus om
analog layou ocus ei he on au oma ing
one o mo e o he di e en s eps in ol ed
in he p ocess, o on p o iding he layou as
a whole single p ocess. Wha e e he ocus,
hese me hods can be b oadly classi ied,
like elec ical syn hesis, in o wo di e en
app oaches: op imiza ion-d i en
app oaches and knowledge-d i en
app oaches [17]. Fig.3 shows a axonomy
o hese wo app oaches.
4.1 Op imiza ion-d i en app oaches
Op imiza ion-d i en app oaches aim a au oma ically gene a ing he layou while s i ing o minimize he layou -induced
e o s by means o an op imiza ion algo i hm. Following a digi al-like app oach, placemen and ou ing s ages o he layou
gene a ion a e ca ied ou by such an op imiza ion p og am acco ding o a ce ain cos unc ion. This cos unc ion ypically
conside s minimiza ion o some design aspec s such as a ea and ne leng h, while penalizing iola ion o some analog
design cons ain s, such as de ice misma ch, loading capaci ances, and c oss alk. The quali y o hese op imiza ion-d i en
ools is mainly de e mined by he e iciency o he op imiza ion algo i hm and he se -up o he cos unc ion.
Depending upon he way o de i ing he cos unc ion and dealing wi h cons ain s on analog pe o mance, wo ca ego ies
a e usually conside ed [17]. The i s g oup is composed o heu is ic-based app oaches. Layou -induced e o s a e aken
Figu e 2: Typical analog layou
design low.
MACRO-CELL
GENERATION
PLACEMENT
ROUTING
LAYOUT
COMPACTION
COMPLETELY
SIZED NETLIST
MACRO-CELL
IDENTIFICATION
TECHNOLOGICAL
DATA
F
igu e 3: Taxonomy o CAD ools o layou gene a ion o analog ci cui s.
FULL-CUSTOM
OPTIMIZATION-BASED
KNOWLEDGE-BASED
RULE-BASED
TEMPLATE-BASED
DESIGN-BY-
EXAMPLE
PROCEDURAL
GENERATOR
HEURISTIC-BASED
PERFORMANCE-DRIVEN
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in o accoun by classi ying ne s acco ding o hei sensi i i y and ci cui unc ion. Al hough op imizing he ci cui
pe o mance, hese app oaches do no use a sys ema ic way o gene a e ne sensi i i ies and o handle pe o mance
cons ain s. The e o e, hey may yield solu ions ha do no mee pe o mance cons ain s a e he layou is e i ied. Time-
consuming layou -ex ac ion- e i ica ion spins may hus be necessa y. Besides, he e is no way o iden i y which pa asi ics
a e mos ly deg ading he ci cui beha io and, he e o e, o know which changes a e necessa y. Examples o hese ools a e
ILAC [18], and KOAN/ANAGRAMII [19]. Al e na i e app oaches o placemen o MOS ansis o s di ide his s ep in o
de ice s acking and s ack placemen . This is done by using se e al heu is ic algo i hms ende ing he ci cui as di usion
g aphs o connec ed d ains and sou ces.
A no able imp o emen is accomplished by he o he g oup o app oaches, whose ope a ion is based on pe o mance-
d i en op imiza ion o he ci cui layou (also known as cons ain -d i en op imiza ion). Unlike heu is ic app oaches,
whe e no quan i ica ion o he pe o mance deg ada ion is done, pe o mance-d i en ools y o measu e he layou -
induced deg ada ion on he ci cui pe o mance and keep i below desi ed ma gins. In his way, he impac o each layou
pa asi ic is weighed ou acco ding o i s e ec on he ci cui pe o mance [20]. The i s con ibu ions epo ed we e o
pe o m channel ou ing [21]. In hese wo ks, he e ec o layou pa asi ics a e modeled by using sensi i i ies and, hen,
he pe o mance cons ain s o he ci cui a e mapped o a se o cons ain s on he layou pa asi ics. La e app oaches
showed ha his in e media e mapping could be skipped [16] [17].
The main ad an age o op imiza ion-d i en ools is hei gene ali y: in p inciple, hey can be applied o any analog o
mixed-signal ci cui . The d awbacks, howe e , a e he complexi y o he op imiza ion p oblem (e en o he simples
p oblems, hese a e NP-ha d p oblems), he di icul y o he cos - unc ion se -up, and he la ge u na ound ime.
4.2 Knowledge-d i en app oaches
These app oaches y o s o e and exploi he knowledge equi ed o c ea e he analog layou . This knowledge e e s o he
p ocedu es ha expe layou designe s use o imp o e he quali y o he layou , and spans a wide a ie y o echniques,
om speci ic placemen s a egies used o imp o e de ice ma ching (e.g., complex common-cen oid a ays) and minimize
he layou a ea, o ou ing echniques o minimize he loading e ec s. Since his speci ic knowledge is o be s o ed and used
whene e necessa y, his app oach is mainly in ended o euse p e ious expe iences o expe layou designe s.
Knowledge-d i en app oaches a e speci ically de eloped o gene a e he layou o ixed a chi ec u es/ opologies. This
means ha he inpu in o ma ion is no only a ne lis o he sized ci cui (see Fig.2), bu also a desc ip ion o he layou i sel
as well as aluable layou knowledge. Knowledge-d i en layou gene a ion is no as complex as he op imiza ion-d i en
one, as placemen and/o ou ing a e speci ied in ad ance.
The e a e wo ypes o knowledge-d i en app oaches, namely ule-based and empla e-based app oaches. Rule-based
app oaches s o e he layou knowledge in a cus omizable ule se o be obeyed du ing layou placemen and ou ing. A clea
example o his app oach is ALSYN [22]. Al hough e e y use can adap he se o con olling ules o his/he own needs,
he quali y o he layou la gely depends on he quali y o his se o ules. Besides, he ules a e di icul o o mula e i
hey a e in ended o be gene al and con ex -independen .
Templa e-based ools a e also de eloped o bes use layou designe s’ expe ise. The unde lying idea is o cap u e his
expe ise in a pa e n o empla e ha speci ies all necessa y de ice- o-de ice and de ice- o-wi e spa ial ela ionships.
Besides, i mus cap u e analog speci ic cons ain s like symme y, de ice ma ching, and pa asi ic minimiza ion. To
gene a e a ci cui layou om his empla e, which is called layou ins ancing, i is equi ed o p o ide he alue o a se o
elec ical and geome ic pa ame e s (e.g., he ansis o wid h and leng h, o he maximum cu en densi y allowed o low
on a ce ain mask laye ). The empla e can be gene a ed ei he in a p ocedu al o a g aphical way. The la e way consis s
in cap u ing he layou knowledge om a empla e p e iously laid ou by an expe designe . A ypical example is he
design-by-example app oach p esen ed in [23]. The example p o ided by he expe cap u es his/he knowledge
( ega ding de ice placemen , ou ing wi e ajec o ies, ma e ial ypes and wid hs, and posi ion o mac o-cell e minals). To
gene a e a new layou , i is necessa y o p o ide he equi ed elec ical pa ame e s o each de ice, he se s o ma ched
de ices, and he geome ic cons ain s (e.g., a desi ed aspec a io). S a ing om a ixed de ice placemen , he ool de i es
all possible layou s (eme ging om all possible de ice layou s, e.g., om di e en alues o he numbe o uni a y
componen s o a MOS ansis o ). Then, an exhaus i e op imiza ion is execu ed o ind he one ha sa is ies he speci ied
geome ic cons ain s. Finally, ou ing and compac ion phases a e ca ied ou . This app oach can p oduce good compac
layou s in a mode a e amoun o CPU ime (a ound 37 minu es o a 24-de ice ope a ional ampli ie ), bu he layou
empla es ha e o be upda ed o each new ab ica ion p ocess, which equi es addi ional e o .
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Cap u e o layou knowledge h ough empla es can also be done by using p ocedu al gene a o s [24]. The mechanisms
o desc ibe hese p ocedu al gene a o s can be speci ic layou languages such as BALLISTIC [25] and MSL [26], o
common sp eadshee in e aces [27], bu bo h app oaches a e in ended o code he analog-speci ic layou knowledge in o
he so wa e i sel . Al hough he coding e o can be high, his e o needs no longe be was ed when he de ice sizes and/
o he ab ica ion p ocess a e changed. The p ocess simply consis s in he compila ion o he coded empla e (when
necessa y) and he upda e o he de ice sizes as well as he ab ica ion p ocess pa ame e s.
4.3 Au oma ed layou gene a ion o layou euse and layou -awa e syn hesis
Ha ing all his in mind, he mos sui able layou gene a ion app oach o bo h layou euse and layou -awa e syn hesis u ns
ou o be he knowledge-d i en gene a ion o p ocedu al layou empla es. The easons suppo ing his conclusion a e he
ollowing [28] [29]:
•Layou empla es a e e y e icien a handling design expe ise. Analog layou e a ge ing, as explained in Sec ion
2.1, equi es imposing se e al layou cons ain s based on accumula ed design knowledge. These cons ain s canno be
easily conside ed by adi ional placemen and ou ing algo i hms. On he con a y, layou empla es can be de ined, as
shown in Sec ion 5, as s uc u es whe e use -de ined cons ain s a e easily s o ed.
•Layou empla es can be s aigh o wa dly po ed. Full echnology independence can be achie ed by coding he p oce-
du al empla e gene a o using symbolic p ocess pa ame e s and mask laye s. The e o e, nei he scaling me hods no
complex compac ion echniques would be equi ed o be applied. The main ad an age o p ocedu al layou wi h
espec o scaling and compac ion me hods is i s highe p ecision and speed, espec i ely.
•Layou empla e ins ancing ime is compa a i ely much smalle han layou gene a ion wi h op imiza ion-d i en
app oaches. Fo ins ance, he ools epo ed in [17] yield CPU imes om 550 o 800 seconds o opamp-like ci cui s,
while ins ancing hei layou empla es would ake no mo e han 0.01 seconds o CPU ime [14]. This allows sho en-
ing he o e all design ime while managing he inhe en complexi y o analog ci cui s.
•Layou empla es ease placemen . The layou gene a ion p ocedu e is simpli ied because he posi ions o he blocks in
he empla e a e s o ed acco ding o p e-de ined ela ionships embodying cons ain s om he layou expe ha
enhances he layou quali y. Op imiza ion-d i en me hods y o a ain he same quali y a he expense o ime-con-
suming algo i hmic echniques. Ha ing he placemen hus de ined (especially i , as i will be explained below, i ol-
lows a slicing s yle app oach), also eases he loo plan sizing p oblem, since bina y slicing ees can be eadily buil
and i is hen possible o eckon e e y building block’s shape o minimize ce ain geome ic unc ion, such as he a ea
occupa ion o he aspec a io.j
•Layou empla es pe mi sea ching o op imal block pa ame e s while e ealing he knowledge needed o es ima ion
o layou pa asi ics in pa asi ic-awa e sizing. As said in Sec ion 3, i u ns ou c i ical o educe he CPU ime o lay-
ou gene a ion. Heu is ic-based o pe o mance-d i en app oaches a e cu en ly oo slow o layou gene a ion o be
called wi hin he ci cui sizing p ocess [17]. Conside , o ins ance an op imiza ion-based whe e ypically a ew hou-
sand i e a ions a e equi ed. Neglec ing he CPU ime o he es o p ocesses (simula ion, ex ac ion, and so on), i
would ake se e al days o comple e he pa asi ic-awa e ci cui sizing, which can be compa able (i no wo s ) o man-
ual design. Using p ocedu al layou empla e allows, on he o he hand, as gene a ion o ci cui layou since no ime-
consuming op imiza ion algo i hms a e in ol ed. Fu he mo e, i is possible o ha e a comple e and de ailed desc ip-
ion o he ci cui layou (placemen and ou ing cha ac e is ics as well) wi hou ac ually ins ancing i , o he empla e
is a ully pa ame e ized objec , he pa ame e s depending on design a iables and echnological cons an s. The e o e,
modeling layou pa asi ics becomes also possible.
Despi e hese impo an bene i s, p ocedu al me hods ha e wo d awbacks, namely cos – he e o o gene a e e e y new
empla e may la gely exceed he e o o c ea e, manually, he co esponding ull-cus om layou – and lexibili y –la ge
changes o he ci cui pe o mance may lead o a d ama ic deg ada ion o he layou egula i y, aspec a io, and a ea usage.
Bo h issues will be discussed in Sec ion 7.
5. A METHODOLOGY FOR LAYOUT TEMPLATE GENERATION
A layou empla e is a da a s uc u e ha comple ely de ines he physical implemen a ion o a ce ain ci cui a chi ec u e/
opology wi hou ha ing de ailed in elligence on ac ual de ice sizing. The mos impo an ac o common o all ypes o
layou empla es is ha expe ience and knowledge om expe layou designe s can be s o ed in an o de ly sys ema ic
way. The e o e, designe ’s expe ise on analog layou can be eused when needed. This a chi ec u e/ opology desc ibes
only which a e he ci cui componen s and how hey a e connec ed. The layou empla e does no con ain in o ma ion abou
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a speci ic ci cui sizing o he ab ica ion p ocess: qui e he opposi e, he layou empla e mus be as gene ic as possible.
The consequence is ha he layou empla e mus be a ully pa ame e ized en i y. The p ope ies o a pa ame e ized layou
empla e a e he ollowing:
1. Pa ame e ized componen s. The layou empla e can adap di e en pe o mance speci ica ions –o , in o he
wo ds, di e en de ice sizing– because each one o he ci cui design pa ame e s (e.g., ansis o wid h and leng h)
is a pa ame e o he empla e i sel .
2. Rela i e placemen . The loca ion o e e y single block in he layou empla e mus be a unc ion o he loca ion
and dimension o he es o i s neighbo ing blocks.
3. Rela i e ou ing. As wi h ela i e placemen , he physical implemen a ion o he connec ions be ween all he ci cui
iles mus be s o ed in a ela i e way. No e ha ou ing mus be de ined as a unc ion o he block placemen , o
block dimensions, o block pin posi ions, and, o a oid wi e c ossing o e , o he loca ion o o he ou ing wi es.
4. Technology independence. Any e e ence o a pa icula ab ica ion p ocess in he layou empla e has o be
comple ely a oided, and u ned comple ely gene ic. Tha is, all mask laye s, ela i e placemen , and ou ing ha e
o be s o ed in a p ocess-independen way. When he ci cui layou is implemen ed in a pa icula echnology, i mus
be able o adap o bo h he echnological design ules and he se o layou mask laye s.
5. Hie a chy. The layou empla e is he physical implemen a ion o a ci cui a any hie a chical le el. The e o e, he
layou empla e may con ain lowe hie a chical le els wi hin. Sui able p ocedu es a e he e o e equi ed o
ansmi ing down he pa ame e s o he pa en block o i s immedia e hie a chically lowe building blocks,
co espondingly called child o lea componen s.
To implemen all hese p ope ies, he me hodology desc ibed in his pape elies on wo esou ces: he cons ain g aphs
echnique and a se o geome ic-da abase p ocedu es. Layou empla e gene a ion is hen o ganized in wo s ages, i s ,
cons ain g aph gene a ion o se ela i e placemen and ou ing and, second, empla e coding using he se o p ocedu es,
by means o which pa ame e iza ion, echnology independence, and hie a chy a e a ained.
An op imal way o desc ibing he s uc u e o a layou empla e placemen is by means o co ne -s i ching da a s uc u es
and cons ain g aphs [30]. Fig.3 illus a es his ype o desc ip ion. The en i e plane o he block layou is ep esen ed
explici ly wi h ec angles called iles. These iles ep esen physical laye s (e.g., me al o polysilicon), p imi i e de ices
( ansis o s, esis o s, capaci o s, induc o s) and connec o s (con ac s and ias), an a angemen o de ices o any o he
hie a chically highe ci cui layou . The se o iles de ine e ical and ho izon al line segmen s o cu s. Each ile is linked
o he es o iles by a se o poin e s, called co ne s i ches, a wo o hei ou co ne s, and ela ed geome ic cons ain s.
As illus a ed in Fig.4, hese s i ches a e a he bo om-le co ne and a he op- igh co ne .
Each s i ch ep esen s wo coo dina es, ho izon al and
e ical, so each ile is de ined by ou coo dina es, le (l)
and down (d), o he bo om-le s i ch, and igh ( ) and
up (u), o he op- igh s i ch. In his way, he
a qui ec u e’s/ opology’s loo plan can be ep esen ed by
wo plana g aphs and , called
ho izon al and e ical g aphs espec i ely. A e ex in
(o ) ep esen s a e ical
(ho izon al) cu o he loo plan. The e ices a e o de ed
acco ding o he dis ance o he co esponding cu s om
( ), he le -mos (bo om-mos ) side o he
loo plan ec angle, un il he igh -mos side ( he
op-mos side ) a e eached. Two e ices and
in ( ) a e connec ed by an a c di ec ed om
he o me o he la e i he e is a sub- ec angle in he
loo plan whose le (bo om) and igh ( op) edges lie on
he co esponding e ical line segmen s, espec i ely.
Th ough his ep esen a ion, geome ic cons ain s be ween he iles can be easily es ablished by assigning each a c a
weigh . These cons ain s a ise as consequence o (1) p ocess design ules, (2) connec i i y ( o ensu e ha wo iles
emain elec ically connec ed a e layou e a ge ing/mig a ion), and (3) analog speci ic issues (see Sec ion 2.1).
Fig.4 also illus a es he e ical cons ain g aph o he empla e loo plan. and ep esen wo hypo he ical
es ic ions be ween posi ion o iles , , and , , espec i ely. Two-sided a ows mean “equal”, while one-side
B3D
B3U
B1D
DD
B1U
B2D
B2U UU
B3 heigh
0
cons1
B1 heigh
- cons2
B2 heigh
0
UU
Figu e 4: A layou empla e and i s
e ical cons ain g aph.
DD
LL RR
B1
B2
B3
co ne s i ches
co ne s i ches
heigh
e ical cu
ho izon al cu
GHVE,() GVVE,()
V
GHVE,() GVVE,()
LL DD
RR
UU i j
GHGVeij
eij
wij
cons1 cons2
B3B1B1B2
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a ows mean “highe han” o posi i e cons ain s (e.g., ) o “lowe han”, o nega i e cons ain s (e.g., ).
Ca e ully and sma ly de ising a cons ain g aph is essen ial o, (1), a oid o e lapping o he layou iles (which may esul
in ailing o comply wi h he p ocess layou design ules), (2), educe he complexi y o pa ame e iza ion p ocess, mos
specially o ou ing, and, (3), imp o e he lexibili y o he layou empla e o adap a new ci cui sizing while ende ing
compac layou solu ions.
Once he e ical and ho izon al cons ain g aphs ha e been wo ked ou , he p ocedu al gene a o o he layou empla e
is buil . Se e al esou ces ha e been epo ed o c ea e p ocedu al gene a o s, mos o hem based on a e sa ile
p og amming language. On he one hand, he e a e p ocedu al layou app oaches based on common-pu pose languages
such as C o C++. Examples a e he high-le el languages CAIRO [3] and MSL [26]. On he o he hand, speci ic-pu pose
languages a e limi ed o a pa icula ci cui design en i onmen such as BALLISTIC [25], w i en in he Men o G aphics’
LX language o he GDT en i onmen , o SKILL™ [31], he p og amming language o he Cadence’s Design F amewo k
II™ (DFWII) en i onmen .
Wha e e he language used, he ollowing se o basic geome ic-da abase p ocedu es can be used o implemen he
empla e p ope ies:
(a) Resizing and mo ing: geome ic p ocedu es used o sh ink/s e ch a ile and o mo e g oups o objec s while
s e ching o he s, bo h essen ial in he placemen phase.
(b) Repe i ion: a geome ic p ocedu e used o c ea e a ays o objec s in he ho izon al, e ical o bo h di ec ions.
(c) Condi ional inclusion: a geome ic p ocedu e by which an objec can be included o excluded om an ins ance o
he layou empla e, upon ul ilmen o ce ain p e-de ined condi ions.
(d) Laye aliasing: a da abase p ocedu e used o make selec able he manu ac u ing ma e ial each layou polygon is o
be made o . This p ocedu e is i al o a ain he echnology independence p ope y o layou empla es.
(e) Inhe i ance: a da abase p ocedu e ha le s a lea componen inhe i o use one o mo e pa ame e alues om he
pa en block in which i is placed. This allows hie a chically gene a ing nes ed pa ame e ized layou s as well as
main aining comple e con ol o e all he empla e’s pa ame e s.
A inal bu e y impo an ques ion emains. Layou empla es, a any hie a chical le el, mus be de eloped ha ing in mind
all issues explained in Sec ion 2, especially when ocusing analog layou euse. As said, layou empla es ea u e he abili y
o cap u e he equi ed layou expe ise o do so, bu i is only h ough adequa e cons ain g aph and loo plan de ising ha
uly eusable analog layou empla es can be ca ied ou success ully.
6. IMPLEMENTATION
In he implemen a ion p esen ed he e, SKILL™ language and he PCELL echnology [32] om he Cadence’s DFWII
en i onmen ha e been chosen o hei buil -in capabili ies and hei widesp ead accep ance wi hin he design communi y.
Layou empla es can be c ea ed ei he by using a dedica ed use in e ace whe e he geome ic and da abase p ocedu es
a e g aphically applied o a collec ion o mask laye s and o he PCELLS, o by di ec ly w i ing ou he SKILL™ code o
he empla e. The g aphic me hod, howe e , may esul a he in ol ed o complex layou pa ame e iza ion especially i
echnology mig a ion is also a goal (a MOS ansis o p imi i e pa ame e iza ion equi es mo e han 20 g aphic ope a ions).
W i ing SKILL™ code o b ing abou he same pa ame e iza ion p o ides highe lexibili y o c ea ion o complex designs
and an easie way o main ain and upg ade he layou empla e code.
The layou empla e SKILL™ ile uses gene ic design ules as well as gene ic mask laye names. A nume ical alue o each
design ule and a mask laye name should be supplied e e y ime he empla e is ins anced. P o ided ha he design ule
pai s and he mask laye pai s (i.e., he gene ic design ule o mask laye name and he co esponding ac ual alue a he
a ge ed p ocess), a e bo h a ailable, hese can be au oma ically ead o and each mig a ion pa ame e co ec ly adap ed
e e y ime he layou empla e is po ed. In addi ion o he buil -in, a ailable SKILL™ unc ions, se e al new
unc ionali ies (e.g., o au oma ically loca e and e ie e he size and posi ion o he layou iles in o de o implemen he
pa ame e ized placemen and ou ing) ha e been c ea ed o accele a e he gene a ion p ocess o he empla e code [5].
Fig.5 show se e al layou ins ances o he layou empla e o an analog compa a o whose schema ic is depic ed in Fig.5(a).
The ins ances co espond o di e en echnologies as well as o di e en alues o he layou pa ame e s (i.e., de ice sizes).
The layou empla e in Fig.6(a) implemen s he ully di e en ial opamp co e in Fig.6(b). The shaded de ices in he opamp
schema ic a e he lea componen s o he opamp layou empla e. This opamp layou empla e has been ins anced o
di e en echnologies (ins ances Fig.6(c) and (d) in a 0.5-µm CMOS p ocess, ins ances Fig.6(e) and ( ) in a 0.35-µm
CMOS p ocess) and di e en alues o he pe o mance speci ica ions. The implemen ed de ice sizes we e ob ained om
cons1 cons
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P oc. o SPIE Vol. 5837 669
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