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Application of piecewise-linear switched-capacitor circuits for random number generation

Abstract

An unconventional application of switched-capacitor (SC) circuits is discussed. A systematic method for the design of piecewise-linear (PL) parasitic-insensitive SC chaotic discrete maps is given. A simple circuit which generates a random one-bit digital sequence is reported. Simulation results show that the random behavior is not significantly altered by large (about 5%) variations in the values of the design parameters, which makes monolithic implementation feasible. Simulation results and layout for a 2- mu m double-metal CMOS prototype are included.

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Application of piecewise-linear switched-capacitor circuits for random number generation

Author: Espejo Meana, Servando Carlos; Martín Gómez, José Domingo; Rodríguez Vázquez, Ángel Benito; Huertas Díaz, José Luis
Publisher: Institute of Electrical and Electronics Engineers
Year: 1989
DOI: 10.1109/MWSCAS.1989.102013
Source: https://idus.us.es/bitstreams/f1795d55-eb08-4234-aebe-adbd19385ab6/download
APPLICATION
OF
PIECEWISE-LINEAR SWITCHED-CAPACITOR CIRCUITS
FOR
RANDOM NUMBER
GENERATION
Se ando Espejo-Meana, Juan D. Ma in-Wmez, Angel Rod iguez-Vbzquez and
Josd
L. Hue as
Depa amen o de Elec onica y Elec omagne ismo, Uni e sidad de Se illa, 41012-Se illa, SPAIN
Abs ac
An
uncon en ional applica ion o swi ched-capaci o
(SC) ci cui s is discussed in his communica ion. A
sys ema ic me hod is gi en o he design o piecewise-
linea (PL) a asi ic-insensi i e
SC
chao ic disc e e maps.
A
e y simpye ci cui
is
e ed which gene a es a andom
one-bi digi al sequence. &!mula ion esul s show ha he
andom beha io is no signi ica i ely al e ed by la ge
(abou
5%)
a ia ions in he alues o he design
pa ame e s, which makes monoli hic implemen a ions
easible. Simula ion esul s and layou o a 2pm double
me al
CMOS
p o o ype a e included.
In oduc ion
Con inuous p og ess in in eg a ed ci cui echnology
makes
i
possible
o
design comple e signal p ocessing
sys ems (analog plus digi al) in a single chip. Swi ched-
Capaci o (SC) ci cui s ha e been demons a ed
o
be e y
e icien o building hese complex chips
11-31.
As a ma e
o ac ,
SC
echniques ha e been success ully applied
o
he
design o
a
lo
o
signal p ocessing basic ope a o s, ei he
linea o nonlinea . In pa icula si nal gene a ion
(sinusoidal, iangula , squa e
...
)
ia
sC
ci cui s ha e
a ac ed big a en ion in echnical li e a u e
[4-61.
P e ious wo k abou
SC
signal gene a o s has
concen a ed on pe iodic wa e o ms. Howe e , in o he
con ex s, i has been shown ha e y simple nonlinea SC
ci cui s can exhibi e y complica ed chao ic beha io s
171.
I
sugges s he possibili y o applying
SC
echniques o he
gene a ion o ape iodic, e godic signals. Thus, on-chip
andom numbe gene a ion would be possible wi h
po en ial applica ions in SC-based ins umen a ion and
communica ion chips.
In his pa e we
i s
p esen a sys ema ic echnique o
he design
o
pa asi ic-insensi i e
SC
chao ic gene a o s
based on piecewise-linea (PL) disc e e maps,
(1)
(*)
being a PL unc ion, and hen gi e simula ion esul s
and layou o a SC andom numbe gene a o IC p o o ype
based on a wo-pieces discon inuous PL map.
DesiPn o Pa asi ics-insensi i e PL disc e e maps
x(n+
l)=/Lx(n)l,
n=0,1,2,3
,...
Le us conside an in e al
[E,,
EN],
a pa i ion
A={Eo,
E,,
...
EN}
and he ollowingPL unc ion,
MoX
+
Po
,
E,<x<E,
M,x+P,
,
E,<x<E,
. .
. . . . .
.
.
.
. .
.
. .
.
.
.
. . . . .
.
Ax)
=
Mlx+P1
.
E1<x<E,+,
A
mo e compac exp ession o his unc ion can be
ob ained by using wha we call he e he egionalize
ope a o , as ollows,
whe e we de ine,
1
(3b)
,A<x<B
gn(x,A,B)
=
0
,
olhe wise
Fig.la shows a concep ual block diag am o a pa asi ic-
insensi i e
SC
implemen a ion o eq.(3a). Each e m in his
equa ion con ibu es du ing he n- h odd clock phase a
cha ge
Aq:
o
he nega i e inpu e minal o he opamp,
hus
gi ing,
(4)
The im lemen a ion o he i- h cha ge componen in
Fig.la cange made as is shown in Fig.lb, whe e we de ine,
(5)
and whe e
1
and
0"
espec i ely deno e he one and ze o in
he bina y numbe sys em.
The clockin condi ions o he inpu swi ches in Fig.lb
ha e
o
be se ec ed aking in o accoun he signs o
pa ame e s
MI
and
PI,
espec i ely. Fo posi i e
pa ame e s he phases in pa en hesis should be used, he
o he applying o nega i e ones.
By analyzing Fig.lb wi h
(5)
and using he co ec
clocking o he inpu swi ches, i can be concluded
ha
,-------.-----
!I
.I
:
I
Aqp
I
.
I
Fig. la ac ually implemen s he PL ans e unc ion
cha ac e is ics,
u,(n)
=A;),
gi en in (3). Fig.2 shows he
gene al ci cui a chi ec u e
o
a
SC
PL unc ion gene a o
using he abo e me hodolo
.
The signals
WiRo
ha con ol
he ans e o cha ge
o
g
i ual g ound o he opamp
can be implemen ed by using dynamic compa a o s as
i
is
shown in Fig.3.
Figu e
2
I/
Ih
h
IF.
*
Figu e
3
Simpli ica ions in he
SC
PL gene a o
Fig.2 is a gene al scheme ha can be simpli ied in case
he PL unc ion exhibi s some kind o egula i ies. Fo
ins ance, Fig.4a illus a es how
o
elimina e one capaci o
and co esponding swi ches in case wo slopes a e equal,
Mh
=M,.
The case in which wo o dina es a he o igin a e
equal can be handled in a simila way. On he o he hand,
Fig.4b illus a es a simpli ica ion in he case o ha ing wo
pieces wi h opposi e slopes.
Mh
=
-MI.
A
discon inuous PL map o andom numbe gene a ion
pieces PL unc ion,
Fig.5 shows an
SC
ci cui diag am o he ollowing wo
-A+Bx
,
x>o
Ax,
=
(6)
A+Bx
,
o he wise
whe e di e en simpli ica ions ha e been made acco ding
o
he echniques in he abo e pa ag aph. In he nex
sec ion his unc ion is used as a basic building block
o
andom numbe gene a ion.
Figu e4
=i=
Figu e
5
A chi ec u es o PL disc e e maps
Fig.6a shows he concep ual block diag am o a disc e e
map based on a pa asi ic-insensi i e PL unc ion gene a o .
Since he ou pu
o
he unc ion ene a o is only alid
du ing odd ime ins ances, wo h a%-a-pe iod delay s ages
a e equi ed
o
gua an ee p ope iming
o
bo h posi we
and neqa i e inpu signals o he gene a o . Fig.6b shows a
pa asibc-insen i e implemen a ion o he delay s ages in
Fig.6a
[81.
b)
*-
Figu e
6
Fig.7 shows he concep o a andom numbe gene a o
based
on
a
PL disc e e map. The
ou
u signal
dn)
o he
disc e e map is compa ed wi h
a
eg ence le el
E,
hus
esul ing in he ollowing digi al signal a he ou pu o he
compa a o ,
,
x(n)>E
,
o hemise
(7)
'1)
OD
d(n)
=
p o iding
x(n)
is chao ic, his digi al signal may be
expec ed
o
exhibi andom cha ac e is ics.
961
n
1
ET
dln)
I
I
Figu e
7
Design o a andom numbe gene a o p o o ype
Fo he p ocess o gene a ion o
an)
ia Fig.7
o
be a
andom p ocess he ollowing condi ions mus be ul illed:
1.
The unde lying analog signal x(nl has
o
be chao ic.
2.
The p ocess has o be e godic (bo h egula and
s a iona y).
exhibi he same p obabili y.
3.
E e y possible esul {d(n)=I and d(n)=O) mus
4.
P obabili y o ani esul is no dependen on ei he
Analysis o he disc e e map o (6) shows ha o
1
<B
(2
he signal
x(n)
canno escape om he in e al
[-A,
AI also being chao ic in i . Fu he mo e, o
B
>
(
=
1.451,
he ull in e al is isi ed in he ime e olu ion
o he signal. Values o
B
la ge han
1.45
should hen be
used. Pa ame e A has o be chosen o p e en he SC
ci cui implemen a ion
o
he map
o
be locked a pa asi ic
s able poin s caused by he opamp ol age sa u a ion
cha ac e is ics. I is gua an eed by ul illing he ollowing
condi ions,
pas o u u e esul s.
A
A<Vdd‘c
H-l
whe e
Vl,D
and
VS,
a e he posi i e and nega i e powe
supply ol ages, espec i ely.
Fo a 5 ol s CMOS digi al echnology
VU^,
=2.5u,
VSS
=
-2.5~)
an app op ia e choice owing o p e ious
conside a ions should be A
=2.1
U,
B
=
1.76. This
gua an ees ha a disc e e map implemen a ion based on
Fig.5 will, in esponse
o
he powe -on ansien , sel -s a
o
gene a e a chao ic signal x(n) whose alues a e
comp ised in a in e al
[
-2.1
U,
2.1
U].
Besides, hey also
gua an ee ha he sequence will e u n
o
his in e al o
any dis u bance e en ually d i ing x(n) ou side i .
Fig.8 shows he measu ed p obabili y dis ibu ion and
densi y unc ions o he map o (6) wi h A=2.l and
E
=1.76. As i can be seen, he p obabili y densi y unc ion
is symme ical a ound he poin
x=Ou.
I
means ha he
subin e als [-A,
01
and
[O,
A] a e equally p obable.
Hence, i
is
possible
o
design Fig.7 in such a way ha
e e y esul exhibi s he same p obabili y. I can be
achie ed ia he disc e e map o (6) wi h
A
=2.1
U,
B
=
1.76
and E
=
Ou.
Figu e
8
Fig.9 shows he ci cui diag am o he he ein p o osed
SC andom numbe gene a o . The obus ness o? his
ci cui s has been examined in de ail by making a la ge
numbe o simula ions whe e
A
and
B
a e andomly
modi ied wi hin ypical ole ance ma gins a ound he
nominal design alues. The di e en simula ions showed
s a iona y, egula and e godic beha io , hus
demons a ing he iabili y o an IC p o o ype.
-
T
Figu e
9
Fig.10 shows a layou o a 2pm
CMOS
monoli hic
p o o ype. Samples a e now in p og ess. HSPICE de ice
le el simula ions (including pa asi ics capaci o s and
esis o s) ha e been pe o med demons a ing he co ec
ope a ion o he p oposed ci cui . Typical p ocess ole ances
ha e been also conside ed in he simula ions.
Conclusions
A
sys ema ic me hod is p esen ed o he design o
pa asi ic-insensi i e SC PL unc ion gene a o s and chao ic
disc e e maps. A wo-pieces PL map is epo ed leading
o
a
p obabili y densi y unc ion ha is symme ical a ound
he poin
x=O.
Simula ion esul s a he unc ional le el
demons a e he easibili y o a SC andom numbe
gene a o based on his map. The co esponding andom
p ocess exhibi s egula i y and s a iona i y p ope ies,
being also ole an o ypical de ia ions in he design
pa ame e s. De ice le el simula ion esul s o a 2pm
CMOS
monoli hic p o o ype a e in acco dance o bo h
unc ional simula ions and heo e ical analysis.
Re e ences
R.
G ego ian and G.C. Temes: “Analog MOS
In eg a ed Ci cui s
o
Signal P ocessing”. John
Wi1e“y 1986.
K. Nakayama and
Y.
Ku aishi: “P esen and Fu u e
Applica ions o Swi ched-Capaci o Ci cui s”.
ZEEE
Ci cui s and De ices Magazine, Vol. 3, pp 10-21,
-
Sep . 1987.
Y.
Solomon: “Swi ched-Capaci o Fil e s: P ecise,
ComDac and inexpensi e”. IEEE Spec um, Vol. 25,
pp. 28-32, June 1988.
B.J. Hos icka e al. “Design o Nonlinea Analog
Swi ched-Capaci o Ci cui s using Building Blocks”.
IEEE T ans. Ci cui s and Sys ems, Vol. CAS-31, pp
354-368, Ap 1984.
W.B.
Mikhael and
S.
Tu: Con inuous and Swi ched-
Capaci o Mul iphase Oscila o s”.
IEEE
T ans.
Ci cui s and Sys ems, Vol. CAS-31, pp 280-293,
Ma ch 1984.
P.E. Fleische e al.:
“A
Swi ched-Capaci o
Oscila o wi h P ecision Ampli ude Con ol and
Gua an eed S a -up”. IEEE
J.
Solid-s a e
Ci cui s,
Vol. SC-20, pp 641-647, Ap 1985.
A. Rod iguez-Vazquez e al. “Chaos om Swi ched-
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o
heZEEE,Vol. 75, pp 1090-1106,Aug. 1987.
R.
G ego ian: “High Resolu ion Swi ched-Capaci o
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Figu e
10
963
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