2
A PRACTICAL FLOATING-GATE MULLER-C ELEMENT USING νMOS
THRESHOLD GATES
E. Rod íguez-Villegas, G. Hue as, M.J. A edillo, J.M. Quin ana, and A. Rueda
Ins i u o de Mic olec ónica de Se illa (IMSE-CNM)
Edi . CICA, A da. Reina Me cedes s/n, 41012 Se illa, SPAIN.
Indexing Te ms: Th eshold logic design, Concu ence elemen s, Neu on-MOS ansis o
applica ions.
Abs ac :
This pape p esen s he a ionale o νMOS-based ealiza ions o digi al ci cui s when logic
design echniques based on h eshold logic ga es (TGs) a e used. Some p ac ical p oblems in
he νMOS implemen a ion o h eshold ga es ha e been iden i ied and sol ed. The easibili y
and e sa ili y o he p oposed echnique as well as i s po en ial as a low-cos design echnique
o CMOS echnologies ha e been shown by expe imen al esul s om a mul i-inpu Mulle
C-elemen . The p oposed new ealiza ion exhibi s be e pe o mance ela ed o delay, a ea and
powe consump ion han he adi ional logic implemen a ion.
I. In oduc ion
Neu on MOS (νMOS) ansis o p inciple [1] has been iden i ied as one o he mos p om-
ising ways o ealize ul a la ge logic ci cui s [2-5], because he enhancemen in he unc ional
capabili y o an elemen al ansis o makes i e y e ec i e in educing he complexi y o he
o al ci cui . The νMOS ansis o has a bu ied loa ing polysilicon ga e and a numbe o inpu
polysilicon ga es ha couple capaci i ely o he loa ing ga e [1-3]. The ol age o he loa ing
3
ga e becomes a weigh ed sum o he ol ages in he inpu ga es, and hence, is his sum which
con ols he cu en in he ansis o channel.
Logicdesign echniques o implemen a iono νMOSci cui sha ebeenca iedou byShiba a
[2,3], bu hei use ulness is limi ed because, in gene al, i leads o complex ci cui con igu a ions
which equi e handling 2nlogic s a es o an n-inpu logic unc ion. This imposes s ingen con-
s ain s on p ocess ole ances, no ealizable by p esen echnologies o e en a ela i e small n.
A di e en and mo e powe ul app oach o he logic design akes ad an age o he ac ha
he unc ionali y o νMOS ci cui s is closely ela ed o ha o a h eshold logic ga e (TG) [5,
14]. The exis ence o logic design echniques which use TGs as building blocks [6, 7, 8] eases
he syn hesis o complex unc ions. Th eshold logic ga es ha e n wo- alued inpu s x1,x2,…,
xnand a single wo- alued ou pu , y. They a e de ined by n+1 eal numbe s: h eshold Tand
weigh sw1,w2,…,wn,whe e weigh wiis associa ed wi h a iable xi. The inpu -ou pu ela ion
o a h eshold ga e is de ined as y=1 i and y=0 o he wise. Sum and p oduc a e
he con en ional, a he han he logical, ope a ions. The se o weigh s and h eshold can be
deno ed in a mo e compac ec o no a ion way by .
In his pape we epo on a wo king νMOS-based logic ci cui speci ically de ised o alida e
he design app oach using νMOS-based TGs. The pape is o ganized as ollows. Sec ion II de-
sc ibes heimplemen a ion o TGs wi hνMOS ansis o s, i s a a heo e icalle el and hen, dis-
cussing p ac ical conside a ions. The design and expe imen al esul s o an 8 inpu Mulle C-el-
emen a e gi en in Sec ion III, and inally, some conclusions a e discussed in Sec ion IV.
II. νMOS Implemen a ion o Th eshold Ga es
A) Theo e ical backg ound
The mos simple νMOS-based h eshold ga e (νMOS-TG) is he complemen a y in e e
using bo h p- and n- ype νMOS de ices. A schema ic o his TG is shown in Fig. 1. I consis s
wixiT≥
i1=
n
∑
w1w2…wnT;,,,[]
4
in a loa ing ga e, which is common o bo h he PMOS and he NMOS ansis o s, and a numbe
o inpu ga es (Vx1,Vx2, ..., Vxn), co esponding o he h eshold ga e inpu s plus an ex a inpu
(indica ed by in he igu e) o logic h eshold adjus men as will be explained la e . Wi h-
ou using he ex a con ol inpu , and assuming he cha ge in he loa ing ga e is ze o, he ol -
age in he loa ing ga e is gi en by , whe e is he coupling
capaci ance be ween he i- h inpu and he loa ing ga e, and is he o al capaci ance, in-
cluding he pa asi ic capaci ances a he loa ing ga e , . As be-
comes highe han he in e e h eshold ol age, VTH, he ou pu swi ches o logic 1.
A CMOS TG has digi al en ies, i.e., , whe e is he powe supply and
. A ela ion be ween he exp ession o and ha o he de ini ion o he TG can be
es ablishedas he weigh ed summa ion in he TG, , is implemen ed by he capaci i ene -
wo k in he νMOS de ice, . The weigh o each inpu is p opo ional o
he a io be ween he co esponding inpu capaci ance and ( ). Thus,
design in ol es mapping he logical inequali ies and o he elec ical
ela ions and h ough capaci-
ance sizing and uning o he h eshold ol age o he in e e .
When logical h eshold Tis no cen ed (i.e., Tis a om ), he h eshold ol -
age o he in e e would ha e o be also non cen ed (nea 0 o VDD). This can be achie ed
using ex a inpu s. Fo example, le us assume a single con ol inpu wi h capaci ance CCon ol.
I Vc is applied o his con ol inpu , he new is:
whe e
Vc
VFCiVxi
i1=
n
∑



C o
⁄=Ci
C o
CcC o Ci
i1=
n
∑Cc
+= VF
Vxi xiVDD
=VDD
xi01{,}∈VF
wixi
i1=
n
∑
CixiVDD
i1=
n
∑



C o
⁄
CiC o wiCiVDD C o
⁄=
wixiT≥
i1=
n
∑wixiT<
i1=
n
∑
CixiVDD
i1=
n
∑



C o
⁄VTH
>CixiVDD
i1=
n
∑



C o
⁄VTH
<
wi
i1=
n
∑



2⁄
VF
VFCixiVDD
i1=
n
∑



C o
⁄CCon olVc()C o
⁄+=
C o Ci
i1=
n
∑CcCCon ol
++=
5
F om he poin o iew o he TG a compa ison is pe o med be ween
and . Thus, he e ec i e h eshold ol age o he in e e has been
modi ied. In p ac ical digi al design analog ol ages a e a oided and so he ole o he analog
ex a inpu Vc is ealized by a se o digi al inpu s wi h he app op ia e coupling capaci ances.
Clea ly, p ac ical design equi es conside ing second o de e ec s no included o simplici y in
he abo e exp essions. The main issue o he ci cui in Fig. 1 is ela ed wi h he coupling e ec p o-
duced when swi ching on he powe supply. T ansis o capaci ances C d (be ween loa ing ga e and
d ain) and C s (be ween loa ing ga e and sou ce) a e esponsible o hese couplings which in o-
duce addi ional e ms in VF. Sizing o inpu capaci o s and ansis o s should be pe o med on he
basis o educing hese ex a e ms, o also o adequa ely con olling he e ec i e in e e h eshold
ol age. In addi ion, he e could be pa asi ic cha ge in he loa ing ga e a e ab ica ion and i is ob-
ious ha he ci cui ope a ion is sensi i e o i . Fo his e ec , UV e asu e is ecommended.
B) P ac ical design aspec s
Beside he heo e ical backg ound o he ealiza ion o TGs wi h νMOS de ices, p ac ical de-
signandimplemen a iono hesega es equi e akingin oaccoun andsol ing he ollowingissues.
a) Signal egene a ion. Clea ly hese TGs exhibi educed noise ma gins as a consequence
o he elec ical ope a ion o he ci cui . On he o he hand, some inpu combina ions can p o-
duce ou pu ol ages di e en om VDD o g ound. These wo conside a ions a e specially
c i ical when logic ne wo ks a e buil up in e connec ing νMOS-TGs. Thus he in e e Iin
Figu e 1 should be seen as an in e ing signal egene a ion s age.
b) Elec ical simula ion. Du ing he design phase, elec ical simula ions o alida ion mus
be pe o med, and hence, good models o loa ing-ga e MOSFETs should be used. Since man-
CixiVDD
i1=
n
∑



C o
⁄
VTH CCon olVc()C o
⁄–
6
u ac e s do no p o ide hese models, echniques o simula e loa ing ga e de ices wi h s anda d
MOS models mus be de ised. O he o he di icul ies in simula ing loa ing ga e de ices elies
on he inabili y o he simula o o con e ge when loa ing nodes exis . An ini ial ope a ing poin
o heci cui mus be in oduced. P e ious app oaches o hisp oblem a e gi en in [9,10].They
use an addi ional ne wo k o med by esis o s and VCVSs (Vol age Con olled Vol age Sou c-
es) o es ablish he ini ial loa ing-ga e ol age alue. The main p oblem o hese app oaches is
ha anope a ionpoin is p e iously de e mined o ix he alue o he ol ages a heVCVS con-
ol e minals. Those alues a e hen assumed cons an o all he es o he ci cui ope a ion.
This las is no comple ely co ec because o he nonlinea ela ionship be ween he loa ing-
ga e ol ageand he ol ages in heo he de ice e minals (d ain, sou ce), dependingon he an-
sis o ope a ion egion. The simple p ocedu e we ha e de ised [11] o e comes he abo e p ob-
lem. I is based on pe o ming a ansien analysis which s a s wi h all he powe supplies and
ci cui inpu s se o ze o. Thus, ini ial condi ion o he loa ing-ga e ol age p o ided o he sim-
ula o is ze o. A e wa ds, in he same ansien analysis, powe and inpu s a e se o hei alues.
The s a iona y s a e eached p o ides he co ec ini ial ope a ion which can be used o he es
o simula ions. In o de o illus a e he accu acy o ou me hod he ci cui shown in Fig. 2(a)
has been designed and ab ica ed. I consis s o wo cascaded in e e s. The i s one is imple-
men ed using νMOS de ices and he second is a con en ional logic CMOS in e e o signal
egene a ion. The ci cui has wo inpu s Vin and Vc wi h equal coupling capaci ances (C=70 F).
I beha es like an in e e wi h inpu Vin and h eshold ol age a ying wi h Vc. Bo h in e e s
a e equally sized. In Fig. 2(b), one o he simula ions pe o med o ob aining he ans e cha -
ac e is ics o nodes Vou 1 and Vou is shown o illus a e ou simula ion app oach. No ice ha
he ini ial alue o VFis p o ided by he simula o aking in o accoun all he pa asi ic coupling
e ec s. Figu e 3 compa es he expe imen al measu emen s ob ained a e UV e asu e wi h he
simula ion esul s ob ained ollowing ou echnique and he app oach in [9]. Inpu -ou pu cha -

7
ac e is ics o di e en alues o Vc (0, 1, 2, 3, 4 and 5 ol s) a e shown. Ag eemen be ween
simula ion wi h ou echnique (Figu e 3a) and expe imen al (Figu e 3c) is obse ed. Howe e
he esul s ob ained wi h he echnique in [9] (Figu e 3b) di e om he expe imen al ones since
he simula ed h eshold ol ages o he in e e appea shi ed o he igh . The easibili y o he
p oposed simula ion echnique o analog ci cui s has been also expe imen ally e i ied [11].
III. Applica ion Example: A Mul i-Inpu Mulle C-elemen
A Mulle C-elemen (whe e he C s ands o concu ence) is a ci cui widely used in he de-
sign o sel - iming ci cui s o pe o m he unc ion “and” o e en s ( ansi ions 1→0o 0→1).
I s ou pu is made equal o he alue o inpu a e all he inpu each he same alue; o he wise,
he ou pu emains he same. I has been p o en [12] ha an m-inpu Mulle C-elemen can be
implemen ed using a single h eshold ga e wi h (m+1) inpu s, and he simples solu ion is ob-
ained when he p ima y inpu s ha e an associa ed weigh o 1, he (m+1)- h inpu ( he eedback
inpu ) is a ec ed by a weigh o (m-1), and he h eshold o he TG is m, as shown in Figu e 4a.
The complexi y o his logic elemen is high enough o se ing as a good demons a o o
he easibili y o he p oposed design app oach based on νMOS-TG. On one hand, i shows ha
a complex unc ionali y can be implemen ed by a single in e e . On he o he , he exis ence o
a eedback loop wi h a high associa ed weigh (m-1) allows es ing he signal egene a ion ca-
pabili y ha would gua an ee he co ec ope a ion o h eshold ne wo ks.
Figu e 4b depic s he νMOS ealiza ion we p opose o he logic diag am shown in Figu e
4, when m= 8. This ci cui has been designed and ab ica ed in an 0.8µmdouble poly CMOS
echnology. Ope a ion unde p ocess and ambien pa ame e s has been alida ed h ough ex-
ensi e HSPICE simula ions o he ex ac ed ci cui including Mon e Ca lo simula ions and
simula ions using di e en s anda d wo s case de ice pa ame e s. Figu e 5 shows he espons-
es ob ained in he labo a o y. Wa e o m a he bo om ace is he ci cui ou pu and he emain-
8
ingwa e o ms co espond o he ci cui signal inpu s. No ice ha ope a ion is co ec . Thisco -
ec ope a ion has been obse ed in he labo a o y wi h he supply ol age down o 3V.
Fo compa ison pu poses we ha e also designed and laid-ou a con en ional 8 inpu Mulle
C-elemen ollowing he s uc u e p oposed in [13] which has been shown o be e y e icien .
Table I compa es he a ea, ime pe o mance and powe consump ion o bo h Mulle C-ele-
men s.
IV Conclusions
We ha e exploi ed he ela ionship be ween he νMOS ansis o p inciple and he h eshold
ga e concep . On i s basis a new νMOS ealiza ion o mul i-inpu Mulle C-elemen s has been
p oposed and i s easibili y demons a ed wi h an eigh inpu Mulle C-elemen wo king in sili-
con. Compa ed o a con en ional ga e-based implemen a ion, he νMOS design is e y e icien .
I occupies hal he a ea han i s con en ional coun e pa , exhibi s be e ime pe o mance and
consumes signi ican ly less powe . In addi ion, an elec ical simula ion echnique o loa ing
ga e de ices has been desc ibed and i s accu acy has been p o en expe imen ally.
Re e ences
1 T. Shiba a, T. Ohmi, “A unc ional MOS ansis o ea u ing ga e le el weigh ed sum and
h eshold ope a ions”, IEEE J. Solid-S a e Ci c., ol. 39, pp. 1444-1445, 1992.
2 -------, “Neu on MOS bina y-logic in eg a ed ci cui s- Pa I: Design undamen als and
so -ha dwa e-logicci cui implemen a ions”, IEEE T ans.Elec onDe ices, ol. 40,pp.
570-576, 1993
3 -------,“Neu on MOS bina y-logic in eg a ed ci cui s- Pa II: Simpli ying echniques o
Ci cui Con igu a ion and hei P ac ical Applica ions”, IEEE T ans. Elec on De ices,
ol. 40, pp. 974-979, 1993.
9
4 W. Webe , e al., “On he applica ion o he Neu on MOS T ansis o P inciple o Mod-
e n VLSI Design”, IEEE T an. Elec on De ices, ol. 43, No. 10, pp. 1700-1708, Oc o-
be 1996.
5 K.F. Gose , C. Pacha, A. Kans ein, and M.L. Rossmann, “Aspec s o Sys ems and Ci -
cui s o Nanoelec onics”, P oc. o he IEEE, Vol. 85, No. 4, pp. 558-573.
6 S. Mu oga, Th eshold Logic & i s Applica ions, New Yo k: John Wiley & Sons, 1971.
7 A. L. Oli ei a and A. Sangio anni-Vincen elli, LSAT- An Algo i hm o he Syn hesis
o Two Le el Th eshold Ga e Ne wo ks, P oc In . Con . on Compu e Aided Design, pp.
130-133, 1991.
8 K. Siu and V.P. Roychowdhu y, An Op imal-dep h Th eshold Ci cui o Mul iplica ion
and Rela ed P oblems, SIAM Jou nal o Disc e e Ma hema ics,7, (2): 284-292, 1994
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and Sys ems, pp. 2020-2023, 1997.
10 L. Yin, S.H.K. Embabi and E. Sánchez-Sinencio, “A Floa ing-Ga e MOSFET D/A Con-
e e ”, IEEE In e na ional Symposium on Ci cui s and Sys ems, pp. 409-412, 1997.
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onica de Se illa, IMSE-CNM, 1998.
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sign, ECCTD’95, pp. 51-54.
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Mulle C-elemen ”, IEEE T ans. on VLSI Sys ems, ol. 1, no. 2, pp. 215-219, June 1993.
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Elec ical and Elec onics Enginee ing, J.G. Webs e , Ed., Vol. 22, pp. 178-190, 1999.
10
Cap ions o he Figu es:
Figu e 1: MOS h eshold ga e schema ic
Figu e 2: a) Floa ing-ga e CMOS in e e wi h h eshold con ol;
b) T ansien simula ion pe o med o ob ain ans e cha ac e is ic o ci cui in
Figu e 2a o Vc = 3V
Figu e 3: Simula ion and expe imen al inpu -ou pu cha ac e is ics o he ci cui in Fig. 2a:
a) Simula ion esul s wi h ou echnique;
b) Simula ion esul s wi h he echnique in [9];
c) Expe imen al esul s
Figu e 4: a) Th eshold-ga e-based m-inpu Mulle C-elemen ealiza ion;
b)Elec ical diag am o MOS-based 8 inpu Mulle C-elemen
Figu e 5: Expe imen al wa e o ms o MOS-based 8 inpu Mulle C-elemen
Cap ions o he Tables:
Table I: Pe o mance pa ame e s o MOS and con en ional 8-inpu Mulle C-elemen s