MIXED-SIGNAL DESIGN OF A FULLY PARALLEL FUZZY PROCESSOR
I. Ba u one, A. Ba iga, S. Sánchez-Solano and J. L. Hue as.
Ins i u o de Mic oelec ónica de Se illa (IMSE-CNM).
Edi icio CICA, A da Reina Me cedes s/n, 41012 Se illa, Spain.
Indexing e ms: Fuzzy p ocesso s, pa allel a chi ec u e, mixed-signal cu en -mode
design.
ABSTRACT
This pape p esen s a no el a chi ec u e o implemen gene al-pu pose uzzy chips. I
allows ully-pa allel ule p ocessing employing a educed numbe o mixed-signal com-
pu ing blocks and minimum-sized digi al memo ies. The esul ing uzzy p ocesso can in-
e ac di ec ly wi h con inuous senso s and ac ua o s and subsequen digi al p ocessing
sys em.
INTRODUCTION
A ypical mul iple-inpu single-ou pu uzzy sys em con ains a se o IF-THEN ules
like he ollowing:
ule :IFx1 is A1 and ... and xu is Au THEN y is B
whe e xi (i=1,..., u) a e he inpu s and y is he ou pu . The an eceden s’ uzzy se s, Ai ( =1,
..., R), pa i ion each inpu space in o L local uzzy egions while he consequen B de-
sc ibes he beha iou wi hin he joined egion (A1 , ..., Au ). Hence, he o al numbe o
possible ules is R=Lu.
A uzzy sys em is inhe en ly pa allel in he u inpu a iables, R ules, and N elemen s
in which he ou pu space is disc e ized. Rega ding ha dwa e, his means a ade-o be-
ween high in e ence speed (pa allel p ocessing) and low silicon a ea (sequen ial p ocess-
ing). Single on uzzy sys ems ha employ single on alues, c , o de ine he consequen s,
B , a e usually chosen o ha dwa e ealiza ion since hey elimina e pa allelism in N [1-3].
In he li e a u e, ully-digi al app oaches ha e been epo ed educing pa allelism in R
(=Lu) by only p ocessing he αu simul aneously ac i e ules (whe e α is he o e lapping
deg ee o he inpu membe ship unc ions) [1, 4]. To allow pa allel p ocessing o he ules,
he p oposal in [4] is o employ αu copies o he ule memo y and o use mul ibi compu -
ing ope a o s, which a e e y a ea consuming. Combining analogue and digi al ci cui y
seems mo e in e es ing since digi al ci cui y eases p og ammabili y o he uzzy p oces-
so and compa ibili y wi h subsequen digi al sys ems while analogue ci cui y o e s pa -
allel compu ing wi h lowe ha dwa e esou ces. Howe e , digi ally-p og ammable ana-
logue ealiza ions p e iously epo ed implemen a small numbe o ules and hey do no
op imise digi al pa because he p og ammable pa ame e s a e s o ed in digi al egis e s
and selec ed by ex ensi e ma ixes o swi ches (mul i-po -like digi al memo ies), which
occupy a la ge a ea [2-3].
The a chi ec u e p esen ed in his le e allows op imiza ion o bo h he analogue and
digi al pa o a ully-pa allel uzzy p ocesso . The analogue co e is op imised by using an
ac i e- ule d i en scheme implemen ed wi h cu en -mode compu ing blocks. The digi al
pa is also op imised by using an adequa e memo y o ganisa ion ha makes possible o
e ie e all he equi ed pa ame e s in pa allel wi hou a need o eplica ion o mul i-po
cos ly memo ies.
PROPOSED DESIGN
Single on uzzy sys ems ca y ou he ollowing o mula: y = Σ h •c / Σ c , whe e h
is he ac i a ion deg ee o he - h ule [1-3]. The a chi ec u e we p opose o implemen
hem is illus a ed in Figu e 1 o he case o wo inpu s, u=2, and a maximum o e lapping
deg ee o wo, α=2. The pa ame e s ha de ine he an eceden s and consequen s a e s o ed
in con en ional RAMs (Xi-Mem and Y-Mem se s) so ha he uzzy p ocesso can be sui -
ably p og ammed o a gi en applica ion.
The membe ship deg ees, Iµ, o each inpu a iable a e ob ained by he ans e unc-
ions o α ci cui s known as MFCs. The MFCs desc ibed in [5] (Figu e 2), which a e
based on digi ally-p og ammable cu en mi o s (D/A), ha e been selec ed. They admi
analogue inpu signals and p o ide apezoidal unc ions de ined by 4 digi al wo ds.
Hence, he size o he global memo y, X-Mem, ha s o es he membe ship unc ions’ pa-
ame e s o each inpu is 4•L wo ds. Each X-Mem memo y is di ided in o α pa s (con-
en ional RAMs) which s o e he pa ame e s o he membe ship unc ions ha a e ne e
ac i e simul aneously. This is illus a ed in Figu e 3 o he simple case o L=4 (in his
example, he 4•2 wo ds associa ed wi h he membe ship unc ions NB and PS a e s o ed
in he M11 pa o he X1-Mem while he o he 4•2 wo ds a e s o ed in he M12 pa ). Fo
a gi en inpu xi, one se o pa ame e s (4 wo ds) o each memo y pa is add essed by a
code o n bi s, {b1xi, ..., bnxi}, n being he in ege bigge o equal o log2(L+1-α), whe e
L+1-α a e he possible combina ions o ac i e inpu uzzy se s. Hence, calcula ion o he
membe ship deg ees is pe o med in pa allel since he α se s o equi ed pa ame e s pe
inpu a e e ie ed wi h one access o he X-Mem global memo y. Each code {b1xi, ...,
bnxi} is ob ained by compa ing he inpu xi wi h he cen es o he membe ship unc ions
ha co e he i- h inpu space, as illus a ed in Figu e 3. This compa ison can be done in
pa allel by using L-α cu en compa a o s and a maximum o L-2 p og ammable cu en
mi o s. Ano he solu ion is o op o a bina y- ee compa ison scheme. In his case,
shown in Figu e 1, he ope a ion akes mo e ime (n clock phases go e ned by he signals
{R1, ..., Rn}) bu no addi ional cu en compa a o s o p og ammable mi o s a e equi ed
by exploi ing he inpu s age o he MFCs (shown wi hin a dashed box in Figu e 2).
The i- h MUX block a e he MFCs implemen s cu en eplica ions and iden i ies
which MFC ou pu goes o each ΜΙΝ by using he leas signi ican bi s o he se {b1xi, ...,
bnxi}. Compu a ion o he ules’ ac i a ion deg ees is pe o med in pa allel by he αu mul-
i-inpu analogue MIN ci cui s whose s uc u e is desc ibed in [5]. The MUX blocks a e
he MIN ci cui s iden i y he co esponding CONS by using he leas signi ican bi s o
he whole se {b1x1, ..., bnx1, ..., b1xu, ..., bnxu}.
The CONS blocks a e digi ally p og ammable cu en -mi o s (Figu e 2) ha weigh
each ule’s ac i a ion deg ee by i s co esponding single on alue. The Lu digi al wo ds
ha de ine all he single on alues a e s o ed in he Y-Mem global memo y. This memo y
is di ided in o αu pa s (con en ional RAMs) whe e each pa s o es he consequen s’ al-
ues ha a e ne e ac i e simul aneously. Fo he case illus a ed in Figu e 3 (αu =4), each
o he 4 pa s s o es 4 digi al wo ds (M1, o ins ance, s o es c1, c3, c9, and c11). Gi en an
inpu {x1, ..., xu}, one wo d o each memo y pa is add essed by he whole code {b1x1,
..., bnx1, ..., b1xu, ..., bnxu} so ha he αu equi ed consequen s a e e ie ed in jus one ac-
cess o he Y-Mem memo y. The sums Σ h •c and Σ h a e simply implemen ed by wi ed
connec ion as we a e wo king wi h cu en signals. Hence, he whole p ocessing o all he
ac i e ules is ca ied ou in pa allel.
The block DIV implemen s he inal di ision Σ h •c / Σ h wi h a successi e-app oxi-
ma ion echnique so ha he ou pu is p o ided in bo h digi al and analogue o ma s (Fig-
u e 2). Di ision can be pe o med in pa allel by using a lash A/D con e e a he cos o
silicon a ea. A good ade-o speed/a ea is achie ed by a di ide based on con inuous-
ime algo i hmic da a con e e s, like ha desc ibed in [3]. In his case, he ime in es ed
in di ision inc eases wi h ou pu esolu ion.
F om p e ious designs in eg a ed in 2.4-µm CMOS p ocess [3, 5], we can es ima e he
ollowing ea u es o a ypical wo-inpu uzzy p ocesso wi h α=2 implemen ed wi h he
p oposed a chi ec u e: I s analogue co e occupies a silicon a ea o abou 1mm2 (consid-
e ing 8- and 4-bi wo ds o p og am he an eceden s and consequen s, espec i ely, and 5-
bi esolu ion o he ou pu ) and i consumes less han abou 20mW o a 5-V powe sup-
ply. I s esponse ime is less han abou 2µs. These ea u es sligh ly change when inc eas-
ing he o al numbe o ules ( o ins ance implemen ing 16, i L=4, o 81 ules, i L=9).
The a ea and powe consump ion o he digi al pa is also op imised since he numbe o
wo ds s o ed is he minimum o de ine he sys em.
CONCLUSIONS
A no el a chi ec u e o implemen uzzy p ocesso s has been p esen ed. A ea and pow-
e consump ion is e y small because pa allel compu ing is pe o med in cu en -mode
analogue domain using an ac i e- ule d i en scheme. An adequa e o ganisa ion o he dig-
i ally p og ammable pa ame e s makes possible o e ie e hem in pa allel om con en-
ional RAM memo ies. Hence, p ocessing o many ules can be achie ed a high in e ence
speed and wi h e y low ha dwa e esou ces.
REFERENCES
[1] SASAKI, M., UENO, F., and INOUE, T.: “An 8-bi esolu ion 140 KFLIPS uzzy
mic op ocesso ”, P oc. Fi h IFSA Wo ld Cong ess, Seul 1993, pp. 921-924.
[2] MANARESI, N., FRANCHI, E., GUERRIERI, R., and BACCARANI G.: “A ield
p og ammable analog uzzy p ocesso wi h enhanced empe a u e pe o mance”,
P oc. ESSCIRC’96, Neucha el 1996, pp. 152-155.
[3] BATURONE, I., SÁNCHEZ-SOLANO, S., BARRIGA, A., and HUERTAS, J. L.:
"Flexible uzzy con olle s using mixed-signal cu en -mode echniques", P oc.
FUZZ-IEEE’97, Ba celona 1997, pp. 875-880.
[4] CHIUEH, T.-C.: “Op imiza ion o uzzy logic in e ence a chi ec u e”, IEEE Com-
pu e , 1992, 24, (5), pp. 67-71.
[5] BATURONE, I., SÁNCHEZ-SOLANO, S., BARRIGA, A., and HUERTAS, J. L.:
“Implemen a ion o CMOS uzzy con olle s as mixed-signal IC’s”, IEEE T ans.
on Fuzzy Sys ems, 1997, 5, (1), pp. 1-19.
Y-Mem
x1
MFC11
MFC12
x2
MFC21
MFC22
M
CONS1
CONS2
CONS3
CONS4
DIV
y
Analogue co e
R1 ... Rn
M1
M2
M3
M4
U
X
M
U
X
b1x2 ... bnx2
b1x1 ... bnx1
MINbb
MINaa
MINba
MINab
X2-Mem
M21
M22
X1-Mem
M11
M12
M
U
X
M
U
X
M
U
X
M
U
X
Figu e 1: P oposed a chi ec u e o he case o wo inpu a iables and a
maximum o e lapping deg ee o wo.
D/A
D/A
analogue Iµ
slope
D/A
D/A
V/I
cen e
sa u a ion
MFC
inpu
om
X-Mem
signal o
gene a e
he bi s
slope
Σh Ip
A/D
Σh •c analogue
q1
qm
D/A
h
h •c
D/A
CONS
DIV
digi al
ou pu
ou pu
om
Y-Mem
{bj}
Figu e 2: Schema ics o he compu ing blocks [3, 5].
c13 (M3)c
14 (M4)c
15 (M3)c
16 (M4)
c9 (M1)c
10 (M2)c
11 (M1)c
12 (M2)
c5 (M3)c
6 (M4)c
7 (M3)c
8 (M4)
c1 (M1)c
2 (M2)c
3 (M1)c
4 (M2)
x1
example o ac i e ules
NB (M11) NS (M12) PS (M11) PB (M12)
x2PB
PS
NS
NB
b1x1b2x1:00 01 11
Figu e 3: Rule able ha illus a es he pa i ions o he an eceden s’ and
consequen s’ memo ies.