Expandible high-order cascade ya modulator with constant, reduced systematic loss of resolution

IMTC 2003 - lnsmmenialion and Measurement Technology Conference Vail. CO, USA, 20-22 May 2003 Expandible High-order Cascade ZA Modulator with Constant, Reduced Systematic Loss of Resolution E Medeiro, R. del Rio, J.M. de la Rosa, B. PCrez-Verdli, and A. Rodriguez-VBzquez Instituto de Microelectr6nica de Sevilla - CNM-CSIC Edif. CICA-CNM, Cmarfia s/n, 41012Sevilla, SPAIN Phone: +34 95 5056666, Fax: +34 95 5056686, e-mail: [email protected] A-t - An arbitrary order sigma-delta modulator cascude architecture is presented with only I-bit loss of resolution due to scaling issues, even with single-bit quantizulion. This loss is kept with a high overloading point, regardless of the order. Simulations reveol that circuit imperfections can be tolerated up to 6th order, so that 90-dB SNDR can be obtained with x16 oversampling, without multi-bit quantization. I. INTRODUCTION The increasing demand for broadband access to the internet has stimulated the industrial interest in high-performance AD converters able to achieve between 12and 16-bit accuracy for signal bandwidths exceeding lMHz [I]. These specifications seem a priori better suited for pipeline architectures. However the larger linearity and simpler circuitry of oversampled, sigma-delta modulator (ZAM) converters render them worth exploring for the implementation of wireline modems as mixed-signal systems on-chip. This is only feasible if ZAM architectures are devised capable to feature those resolution levels with low values of the oversampling ratio-M. This involves either increasing the modulator order or' using multi-bit quantization, or a combination of both. Among the alternatives explored, many designers have focused on cascade architectures (including single-bit or multi-bit quantization) to provide up to 6th-order, low oversampling ratio AID conversion over the xDSL band [21-[61. Two considerations are important for fully exploiting the potential of cascade ms. On the one hand, signals in the cascade must be properly scaled to prevent a premature overload of the modulator stages. Digitally compensating such scale factors causes a systematic loss of resolution. The larger the number of stages, the more evident the overloading problem becomes, so that the systematic loss increases with the modulator order. On the other hand, the integrator finite DC-gain and the weight mismatches impact cascade architectures, causing imperfect cancellation of the low-order quantization error produced by the first stages. In this paper the order of the cascade ZAM is extended arbitrarily while the systematic loss of resolution is not increased. A 2-11 cascade together with a set of integrator weights and a simple cancellation logic are proposed to reduce the systematic loss to Ibit, regardless of the order and without changing the overloading point. We show that the degradation due to circuit imperfections can be tolerated up to 6th order for an oversampling ratio of 16, which makes it possible to obtain 15-bit resolution in the ADSL band and without multi-bit quantization. 11. MODULATOR ARCHITECTURE Fig.1 shows an Lth -order cascade architecture consisting of L - 1 stages: a second-order ZAM, acting as a first stage, and L - 2 identical first-order stages. All quantizers are also identical comparators. The cancellation logic is also easily expandible, requiring just right shifters and delay blocks. The key to run this architecture, and what makes it advantageous with respect to other high-order cascades, is the integrator weight selection. It has been made according to the following criteria: (a) ideally, the quantization error generated by all stages other than the last one must be removed by the cancellation logic; (b) the modulator must preserve a high overloading point; (c) the output swing needed in integrators must be physically achievable according to the supply voltage; (d) the number of branches required for each integrator and the total number of unitary capacitors should be minimized. Combining behavioural simulation and statistical optimization we obtain: go = go1 = 0.25 g1 = l,gl' = 0.5 (1) which, under ideal conditions, leads to the following z -domain output, gk=1,g~=0.5,g~=0.5 k=2 ,..., L-1 Y(z) = X(2)z-L + 2(1 -z-')LE,_ (2) 0-7803-7705-2/03/$17.M) 02003 IEEE 229 Y first-order )I - - - - A staqes U Cancellation Logic Fig. 1.Lth-order2-1L-2~AM. ~~(z)=(I-~-l)k,k = 2...,-1 where E, - I (2) stands for the last-stage quantization error. Note that its transfer function contains an amplifying factor of 2, which means a systematic loss of only lbit, or 6dB signal-to-(noise + distortion) ratio (SNDR j, with respect to an ideal Lth -order ZAM. This loss is considerably smaller than the systematic loss in other cascade architectures and does not increase with the modulator order. Neither the overloading point (-5dB below full scale) is modified by the increasing order. To illustrate this, Fig.2(a) shows the SNDR vs. input level for two versions of a 6th-order 2-2-2 cascade [4] 151, and the one in this paper with L = 5 and 6. Note that even with L = 5 the SNDR is improved with respect to the 6th-order 2-2-2 cascades. Returning to the proposed coefficients, note that the largest weight of each 3-weight integrator (k = 2, .._, L1 ) can be obtained as the summation of the others, so that no 3-branch SC integrators are required. This also minimizes the number of unitary capacitors to 2(4L + I) in a fully-differential implementation. Finally, the total output swing required in all integrators equals the quantizer full-scale. This interesting feature for implementation in low-voltage technologies is illustrated in Fig.Z(b) for the case L = 6. ID. CIRCUIT IMPERFECTIONS Apart from other circuit imperfections whose impact is, to a first order, independent of L, integrator weight mismatch and finite DC-gain produce incomplete cancellation of the quantization noise induced in the first stages, which may mask the ideal one, thus imposing an upper bound to the feasible values of L . In order to estimate this limit under realistic I -60 45 -30 -1 5 0 input amplitude I Vref (dB) (4 300 I - InMl 200 E 2 tn +. .- = 100 0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 (b) Output voltage / Vref Fig. 2. (a) SNDR vs. input level under ideal conditions. (b) Histograms of the integrator outputs relative to the reference voltage. circuit imperfections, Fig.3(a) shows the simulated half-scale SNDR as a function of the amplifier DC-gain for M = 16. Fig.3(b) shows the SNDR histograms obtained from Montecarlo simulation assuming 0.1% sigma in capacitor ratios (0.05% is currently featured by MiM capacitors in standard CMOS processes [7]). Under these conditions, mainly because of the matching sensitivity, the 7th-order architecture is not worth implementing. Nevenheless, the 6th-order modulator provides 90-dB worst-case SNDR with DC-gain of 2500. Especially robust is the 5th-order cascade requiring a DC-gain of 1000 to achieve 80-dB worst-case SNDR with M = 16. The required DC-gains are smaller for the remaining L - 2 stages of the cascade, down to 500, which allows us to use simpler circuits and layouts for these otherwise identical stages. As a concluding remark, note that since most degradations are due to imperfect cancellation of the first-stage quantization error, orders larger than L = 7 become feasible by applying the on-line digital correction strategy in [SI. 230 100 - 90 m E 80m Y) 5 IU 70 - 605040 I I 30 E m 1 20 P k? 10 0 65 75 [SI A.R. Feldman, B.E. Bow, and P.R. Gray, "A 13-Bit. I.4-MSIs Sigma-Delta Modulator for RF Baseband Channel Applications". IEEE JoumnlofSolid-Store Circuits, Vol. 33. pp. 1462-1469. October 1998. [6] K. Vleugels, S. Rabii. and B. Wooley: "A 2.5-V Sigma-Delta Modulator for Broadband Communications Applications". IEEE Journal of Solid-Sme Circuirs. Vol. 36, pp. 1887-1899, December 2001. [71 J.C.H. Lin: 'TSMC 0.25wm Mixed-Signal IP5M+ MIM Salicide 2.5Vl5.OV Design Guideline". Taiwan Semiconductors Manufacturing CO. ADC's - Pan 11: Correction Using Test-Signal Injection". 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