IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 6, JUNE 1997 507
Indi idual Flip-Flops wi h Ga ed Clocks o
Low Powe Da apa hs
Tomas Lang, En ic Musoll, and Jo di Co adella
Abs ac —Ene gy consump ion has become one o he impo -
an ac o s in digi al sys ems, because o he equi emen o
dissipa e his ene gy in high-densi y ci cui s and o ex end he
ba e y li e in po able sys ems such as de ices wi h wi eless
communica ion capabili ies. Flip- lops a e one o he mos ene gy-
consuming componen s o digi al ci cui s. This pape p esen s
echniques o educe ene gy consump ion by indi idually deac i-
a ing he clock when lip- lops do no ha e o change hei alue.
Flip- lop s uc u es a e p oposed and selec ion c i e ia gi en o
ob ain minimum ene gy consump ion. The s uc u es ha e been
e alua ed using ene gy models and alida ed by swi ch-le el
simula ions. Fo he applica ions conside ed, signi ican ene gy
educ ions a e achie ed.
Index Te ms—Flip- lop ene gy model, ga ed clocks, low powe
da apa hs.
I. INTRODUCTION
THE REDUCTION o ene gy consump ion has become
one o he impo an ac o s in digi al sys ems, because
o he equi emen o dissipa e his ene gy in he high-densi y
ci cui s ha a e possible wi h submic on echnology, and o
ex ending he ba e y li e in po able sys ems, such as high-
pe o mance po able compu e s and pe sonal digi al assis an s
(PDA’s) wi h mul imedia and wi eless communica ion capa-
bili ies.
The design o low powe ci cui s can be ackled a di e en
le els, om sys em o echnology, as illus a ed o ins ance
in [4], whe e nume ous e e ences o he opic can be ound.
We he e concen a e on echniques a he logic le el o
CMOS echnology, aiming a educing he a e age ene gy
consumed in he da apa h egis e s du ing an ope a ion. This
ene gy accoun s o a la ge ac ion o he o al ene gy o
he sys em. Fo ins ance, o he PVQ decode desc ibed in
[12] he ene gy consumed by he egis e s is 90% o ha
consumed by he da apa h, and his alue is o abou 75%
o he adix-4 mul iplie and o he accumula o ha we
ha e implemen ed. Double-edge igge ed (DET) lip- lops [8]
Manusc ip ecei ed Ma ch 24, 1997. This wo k was suppo ed in pa by
he Na ional Science Founda ion G an MIP 9314172 and CICYT G an TIC
95-0419. This pape was ecommended by Gues Edi o s S. Kiaei and E. G.
F iedman.
T. Lang is wi h he Depa men o Elec ical and Compu e Enginee ing,
Uni e si y o Cali o nia, I ine, CA 92697 USA.
E. Musoll was wi h he Depa men o Compu e A chi ec u e, Uni e si a
Poli `
ecnica de Ca alunya, 08071 Ba celona, Spain. He is now wi h Na ional
Semiconduc o Co po a ion, San a Cla a, CA 95054 USA.
J. Co adella is wi h he Depa men o Compu e A chi ec u e, Uni e si a
Poli `
ecnica de Ca alunya, 08071 Ba celona, Spain.
Publishe I em Iden i ie S 1057-7130(97)04785-X.
ha e been p oposed as one o he echniques ha can p oduce
signi ican ene gy sa ings (20%) o his ype o sys ems.
Howe e , he synch oniza ion model imposed by DET lip-
lops is no always applicable. Fo his eason, we ocus on
he mo e con en ional single-edge igge ed (SET) lip- lops.
In his pape we conside he app oach o disabling he
clock when he lip- lop mus no change, which educes he
ene gy consumed by he clock ci cui s in e nal o he lip-
lop. This app oach can also be combined wi h app op ia e
da a ep esen a ions o educe he swi ching ac i i y [10].
This disabling echnique is ela ed o me hods p oposed o
shu down inac i e po ions o he sys em [4], [6], such as
inhibi ing he egis e load and/o inhibi ing he clock (ga ed
clock). Inhibi ing egis e load is p oposed in [1] bu his does
no educe he e ec i e load on he clock. The use o ga ed
clocks o educe he ac i i y o logic modules is desc ibed in
[3]–[5], [12], [13].
Ou p oposal is a a ine le el o g anula i y in which
indi idual lip- lops a e ac i a ed/deac i a ed acco ding o
hei local beha io . Flip- lop s uc u es a e p oposed and
models o ene gy consump ion a e de eloped, esul ing in
c i e ia o selec he mos -app op ia e s uc u e depending on
he lip- lop ac i i y.
To alida e he models, he ci cui s ha e been implemen ed
in a Sea-o -Ga es design amewo k [7] and he ene gy con-
sump ion has been de e mined using a swi ch-le el simula o
[14] based on an model wi h iming.
We conclude ha a signi ican educ ion in ene gy can be
ob ained wi h he echniques p oposed in his pape .
II. ANENERGY MODEL FOR DFLIP-FLOPS
We now discuss a model o he ene gy consumed by a
D lip- lop (called in he sequel ), which is used as
a amewo k and a e e ence o compa e wi h he p oposed
s uc u es. As shown in Fig. 1(a) he inpu is he ou pu
o a combina ional ne wo k and he inpu comes di ec ly
om he clock. Because o he s uc u es discussed la e , we
use a ailing-edge igge ed lip- lop.
Since in CMOS he main componen o he ene gy is
dynamic, he lip- lop consumes ene gy whene e he e is a
ansi ion in any o i s inpu s, ha is
1) du ing he ansi ions o These ansi ions a e o wo
ypes: he eal ansi ion co esponding o he unc ion
implemen ed by he combina ional ne wo k, and spu i-
ous ansi ions (gli ches);
2) du ing bo h edges o he clock.
1057–7130/97$10.00 1997 IEEE
508 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 6, JUNE 1997
(a)
(b)
Fig. 1. (a) T ailing-edge D lip- lop
(
con )
. (b) A possible implemen a ion.
Mo eo e , he ene gy consumed du ing a ansi ion depends on
he p esen and nex s a es o he lip- lop and on he ela i e
iming o he ansi ions, so ha he ollowing si ua ions a e
iden i ied.
• Wi h espec o he s a e, we conside h ee cases, namely,
when he lip- lop changes, when he s a e emains 0, and
when he s a e emains 1.
• Wi h espec o he ela i e iming o he ansi ions and
he clock leading edge, we conside wo cases, namely,
when he ansi ion occu s be o e and a e his edge.
Consequen ly, we ob ain he ollowing pa ame e s o he
ene gy consumed by one e en o he co esponding ype:
Flip- lop changes. This includes he ene gy consumed
du ing clock edges and du ing he eal ansi ion o .
Flip- lop emains in s a e 0 (no ansi ion in ).
Flip- lop emains in s a e 1 (no ansi ion in ).
Gli ch o be o e he leading edge o he clock.
Gli ch o a e he leading edge o he clock.
No e ha a gli ch co esponds o wo spu ious ansi ions.
The a e age ene gy pe cycle is ob ained by he summa ion
o he p oduc s o he ene gy pa ame e imes he co espond-
ing a e age numbe o e en s pe cycle (deno ed by ). Tha
is
wi h and
A D lip- lop such as he one depic ed in Fig. 1(b) has been
implemen ed based on he design in [11] and simula ed a he
swi ch le el. We ha e ob ained
whe e is he anou 1and he uni co esponds o he ene gy
consumed by one ou pu ansi ion o a 2-inpu NAND ga e wi h
uni load. This exp ession shows ha a signi ican ac ion o
he ene gy is consumed when he lip- lop ou pu does no
change
1A uni load co esponds o he inpu capaci ance o an in e e .
III. CLOCK ACTIVATION
To educe he ene gy consumed when he lip- lop ou pu
does no change we con ol he inpu o he lip- lop by
he ac i a ion signal so ha
This is implemen ed by he AND ga e shown in Fig. 2(a).
This ga e can be easily in eg a ed in he lip- lop ealiza ion
by adding wo ansis o s. In he sequel, we call his a ga ed
lip- lop (hence o h, ). Mo eo e , in he he inpu is
no necessa ily (as in ), since when he alue
o is a don’ ca e. We call his inpu unc ion
As shown in Fig. 2(b), o he o ope a e co ec ly i
mus be ailing-edge igge ed and he signal mus no
ha e nega i e ansi ions while he clock is high. Fo ins ance,
i in cycle signal has a nega i e ansi ion while
is high, hen a ailing edge in is p oduced, changing
o 0 inco ec ly. Consequen ly, i mus be assu ed ha
he nega i e ansi ion o (including any possible gli ches)
occu s be o e he clock pulse. The e ec o his on he delay
o he ne wo k is conside ed in Sec ion V. I a leading-edge
lip- lop is used ins ead, an OR ga e should eplace he AND
and simila es ic ions exis on he ac i a ion signal. In he
sequel, we only conside he ailing-edge case.
The ac i a ion signal is a unc ion o and Fo
he ne wo k o ope a e co ec ly, i is necessa y ha
whene e he lip- lop has o change alue. This condi ion is
s a ed by he ollowing Boolean inequali y:
(1)
Mo eo e , o a co ec ope a ion, he inpu mus ha e a
alue such ha
i
don’ ca e i
These condi ions a e exp essed by he ollowing Boolean
inequali y
(2)
The ac ual unc ions and should sa is y condi ions (1)
and (2), educe he ene gy consump ion, and sa is y o he
equi emen s, such as delay and a ea.
In he nex wo sec ions we conside s uc u es ha sa is y
(1) and (2) o wo classes o si ua ions, as ollows.
Independen Case The combina ional ne wo k does no in-
clude as an inpu . Tha is
(3)
whe e is he inpu
o he ne wo k.
Dependen Case is an inpu o he combina ional ne -
wo k, namely
(4)
As shown in Sec ion III-B his dependence can be used o
simpli y he ne wo k o ob ain
LANG e al.: INDIVIDUAL FLIP-FLOPS 509
(a)
(b) (c)
Fig. 2. (a) Ga ed ailing-edge lip- lop
(
g);
example o co ec (b) and inco ec (c) iming.
A. Independen Case
Fo he independen case o exp ession (3), we now conside
he h ee s uc u es shown in Fig. 3. Fo he s uc u e,
only when he lip- lop ou pu has o change, so
ha he lip- lop clock is ne e ac i a ed when i does no
change, in con as wi h in which he clock is ac i a ed
in e e y cycle. Al hough his co esponds o he minimum
clock ac i a ion equi ed, his s uc u e migh no be he mos
app op ia e when he ex a ene gy, a ea, and delay o he XOR
ga e is included. Because o his, we conside also he o he
wo s uc u es, in which he complexi y o he gene a ion o
he ac i a ion signal is educed a he expense o ac i a ing he
clock in some cycles when he lip- lop ou pu does no change.
As shown in he Table o Fig. 3, in he case he clock is
ac i a ed when he lip- lop changes and when i emains in
s a e 1. The implemen a ion is shown in Fig. 3(b); he OR ga e
is in eg a ed wi h he AND ga e and wi h an in e nal in e e in
a complex ga e. Simila ly, in he he clock is ac i a ed
when he lip- lop changes as well as when i emains in s a e 0.
The able also shows o each s uc u e he co esponding
exp ession o he condi ion o (2), and he simples
unc ion ha sa is ies his condi ion.
1) Ene gy models: We now conside ene gy models o he
new lip- lop s uc u es and gi e he alues o he ene gy
pa ame e s ob ained om he swi ch-le el simula ions. The
exp ession o he ene gy is simila o ha o Sec ion II, excep
ha now, as discussed in Sec ion III, all ansi ions o ha e
o occu be o e he leading edge o he clock. The esul ing
exp ession is
(a) (b) (c)
(d)
Fig. 3. Flip- lop s uc u es, ou pu ansi ions o which he clock is ac i-
a ed, and Boolean unc ions o he inpu s.
The pa ame e s o lip- lop s uc u es ha ha e been im-
plemen ed a e shown in Table I ( he able also gi es ela i e
a ea and delay, om o one uni load). F om his able
we ob ain he ollowing expec ed conclusions.
• Fo he pa ame e s and a e small, since he
clock is deac i a ed in hese cases. On he o he hand,
he pa ame e s co esponding o ansi ions in ( ha is
and ) inc ease wi h espec o because o
he XOR ga e.
• Fo he pa ame e is small since he clock is
deac i a ed in his case. and inc ease somewha
wi h espec o bu less han o Fo
he si ua ion is simila o exchanging 0 and 1.
Fo speci ic alues o he cha ac e is ics o lip- lops (de-
ined by ) and he a e age numbe o ansi ions (de ined
by ), he lip- lop s uc u e ha consumes he leas ene gy
510 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 6, JUNE 1997
TABLE I
PARAMETERS FOR THE IMPLEMENTED FLIP-FLOP STRUCTURES
(a) (b) (c)
Fig. 4. Ene gy a ios o (a)
N
0
=
N
1
. (b)
N
0
=2
N
1
. (c)
N
1

0
:
(a) (b) (c)
Fig. 5. Rela i e e o be ween model and simula ions. (a)
N
0
=
N
1
. (b)
N
0
=2
N
1
. (c)
N
1

0
.
is de e mined. No e ha i migh be con enien o use di e en
ypes o lip- lops in he same egis e , since he a e age
numbe o ansi ions migh be di e en .
To compa e he ene gy o di e en s uc u es, we use he
a io o ene gy wi h espec o a con en ional implemen a ion,
ha is so ha smalle co esponds o la ge
educ ions. Fig. 4 shows his a io o se e al speci ic cases,
a anou o uni load, and no gli ches. The a io is gi en as
a unc ion o o di e en alues o Since
o hese alues, he s uc u e is be e han he
s uc u e we do no show he case; o
simila plo s would be ob ained wi h he s uc u e be e
han he s uc u e. We conclude ha , he educ ion is la ge
o smalle alues o he bes lip- lop depends on o
small he bes is hen o in e media e he bes
is ei he o and inally, o la ge he bes is
Mo eo e , he b eakpoin be ween egions depends on
he a io The case co esponds o a limi ing
si ua ion, showing he bes educ ion ha can be achie ed.
We ha e no conside ed in hese plo s. The alue o
depends on he pa icula applica ion and on he design
and implemen a ion app oach. In hose applica ions in which
ene gy consump ion is a c ucial design ac o , combina ional
blocks migh be designed o educe he numbe o gli ches
[2], [9]. In he applica ions conside ed in his pape , we ha e
measu ed he gli ches o he speci ic implemen a ion and ha e
included hei e ec in he ene gy calcula ions.
2) Simula ion o Implemen a ions: We ha e implemen ed
he lip- lop s uc u es and ob ained he ene gy om swi ch-
le el simula ions. As can be seen om Fig. 5, he ela i e
e o o he simula ions wi h espec o he models
is less han 5%.
LANG e al.: INDIVIDUAL FLIP-FLOPS 511
B. Dependen Case
We now conside he dependen case o (4). Because o he
dependence o on ins ead o i s ob aining and hen
and sa is ying (1) and (2), he signals and a e ob ained
di ec ly. Consequen ly, we use he s uc u e o Fig. 2(a). To
ob ain he ene gy exp ession we need o iden i y he di e en
possible e en s. They a e
• he lip- lop ou pu changes. In his case We use
he subsc ip o his e en ;
• he lip- lop ou pu does no change and (clock
deac i a ed). We use he subsc ip o his e en ;
• he lip- lop ou pu does no change bu We use
he subsc ip o his e en .
Mo eo e , he e a e wo ypes o possible gli ches: in inpu
and in inpu The ene gy exp ession is hen
Ou implemen a ion o his lip- lop esul s in
As indica ed in Sec ion II, he condi ions o and a e
IV. APPLICATIONS
We now illus a e he use o he lip- lop s uc u es in bo h
he independen and dependen cases. Two de ailed examples
and a summa y o he esul s epo ed o o he examples a e
p esen ed. Fu he in o ma ion on he implemen a ion de ails
o all he examples can be ound in [10].
In he e alua ions we use lip- lops wi h he cha ac e is ics
desc ibed be o e, conside ing an ex e nal load o he lip-
lops o wo uni loads. In he sequel, ep esen s he o al
load (ex e nal and in e nal) o he lip- lops. The in e nal load
depends on he implemen a ion chosen o he applica ion. The
compa isons a e in e ms o he a io o he ene gy o he
con en ional and he low powe implemen a ions. Fo each
applica ion, he ene gy has been es ima ed in wo di e en
ways, namely, (1) by applying he ene gy model p e iously
p esen ed, and (2) by means o swi ch-le el simula ions [14]
o a ealiza ion o he ci cui . To compu e he a e age, we
ha e pe o med a sui able numbe o simula ions wi h inpu s
ob ained om speci ic dis ibu ions, as indica ed in each
applica ion. Mo eo e , we ha e also implemen ed he equi ed
combina ional ne wo k in a Sea-o -Ga es design s yle [7] and
epo he ene gy a io o he o e all ci cui ob ained om he
swi ch-le el simula ions.
The applica ions in his pape ha e a bi -wid h o 16 bi s.
Simila esul s a e expec ed o la ge ope and bi -wid hs.
A. Independen Case: Sampling o Signals
This example co esponds o sys ems in which a signal is
sampled and he alue is s o ed in a egis e . To educe he
ene gy consumed by he egis e , special lip- lop s uc u es a e
ad an ageous o he bi s ha ha e low ac i i y. This si ua ion
happens, o example, o he ollowing wo scena ios.
• Slow- a ying signals (compa ed wi h he sampling a e).
This occu s, o ins ance, in he sampling o audio and
ideo signals.
• Signals in which he alues a e mos o he ime close
o a ixed poin . This occu s, o ins ance, in sys ems
ha moni o physical quan i ies, such as empe a u e and
p essu e.
As an illus a ion, we conside he sys em shown in
Fig. 6(a), in which a iangula signal is sampled and he alue
loaded in o a 16-bi egis e [Fig. 6(b)]. The equency o he
signal and he sampling pe iod a e such ha he p obabili y
o change o lip- lop is as shown in
Fig. 6(c). This is due o he ac ha he alue in he egis e
changes by 1 each cycle. Simila esul s should be ob ained
o o he slow- a ying signals.
Con en ional Implemen a ion
A con en ional implemen a ion would use con en ional D
lip- lops o all bi s. Assuming ha he inpu signal has no
gli ches, he ene gy is
since, on he a e age, wo lip- lops change
Low Powe Implemen a ion
Fo he lip- lop ansi ions we ha e
and o lip- lop Acco ding o he conclusions
ob ained be o e we use he ollowing lip- lop s uc u es.
• Flip- lop 0: use
• Flip- lop 1: use
• Flip- lops 2 o 15 use
The o al ene gy is 48.0 uni s and he a io is 48.0/136.8
0.35. We ha e implemen ed bo h egis e designs and, om
he swi ch-le el simula ion, ha e ob ained a a io o 0.32.
Since he s uc u e has la ge a ea and delay han he
s uc u e we e alua e he ene gy when s uc u es a e
also used o lip- lops 2 o 15. The ene gy is now
• Flip- lop 0: use
• Flip- lop 1 o 15: use
Now he o al ene gy is 90.0 uni s and he a io is
90.0/136.8 0.66. Fo his case, he swi ch-le el simula ion
p oduces a a io o 0.71.
B. Dependen Case: Accumula o
The ope a ion is desc ibed by he ecu ence
whe e and a e he inpu ope ands.

512 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 6, JUNE 1997
(a) (b)
(c)
Fig. 6. Sampling o a slow- a ying ( iangula ) signal. (a) Sys em. (b) Signal. (c) Ac i i y o egis e bi s.
We conside wo ypes o ep esen a ions o non edun-
dan adix-2 and ca y-sa e. Mo eo e , we conside he case
in which he alue o is uni o mly dis ibu ed; simila
analyzes would be applicable o o he dis ibu ions.
1) Non edundan Rep esen a ion
Fo his case a ca y-p opaga e adde is used. Tha is, as
shown in Fig. 7(a), he ecu ence is implemen ed by he
ollowing Boolean exp ession:
whe e is he h bi o he ca y- ec o . This ec o can
be p oduced in se e al ways, such as using ca y- ipple o
ca y-lookahead s uc u es.
Con en ional Implemen a ion
In his case con en ional lip- lops a e used. I he alues o
a e uni o mly dis ibu ed, he a e age numbe o ansi ion
in is We use a symme ic clock in which case
he gli ches occu be o e he leading edge o he clock since
he a e age leng h o he ca y chains is small wi h espec o
he wo s -case delay o he adde . We ha e measu ed
0.52. Consequen ly, he ene gy pe lip- lop is ( o
Implemen a ion wi h Ac i a ion Signal
In his case a is used and he simples ac i a ion signal is
Consequen ly, ins ead o ha ing o include an addi ional
XOR ga e in he implemen a ion o his esul s in a educ ion
o one XOR ga e wi h espec o as shown in Fig. 7(b). In
addi ion
Since in his case is always 0 when he lip- lop ou pu
does no change, we ha e We ha e measu ed
and 0.65, esul ing in he
ene gy pe ( o )
The a io is
2) Ca y-Sa e Rep esen a ion
To ha e a as e ope a ion edundan adde s a e used.
We illus a e he use o a ca y-sa e adde in which he
accumula ed alue is ep esen ed by he sum o wo ec o s
so ha The exp essions a e
Con en ional Implemen a ion
A bi slice consis s o one ull adde and wo con en ional
lip- lops, as shown in Fig. 8(a). In his case, using a symme ic
clock makes he gli ches occu a e he leading edge o he
clock since he a e age delay is simila o he wo s -case delay.
We ha e measu ed he ollowing equencies.
• Fo Fo
LANG e al.: INDIVIDUAL FLIP-FLOPS 513
(a)
(b)
Fig. 7. Non edundan accumula o (a) wi h
con
and (b) wi h
g
:
esul ing in he ene gy pe bi -slice ( o
Implemen a ion wi h Ac i a ion Signal
The ac i a ion signal o is he same as ha o in he
p e ious case, ha is
Because o he “shi ing” in he ca y ec o , he ca y
is o he “independen ” ype (as in Sec ion III-A). We ha e
measu ed
• Fo and Mo eo e , since when
he lip- lop does no change is always 0, we ha e
and .
• Fo
Because o hese alues he bes s uc u e o he ca y bi
is as shown in Fig. 8(b). The ene gy pe bi -slice ( wo
(a)
(b)
Fig. 8. Ca y-sa e accumula o (a) con en ional. (b) Wi h ac i a ion signal.
lip- lops) is ( o )
bi
The a io is 21.7/29.2 0.74.
Implemen a ion and Simula ion
We ha e implemen ed all he accumula o designs and
ob ained by swi ch-le el simula ion he ollowing a ios o he
ene gy consumed by he lip- lops and o he o e all ene gy
o he accumula o .
• Non edundan ep esen a ion wi h ac i a ion signal:
• Ca y-sa e ep esen a ion wi h ac i a ion signal:
Simila analyzes would be applicable o simila sys ems,
such as coun e s.
C. Summa y o he Applica ions
Table II summa izes he esul s ob ained om se e al exam-
ples, including hose p e iouly desc ibed in his sec ion. Fo
each applica ion we show he case wi h he smalles o e all
ene gy. In he cases o he adix-4 sequen ial mul iplie and
he edundan accumula o , a no el encoding echnique o
edundan da a has been also used. Fu he de ails on his
echnique can be ound in [10].
We obse e ha he simula ed esul s a e close o hose
ob ained wi h he model. We u he obse e ha in hose
514 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 6, JUNE 1997
TABLE II
SUMMARY OF THE APPLICATIONS
(
s
AND
o e all
ARE THE
ENERGY SAVINGS RATIOS OF THE FLIP-FLOPS AND OF THE
WHOLE CIRCUIT; I/D STANDS FOR INDEPENDENT/DEPENDENT CASE)
(a)
(b)
Fig. 9. Ne wo k wi h (a) con en ional lip- lop and (b) ga ed lip- lop.
applica ions wi h combina ional logic he e is also a signi ican
o e all ene gy educ ion.
V. TIMING CHARACTERISTICS
We now conside he inc ease in cycle ime ha migh esul
om he use o clock ac i a ion. We compa e he cycle imes
o he ne wo ks o Fig. 9. We conside he case in which he
inpu s o he combina ional block come om he ou pu o
lip- lops igge ed wi h he same clock.
1) Con en ional Flip-Flop
The cycle ime when a con en ional lip- lop is used is
de e mined by he ollowing wo es ic ions:
1) The delay o plus he se -up ime and he
ansmission delay Tha is
2) The es ic ions on he minimum wid h o he wo
subcycles. Tha is
whe e and a e he minimum wid h o he
low subcycle and he high subcycle, espec i ely. These
minima depend on he minimum o co ec lip- lop
ope a ion and and on he minimum wid h
o he clock, as de e mined by clock gene a ion and
Fig. 10. Cycle o con en ional case and o ac i a ion case.
dis ibu ion (which we call and So, o
example
Consequen ly,
as illus a ed in Fig. 10.
2) Ga ed Flip-Flop
In con as o he con en ional case, o a ne wo k wi h
he cycle ime is de e mined by he delay o bo h signals
and As discussed in Sec ion III, signal has o become
s able du ing he pa o he cycle in which he clock is low.
Tha is, he low subcycle ime has he es ic ion
whe e is he delay o he logic calcula ing and is
he ansmission delay o he ga ed lip- lop ( his is somewha
la ge han ha o he nonga ed lip- lop because o he
in eg a ed AND ga e). Since o he high subcycle
we ob ain
Mo eo e , simila ly o he con en ional case, o signal
whe e is he delay o he logic unc ion o he inpu
o he lip- lop and is he new se -up ime. Fo p ac ical
cases, and because o he in e nal delay
p oduced by he ga ed clock.
Combining he las wo exp essions we ob ain
LANG e al.: INDIVIDUAL FLIP-FLOPS 515
TABLE III
TIMING CHARACTERISTICS OF FLIP-FLOPS STRUCTURES
which is shown in Fig. 10. Fo p ac ical cases, usually
and hus
No e ha when using he con en ional lip- lop, he delay o
signal can be sp ead ou o e he whole cycle (low and high
subcycles), whe eas when using he ac i a ion signal he e is
a sepa a e es ic ion on he low subcycle. Consequen ly, o
ob ain he minimum delay i migh be necessa y o ha e an
asymme ical clock.
Fo a pa icula si ua ion he exp essions gi en abo e ha e
o be compa ed o de e mine he co esponding cycle imes.
The cycle ime o he case wi h ac i a ion signal migh be
la ge han ha o he con en ional case because
1) The delay o p oduce migh be la ge han ha o
p oduce
2) The ansi ion ime o he ga ed lip- lop is la ge han
ha o he con en ional lip- lop;
3) I migh be necessa y o add o he o he com-
ponen s.
Howe e , in some cases he delay o he signal migh be
sho e han he delay o so ha can be used o he
high pa o he cycle, and s ill achie e he same cycle ime.
Mo eo e , he iming es ic ion o signal may be elaxed o
e en elimina ed i he logic gene a ing is no on he c i ical
pa h. This may happen, o example, in he leas -signi ican
bi s o a ca y- ipple adde o when p ocessing low- equency
signals.
In [4], a ci cui o gene a e a ga ed clock is desc ibed wi hou
he iming es ic ion o he ac i a ion AND ga e. Howe e ,
his ci cui is complex and, he e o e, only app op ia e when
gene a ing a common ga ed clock o se e al lip- lops, which
is no ou case.
A. Example: Redundan Accumula o
We now conside he edundan accumula o o illus a e he
e ec on he cycle ime.2All imes a e in uni s co esponding
o he p opaga ion delay o a 2-inpu NAND ga e, wi h uni load.
The iming cha ac e is ics o he lip- lop s uc u es we use a e
gi en in Table III. No e he wo se -up imes: is he
se -up ime o lip- lop inpu wi h espec o he ailing
edge o he clock, whe eas is he se up o he signal
applied o he inpu o he XOR,OR,o NAND ga e wi h espec
o he leading edge o he clock.
2Ano he example is gi en in [10].
The cycle ime o he con en ional implemen a ion is
measu ed)
Fo he implemen a ion wi h ac i a ion signal and special
coding ( 2.9)
Compa ing he wo alues o he cycle ime we can see
ha he implemen a ion wi h ac i a ion signal is no slowe
han he con en ional implemen a ion o
VI. CONCLUSIONS
Synch onous sys ems equi e he clock ha dic a es he em-
po al beha io o he sys em. A signi ican amoun o ene gy
is was ed o conse a i ely ensu e a p ope synch oniza ion
among di e en componen s.
In his pape , ine-g ain clock ac i a ion echniques ha e
been p oposed o educe he was e o ene gy in lip- lops
wi h low ac i i y. In some applica ions, such as sequen ial
mul iplie s and accumula o s, ene gy sa ings o abou 25%
( o he mul iplie ) and 50% ( o he accumula o ) ha e been
ob ained by combining he clock ac i a ion wi h special coding
app oaches o edundan da a ep esen a ions. The sa ings
a e e en mo e signi ican o speci ic applica ions such as he
sampling o slow- a ying signals.
Fu he e o is equi ed o in es iga e e icien imple-
men a ions o lip- lops. On he o he hand, echniques o
au oma ically selec ing he mos app op ia e lip- lop s uc u e
acco ding o ac i i y c i e ia mus also be explo ed.
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