Earth fault location based on evaluation of voltage sag at secondary side of medium voltage/low voltage transformers

Earth fault location based on evaluation of voltage sag at secondary side of medium voltage/low voltage transformers ISSN 1751-8687 Received on 15th May 2014 Revised on 23rd February 2015 Accepted on 17th March 2015 doi: 10.1049/iet-gtd.2014.0460 www.ietdl.org David Topolanek1✉, Matti Lehtonen2, Mohd Rafi Adzman2, Petr Toman1 1 Faculty of Electrical Engineering and Communication, Brno University of Technology, Brno, Czech Republic 2 Department of Electrical Engineering, School of Science and Technology, Aalto University, Aalto, Finland ✉E-mail: [email protected]br.cz Abstract: The main reasons for installation of power quality meters in distribution transformer substations are power quality monitoring and global evolution of electrical network towards the ‘smart grid’. In case that all measurements from the meters are properly synchronised and centralised, new possibilities of control or evaluation of the network are enabled. This contribution proposes the possibility for an earth fault localisation with the aid of synchronised data recorded on the low-voltage side of the medium voltage/low voltage transformers in compensated neutral distribution networks which are equipped with auxiliary resistor for short-time increasing of the active part of the fault current. The described method uses voltage sags evoked by connecting of the auxiliary resistor for locating the faulty section. The proposed method is tested with the help of numerical model which presents a part of the distribution network. 1 Introduction The resonant earthed network is the most common type of Czech distribution networks, which its purpose is to compensate network capacitive current during an earth fault (EF) and to limit the EF current level. The level of residual current is very low and therefore it is possible to operate an affected network without an interruption of power supply and risk of hazard voltages occurrence. However, fast and accurate EF location in distribution networks is a very complicated task due to low fault level and independence of fault current magnitude on fault position. This is the reason why lots of different methods have been proposed for EF location in resonant earthed systems. All known methods for EF location can be categorised based on its principle to active and passive methods. Active methods use some specific active signal which is injected into distribution system for EF location by tracking of the signal to fault point [1– 5]. The main disadvantage of these active methods is necessity of active source for generation of the characteristic signal. Other mentioned group of passive methods is based on evaluation of voltages and currents inside of affected network. This group is the most widespread and therefore this chapter will be focused on listing of passive methods. Several simple methods which were designed for isolated distribution network can be find in publication [6,7]. These methods are based on comparison of magnitude or phase displacement of zero-sequence currents, respectively, on detection of zero-sequence reactive power. More sophisticated admittance method which could be used in more common resonant earthed systems was designed in contribution [8,9]. This method utilises similar way as is used for distance protection, where is possible to design a concrete characteristic according to operation condition with maximising sensitivity of the EF protection. Similarly conductance method, where conductance is calculated from zero-sequence components can be used for EF indication in resonant earth systems [10]. The last category of passive methods is based on evaluation of transients which are caused by an EF ignition. As an example, the method described in [11] can be mentioned. This transient method evaluates discharging process represented by transient phenomenon of zero-sequence components. The other transients based algorithms can be found in [12–15]. All the above mentioned methods can be used for indication of faulty feeder or direction to fault, but it is not possible to directly find a fault point inside the affected network. Localisation of an EF inside a wide distribution network is very challenging and technically difficult in contrast to faulty feeder detection which is quite mastered at present. One of the most useful and effective techniques which is still used for delimitation of the faulty section of the line in Czech medium voltage (MV) networks is successive disconnection of the affected line by system operator. This procedure is used to select of the faulty area where a technical staff is sent to find the exact fault point. The disadvantages of this process are time consumed and operational difficulties. It also requires multiple power interruptions in many cases. Another method for EF location is based on redistribution of zero-sequence (residual) current to both feeders when faulty feeder is interconnected with healthy feeder to a loop [16,17]. However, this interconnection cannot be always possible to be implemented in extra-urban parts of the distribution network. The next problem is inhomogeneity of MV lines, where due to high number of different types and short parts of line is very difficult and sometimes impossible to create a suitable impedance model for fault location calculation. Next possible ways to locate an EF in compensated network is usage of EF indicators [18–20]. The indicators use some of steady state or transient principle described for an example in [21,22]. According to the directionality of these indicators and knowledge of the network topology the faulty section can be defined. A necessary condition for the function of this system is single-purpose distribution of the indicators to key points of monitored network what is quite expensive. Other drawback of this solution is the dependence of the size of delimited section on the number of installed indicators and their positions. Another group of methods used for EF location in the MV system is focused on comparison of voltage sags recorded in supply substation with Voltage Sags Database (VSD) [23,24]or evaluation of secondary voltage patterns [25]. The rest of methods are focused on the calculation of the reactance between supply substation and EF point [26–30]. The reactance corresponds to the fault distance which can match more than one fault place in the network. Therefore, additional principle must be used for selection of correct place, otherwise operator has to check all possible IET Generation, Transmission & Distribution Research Article IET Gener. Transm. Distrib., 2015, Vol. 9, Iss. 14, pp. 2069–2077 2069This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) places personally. The drawback of mentioned methods is calculation of an EF position based on currents and voltages measured only in one point of the network in supply substation, which is mostly far away from the real fault location hence its sensitivity is lower than for measurement point close to the fault. This could lead to significant errors in the determination of the fault location what complicates quick fault location. As mentioned above, each of the known methods for EF location, especially in compensated network has its advantages and disadvantages and perhaps there is no universal method, which would allow EF location with sufficient accuracy and reliability for locating all types of EFs keeping reasonable costs for operation and implementation of a location system. 2 Proposal of new EF location method based on evaluation of voltage sags The need for monitoring the characteristic parameters of electric energy and distribution networks development towards the concept of ‘smart grids’impose requirements on the development and installation of the measuring or recording devices into distribution transformer stations (DTSs) where low voltage (LV) monitoring is required. In case when such devices are installed in most of MV/ LV transformer stations and all their recorded data are properly centralised and time-synchronised, new possibilities for the optimisation and management of by this way monitored network are opened up. This approach is due to the large number of DTSs is very costly; therefore, it is important to maximise the overall efficiency of the operation of these monitors. This can be achieved by maximal utilisation of data which are provided by voltage and current monitors installed in distribution network with a positive impact on improving the quality of power supply. Therefore, this proposed method is designed to use data from the monitors to streamline of investments costs in this area. A new method for EF location is proposed here, especially for compensated distribution system equipped with automatic for short-time connection of auxiliary resistor to increase the active component of fault current. This automatic function is usually used in European distribution networks for improving of directional EF protection sensitivity. The functional principle of proposed method is based on the evaluation of voltage sags recorded by monitors installed on the secondary side (LV side) of the transformers 22/0.4 kV, which is caused by connecting of an auxiliary resistor R p during continuous EF. However, the same principle can be used with small modification also in system without auxiliary resistor, but it is necessary to respect operational differences and few disadvantages which this modification brings. 2.1 Effect of connection of the auxiliary resistor on phase voltages on LV side When solid EF occurs in an ideally compensated network, an EF current is flowing through the faulty line to the fault point. The current has an active character and its level is proportional to shunt conductance of affected network considering also losses in the arc-suppression coil. This residual (fault) current causes voltage sag on faulty line impedances which contributes to unbalance of line-to-line voltages towards the fault point. However, this voltage unbalance is hardly detectable in common compensated networks due to the very low level of residual currents. The way of residual current IWflow through faulty line is shown in Fig. 1. The scheme shown in Fig. 1presents simplified scheme of ideally compensated network where a feeder is affected by EF. The feeder has two MV/LV transformer stations (DTS1, DTS2) equipped with voltage monitors on the LV side. It is possible to connect the auxiliary resistor R p which is placed in high-power winding of suppression coil (SC) by the circuit breaker (SB). When the SB is switched on, the major impact on the level of L–L voltage unbalance is due to the short-time connection of auxiliary resistor. In this case, the initial residual current IWis for short-time increased by single-phase fault current Ik1, which is limited by the value of the auxiliary resistor R p .Again,thiscurrentflowing through line impedance causes L–L voltage unbalance along the faulty line what is measurable on the LV side of distribution transformers (DTs) as voltage sags of phase to neutral voltages. This voltage unbalance is increased in the direction of the fault current to the fault point, where it reaches its maximum. This process can be simply described by using a symmetrical components scheme designed for a single-phase EF, as shown in Fig. 2. The symmetrical components scheme corresponds with network in Fig. 1, where Eis the symmetrical operation voltage, ZTis the positive and negative sequence impedance of supply transformer HV/MV, ZL1,ZL2,ZL3 are positive and negative sequence impedances of individual parts of lines, ZDTS1 and ZDTS1 are positive and negative sequence impedances of DTs MV/LV in stations DTS1 and DTS2, Ifis the fault current, R p is the resistance of auxiliary resistor, G all is the total shunt conductance of affected distribution network, L SC is the arc-SC inductance, C all is the total capacitance of affected distribution network, and R f is the fault resistance. Considering an ideal compensated and no-load system, it is possible to derive equation for an approximate calculation of phase voltage US1 and US2 on the LV side of DTs DTS1 and DTS2 according to Figs. 1and 2. Fig. 2 Symmetrical components scheme of single-phase fault in compensated network Fig. 1 Way of a residual current through faulty line during EF in compensated network IET Gener. Transm. Distrib., 2015, Vol. 9, Iss. 14, pp. 2069–2077 2070 This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) A voltage on the secondary side of the MV/LV transformer can be generally expressed from the symmetrical components scheme by (1), respectively, (3) as follows: US=U(1) S+U(2) S(1) U(1) S=E−ZL·If/3  U(2) S=−ZL·If/3  (2) US=E−2 3ZL·If  , (3) where ZLis a sum of HV/LV transformer impedance and line impedances loaded by fault current between the power source (E) end appropriate transformer MV/LV. For calculation of voltage US1 according to Fig. 2the impedance is expressed as ZL=ZT+ZL1 +ZL3 and similarly for calculation of voltage US2 as ZL=ZT+ZL1. Fault current increasing by the connection of auxiliary resistor during an EF (SB is switched on) evokes voltage sag on the LV side of DTs ΔU S which can be expressed by the following equation DUS=USA     −USB      DUS=E−2 3ZL·IfA         −E−2 3ZL·IfB         (4) This equation describes the relation between magnitude of monitored voltage sags and its measuring points which is used by the algorithm for delimitation of faulty section. Equation (5) is result of maximal simplification of (4), when the impact of fault circuit reactance is neglected. This simplification was made only for illustrative description of the relation DUS≃2 3·RL·IfB−IfA  , (5) where index Aindicates a state without connected auxiliary resistor (SB is opened) and index Bindicates state when auxiliary resistor is connected (SB is closed). Fault current in the state without connected auxiliary resistor can be computed as IfA=3·E 2Z(1) +Z(0) +3Rf , (6) where Z(1) is the total positive-sequence impedance, Z(0) is the zero-sequence impedance which can be expressed according to Fig. 2as Z(0) =1 Gall +j v Call −(1/ v 3LSC)  1 Gall (7) Fault current when auxiliary resistor is connected can be similarly computed from the following equation IfB=3·E 2Z(1) +3Rp·Z(0)  /3Rp+Z(0)  +3Rf (8) Alternatively, when considering simplification as follows IfA=3·E 2R(1) +1 Gall +3Rf IfB=3·E 2R(1) +(Gall ·3Rp)/(Gall +3Rp)  +3Rf 3·E 2R(1) +3Rp+3Rf (9) As expressed in (5), the voltage sag is dependent on the fault current increasing due to the connection of the auxiliary resistor and also on the resistance R L (impedance ZL), i.e. on the length of monitored part of affected line corresponding to position of voltage monitor (relevant DTS). Therefore, the dependence is utilised by the method for the purpose of EF location inside affected compensated network. The proposed EF location method will be described in more detail in the following section. 2.2 Operation principle of the method for EF location If the voltage sags are monitored on the LV side of most of DTs which are deployed at the faulty feeder, then it is possible to determine faulty part of network without the need of using some necessary operation for sequential disconnection of individual sections of the line, as shown in Fig. 3. This figure presents a network when one of the feeders is affected by an EF and 11 DTSs, where voltage sag ΔU S is monitored. Based on the above mentioned theory, the highest voltage sag is reached at the MV/ LV stations placed behind the fault point (the longest part of faulty line is monitored) and the smallest value of the voltage sag can be measured in the stations in front of fault point closest to supply substation or in the stations placed on healthy feeders. First, before we compare recorded voltage sags on the LV side, it is necessary to correct their values due to different ratios of MV/ LV transformers. Fault location principle of the method is further explained on the example according to Fig. 3. Considering the EF in a marked spot in Fig. 3and also short-time connection of auxiliary resistor during the fault, the maximal voltage sag on the LV side is measurable at the stations DTS1, DTS2, and DTS3 with comparable level. Similarly for other farther DTS placed behind the fault where maximal voltage sag can be also monitored, because the fault current passes through the longest part of its feeding line, in this case line a+b+c+d+e (whole faulty line section from the supply substation to the fault point), therefore impedance ZLis maximal. Lower voltage sag is measurable in DTS4 and DTS5 where the fault current flows through the shorter part of their feeding line, in this case sections a+b+c+d. The voltage sag is comparable for both DTS in this case, because DTS4 and DTS5 monitor the same part of faulty Fig. 3 Operation principle of the method for EF location IET Gener. Transm. Distrib., 2015, Vol. 9, Iss. 14, pp. 2069–2077 2071This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) line. Similarly, DTS6 and DTS7 are fed by shorter part of faulty line which is section a+b+c. Hence the voltage sag at these stations is smaller. Analogously, as described in Fig. 3, the voltage sag at DTS9 and DTS8 is proportional to section a+b. The minimal voltage sag can be measured at DTS10 and DTS11 which are fed only by faulty section a. All stations located on unaffected feeders or directly connected to the supply substation 110/22 kV record the lowest voltage sag caused by voltage unbalance on the supply transformer due to fault current increasing after connection of auxiliary resistor. If voltage conditions are monitored in all available DTSs, it is possible to define stations behind and closest in front of the fault point based on mentioned principles. The fault point is located always in a section between the station(s) with maximal recorded voltage sag (DTS1, DTS2, and DTS3 according to Fig. 3) and the station(s) with the second highest value of voltage sag (DTS4 and DTS5). The accuracy of defined EF location is therefore given by the length of selected section which depends on the quantity and location of each DTS around the fault location. 2.3 Proposed fault location scheme A schematic description of the proposed EF location method is given in Fig. 5. Based on the diagram, RMS values of phase to neutral voltage are continuously monitored on the secondary side of MV/LV transformers. Assume that EF is occurred, the three-phase voltage RMS values (U SL1 ,U SL2 ,andU SL3 ) are recorded and collected. Subsequently, the voltage sag determination is done for all measuring points. In this process, voltage change of each phase ΔU SL1 ,ΔU SL2, and ΔU SL3 is calculated, as is shown in Fig. 4. The figure presents sample of RMS phase voltages recorded on secondary side of real DT during solid EF which was ignited in time 0 s and the auxiliary resistor was connected in time 2.5 s, for period 1 s. The auxiliary resistor was connected for 1 s. A voltage change waveform ΔU S is calculated as moving difference of values given by Frame 1 and Frame 2, where both frames calculate ten periods moving average of recorded phase voltages. Figs. 1and 2 are time-shifted by a time interval Δtwhich depends on network operation conditions and used time settings of auxiliary resistor automatics. The time interval 0.5 s (half period of auxiliary resistor connection) was chosen for an example showed in Fig. 4. Then, the voltage change waveforms of each phase ΔU SL1 ,ΔU SL1, and ΔU SL1 are processed to determinate maximal value of voltage sag ΔU SM x , where index xis a number of respective DTSs where the RMS voltage waveforms were recorded (x= 1 e.g. in Fig. 4). The ΔU SMx is minimal value subtracted from voltage change waveforms in time t MAX as it is depicted in Fig. 4when ΔU SM1 =−4.8 V. This time corresponds to the moment when the total voltage change ΔU ST given by the sum of all available voltage change waveforms of all monitored DTS is minimal. The waveform of total voltage change can be expressed by the following equation DUST = k x=1 (DUSL1 x+DUSL2 x+DUSL3 x), (10) where kis the number of all measuring points (monitored DTSs). As follows from Section 2.1, the maximal voltage sag occurs in a phase accordant with faulty phase, as it can be seen in Fig. 4, where EF in phase L3 occurred hence maximal voltage sag is in the same phase L3. The above described procedure is applied by analogy to all collected records to determination of the set M(11), which is used in the next step for voltage sag analyses to selection of DTS behind and closest in front of the EF point (Fig. 5). The set Mincludes the absolute values of maximal voltage sags of all measuring points which are corrected by a relevant DT ratio as follows: M=DUSM 1   ,DUSM 2   ,...,DUSM k     .(11) The DTS placed behind the EF are those which recorded the voltage sag belongs to set Bdefined as follows: B=b[M|m− d ≤b≤m{} max M=m(12) where mis the maximal value of all recorded maximal voltage sags belongs to Mand δis constant respecting measurement error or uncertainty of voltage sag evaluation in the distribution system. As well, DTSs placed close in front of an EF are subsequently selected as DTS where maximal voltage sag belongs to set F given by the equation F=f[M|n− d ≤f≤n  , (13) where nis maximal value of recorded maximal voltage sags belongs to set Nas follows: N=M\B n=max N(14) Fig. 4 Example of maximal voltage sag determination for selected DTS during real EF IET Gener. Transm. Distrib., 2015, Vol. 9, Iss. 14, pp. 2069–2077 2072 This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) Finally, a faulty area is delimited by DTS(s) with the voltage sag which belongs to set B, which is behind a fault point on the one side and by DTS(s) which is close in front of a fault point whose recorded voltage sag belongs to set Fon the other side, as follows from operation principle of the method described in Section 2.2. 3 Verification of the method –case study Simulation tool known as PSCAD Professional was used to model a part of 22 kV compensated distribution network that consists of six 22/0,4 kV DTSs equipped with voltage monitors on its LV side. Topology of the test network and position of each DTS were chosen to respect the most common topology of the Czech MV compensated networks. Simplified scheme of the network is depicted in Fig. 6. This test network is made up of part of the cable network (60 km) and from parts of overhead lines with total length 90.5 km. Supply substation 110/22 kV consists three outgoing feeders where feeder V1 is operated in basic state as radial with five prepared faulty points for the simulation of EFs F1–F5. Last predefined fault point F6 is situated in busbar of supply substation. Feeder V2 is designed so that it is possible to interconnected feeders V1 and V2 to ring connection with closing of switch OD for verification of the method during the ring configuration of the network as is shown in Fig. 6. Arc-SC is basically tuned to state when capacitive current 195 A of the network is ideally compensated. In this state, the fault current is compensated to value 18 A (residual current is up to 10% of network capacitive current). Resistance of auxiliary resistor R p for increasing of active part of fault current to maximising sensitivity of EF location was set to minimal value of resistance which is given the most widely used automatics in Czech distribution networks, the additional current after connection of the resistor is approximately 98 A. The auxiliary resistor is connected in 1.5 s after EF ignition for 1 s period, this also follows from the common setting of auxiliary resistor automatics used in the Czech distribution networks. 3.1 Faulty area delimitation for low-impedance EF Firstly, the method was verified during the simulation of low-impedance EF ignited at fault points F1–F6. This simulation represents a normal operation condition when all DTs are loaded to 30% of its rated power with power factor 0.95. Ratio of all DTs in modelled network was set to the some value therefore correction of recorded absolute values of maximal voltage sags by the relevant ratio were not necessary. In this case, EF with resistance 50 Ωwas considered in phase A (L1) and feeders V1 and V2 were operated radially (OD was switched off). Table 1shows absolute values of maximal voltage sags DUSM xrecorded at all measuring points (DTS1–DTS6) which were caused by additional connecting of auxiliary resistor analogous to the example in Fig. 4. Fig. 5 Schematic diagram of an EF location scheme Fig. 6 Simplified scheme of test compensated network IET Gener. Transm. Distrib., 2015, Vol. 9, Iss. 14, pp. 2069–2077 2073This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) Results of faulty section delimitation by the method respecting measurement error 0.2% of voltage monitors (i.e. δ= 0.46 V for nominal voltage 230 V) are noted in Table 1where DTSs behind EF, as follows from (12), are highlighted in bold and DTSs placed close in front of an EF are highlighted in italics as follows from (13). The column ‘section’shows a test network sections as shown in Fig. 7which were selected as faulty section by the method described in chapter 2. As follows from Table 1, all simulated EFs F1–F6 are inside the appropriate sections. For example, an EF F1 is located in section D, which was determined by the described method. According to Table 1, the faulty sections delimited by the method for EF points F1–F6 are depicted in Fig. 7. As explained above, the method based on voltage sag evaluation on the LV side of DT can be successfully used for delimitation of low-impedance EF in compensated network equipped by an auxiliary resistor. 3.2 Faulty area delimitation for high-impedance EFs The same test network configuration as in Section 3.1 was used for verification of the method during high-impedance EFs in phase A. During the test, the only fault resistance R f was changed in range from 50 Ωto 1.6 kΩfor all faulty points F1 up to F6. During the simulation, the maximal voltage sags at DTS1–DTS6 is recorded and the results of its evaluation for delimitation of faulty sections for EFs F1–F6 with fault resistance 600 Ωare shown in Table 2. As shows in Table 2for EF resistance 600 Ω, it is possible to correctly define faulty section for all simulated faults analogous to the case described in Section 3.1. The sensitivity of the proposed method is highly dependent on the level of fault current, and hence on the fault resistance. Table 3shows the results for higher values of fault resistance in the case of EF at the point F2. As given in Table 3, the faulty sections were correctly defined only for EF with fault resistance up to 800 Ω. Unfortunately, in case of higher fault resistances, it is not possible to reliably delimit the faulty section due to low level of voltage change, in this case the voltage sag. 3.3 Sensitivity of the method for under and over-compensated state Since during normal operation of compensated networks, it cannot be ensured ideal compensated state at all the time, the method was also evaluated during over-compensated and under-compensated Table 1 Recorded maximal voltage sags during low-impedance EF Phase A R f =50ΩDTS1 DTS2 DTS3 DTS4 DTS5 DTS6 Faulty area delimitation DUSM 1,V DUSM 2,V DUSM 3,V DUSM 4,V DUSM 5,V DUSM 6,V EF Section F1 −7.11 −12.81 −12.79 −12.77 −12.76 −0.60 D ✓ F2 −6.73 −12.36 −23.82 −18.26 −18.24 −0.63 G ✓ F3 −6.69 −12.29 −18.18 −23.59 −23.56 −0.63 H,I ✓ F4 −6.35 −11.74 −17.42 −27.94 −27.91 −0.61 H,I ✓ F5 −5.95 −11.05 −16.43 −26.47 −31.44 −0.59 K ✓ F6 0.00 0.00 0.00 0.00 0.00 0.00 A ✓ Fig. 7 Faulty sections delimited by the method during low-impedance EF Table 2 Recorded maximal voltage sags during 600 ΩEF at location F1 up to F6 Phase A R f = 600 ΩDTS1 DTS2 DTS3 DTS4 DTS5 DTS6 Faulty area delimitation DUSM 1,V DUSM 2,V DUSM 3,V DUSM 4,V DUSM 5,V DUSM 6,V EF Section F1 −1.05 −1.85 −1.84 −1.84 −1.84 −0.08 D ✓ F2 −1.10 −1.96 −3.69 −2.86 −2.86 −0.09 G ✓ F3 −1.11 −1.97 −2.88 −3.72 −3.71 −0.09 H,I ✓ F4 −1.13 −2.01 −2.94 −4.64 −4.63 −0.09 H,I ✓ F5 −1.13 −2.03 −2.97 −4.69 −5.56 −0.09 K ✓ F6 0.00 0.00 0.00 0.00 0.00 0.00 A ✓ IET Gener. Transm. Distrib., 2015, Vol. 9, Iss. 14, pp. 2069–2077 2074 This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) cases. In these cases, the arc-SC was mistuned by 15% of total capacitive current of the test network. As tabulated in Table 4, we compared the voltage sags during the two states of compensation, there it can be seen that higher sensitivity is achieved in the case of under-compensated state than in the over-compensated state. This conclusion is better apparent from the phase voltage waveforms as shown in Figs. 8and 9. Figs. 8and 9show waveforms of RMS values of phase voltage recorded on the LV side of DT during under-compensated state and over-compensated state. During these states, at the time 0.5 s EF was ignited and at time 2 s auxiliary resistor was connected for 1 s. Both figures present influence of compensation states on phase voltage level measured on the LV side of DT, where in the case of under-compensated distribution network the voltage is increased in Table 3 Recorded maximal voltage sags during impedance EF at location F2 EF F2 DTS1 DTS2 DTS3 DTS4 DTS5 DTS6 Faulty area delimitation DUSM 1,V DUSM 2,V DUSM 3,V DUSM 4,V DUSM 5,V DUSM 6,V R f ,ΩSection 50 −6.73 −12.36 −23.82 −18.26 −18.24 −0.63 G ✓ 200 −3.35 −6.06 −11.54 −8.90 −8.89 −0.29 G ✓ 400 −1.77 −3.16 −5.98 −4.63 −4.63 −0.14 G ✓ 600 −1.10 −1.96 −3.69 −2.86 −2.86 −0.09 G ✓ 800 −0.76 −1.34 −2.52 −1.95 −1.96 −0.06 G ✓ 1000 −0.56 −0.97 −1.82 −1.42 −1.42 −0.04 –× 1600 −0.27 −0.47 −0.87 −0.68 −0.68 −0.02 –× Table 4 Recorded maximal voltage sags during 50 ΩEF at locations F1–F6 for under-compensated (under), over-compensated (over), and ideally compensated state (ideal) Phase A R f = 600 ΩDTS1 DTS2 DTS3 DTS4 DTS5 DTS6 Faulty area delimitation Compensation DUSM 1,V DUSM 2,V DUSM 3,V DUSM 4,V DUSM 5,V DUSM 6, V Section F1 ideal −7.11 −12.81 −12.79 −12.77 −12.76 −0.60 D ✓ under −8.24 −15.09 −15.06 −15.04 −15.02 −0.78 D ✓ over −5.58 −9.95 −9.93 −9.92 −9.91 −0.44 D ✓ F2 ideal −6.73 −12.36 −23.82 −18.26 −18.24 −0.63 G ✓ under −7.94 −14.89 −29.19 −22.18 −22.15 −0.82 G ✓ over −5.07 −9.22 −17.67 −13.59 −13.57 −0.44 G ✓ F3 ideal −6.69 −12.29 −18.18 −23.59 −23.56 −0.63 H,I ✓ under −7.87 −14.77 −22.03 −28.79 −28.76 −0.82 H,I ✓ over −5.05 −9.18 −13.55 −17.54 −17.53 −0.44 H,I ✓ F4 ideal −6.35 −11.74 −17.42 −27.94 −27.91 −0.61 H,I ✓ under −7.41 −14.04 −21.03 −34.38 −34.34 −0.80 H,I ✓ over −4.71 −8.61 −12.75 −20.35 −20.33 −0.43 H,I ✓ F5 ideal −5.95 −11.05 −16.43 −26.47 −31.44 −0.59 K ✓ under −6.81 −13.02 −19.58 −32.28 −38.56 −0.76 K ✓ over −4.34 −7.97 −11.80 −18.92 −22.47 −0.41 K ✓ F6 ideal 0.00 0.00 0.00 0.00 0.00 0.00 A ✓ under 0.00 0.00 0.00 0.00 0.00 0.00 A ✓ over 0.00 0.00 0.00 0.00 0.00 0.00 A ✓ Fig. 8 RMS phase voltage waveforms on the LV side of DT during EF in phase A for under-compensated state Fig. 9 RMS phase voltage waveforms on the LV side of DT during EF in phase A for over-compensated state IET Gener. Transm. Distrib., 2015, Vol. 9, Iss. 14, pp. 2069–2077 2075This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/) the phase which is leading faulty phase as shown in Fig. 8. However, in the case of over-compensated state, the phase voltage values of the faulty phase and also phase leading faulty phase is decreased as depicted in Fig. 9. The voltage sag caused by EF during over-compensated state limits the evaluated maximal voltage sags thereby reducing the sensitivity of the method as seen from Table 4where the highest values of maximal voltage sag were recorded during under-compensated state and lowest for over-compensated state. The influence of the capacitive current compensation to the voltage condition in MV network and also in LV network is shown in Fig. 10, where Iaic is phase current of no-load faulty feeder in the state of ideally compensated EF in phase A (index ‘ic’). If the arc-SC is going to under-compensated state (index ‘uc’), the phasor Iaic is phase shifted counter clockwise to the position of phasor Iauc (15% under-compensated state). The under-compensated current Iauc is cause of voltage drop DUauc, which shifts the peak of the symmetrical triangle from point A0´ to point A2. Point A0´ is the vertex of the triangle of symmetric line-to-line voltage phasors UPab and UPca at supply substation and point A2 is the vertex of the triangle of symmetric line-to-line voltage phasors at measuring point of faulty line. Otherwise, when the arc-SC is passing to over-compensated state (index ‘oc’), the original phasor Iaic is shifted clockwise, and the current Iaoc flowing through faulty phase causes voltage drop DUaoc, which shifts the peak of the symmetrical triangle from point A0´ to point A1. 4 Conclusion Based on the simulation results, it is confirmed that the principle of the described method is useful for delimiting of faulty section in compensated networks during solid and low-impedance EFs. Since the sensitivity of the method strongly depends on the fault current level and thus on a fault resistance, the sensitivity of faulty section definition during high-impedance EF is very low. It may disable faulty section delimitation or lead to definition of an incorrect section which is not affected by the fault, especially during EF with fault resistance over 800 Ω. The advantage of the method is the possibility of its using for definition of faulty section which is affected by any type of asymmetrical faults, such as single-phase short-circuit in effectively or resistance earthed networks, line-to-line or also line-to-line to ground short-circuits, whereas the length of the defined section is dependent on the number and location of monitored DTSs and on the level of fault current. The requirement for a large number of DTSs to delimitation of the shortest faulty section and similarly the requirement for high value of fault current predetermine the method for use in urban or sub-urban MV distribution networks characterised by a high density of DTS location and higher fault current level (low fault loop impedance). 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