Single CFOA-based active Negative Group Delay circuits for signal anticipation

Engineering Science and Technology, an International Journal 48 (2023) 101590 2215-0986/© 2023 The Authors. Published by Elsevier B.V. on behalf of Karabuk University This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/). Contents lists available at ScienceDirect Engineering Science and Technology, an International Journal journal homepage: www.elsevier.com/locate/jestch Full length article Single CFOA-based active Negative Group Delay circuits for signal anticipation Onat Baloglu a, Oguzhan Cicekoglu a, Norbert Herencsar b,∗ aDepartment of Electrical and Electronics Engineering, Bogazici University, Bebek/Istanbul, 34342, Turkey bDepartment of Telecommunications, Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 3082/12, 61600 Brno, Czech Republic ARTICLE INFO Keywords: Audio signal processing Current feedback operation amplifier Design method Negative Group Delay NGD Time-domain validation ABSTRACT The group delay of a signal prior to data monitoring is a crucial consideration in today’s real-time applications, especially for those that involve long sensor arrays or high-order filters. In this article, nine new second-order Negative Group Delay (NGD) circuits based on Current Feedback Operation Amplifier (CFOA) are proposed, and their transfer functions are demonstrated. These circuits have a wide range of applications, from audio to mechanical signals and sensor signal anticipation. An example design procedure is provided for one of the introduced circuits. A time-domain analysis is performed using both a single-tone sinusoidal and a band-limited audio recording in the frequency range of 1 Hz to 500 Hz. The article assesses the change in the signal using Root Mean Square Error (RMSE) and cross-correlation. Furthermore, the relationship between the NGD value and the operation range of the circuit is investigated and verified experimentally. The results show that an NGD value of approximately 100 μs can be achieved with an amplitude error of 0.86% for a single-tone input and 1.54% for an audio recording, and an operation range of about 650 Hz. 1. Introduction Negative Group Delay (NGD) is an intriguing physical phenomenon that can be utilized for signal prediction. In these circuits, the output visually appears to be time-advanced compared to the input, making signal prediction possible, but this effect does not violate the causality principle [1]. The crucial aspect is that the input signal must be band-limited, meaning that sudden jumps in the input signal are not allowed, and the derivatives of the input signal must remain bounded. Furthermore, NGD typically occurs within a specific frequency band in these circuits [2]. Although NGD can be observed in passive circuits, active elements are necessary if the output signal is to be used to drive other circuits or systems. The phase delay of a system refers to the phase shift of the single sinusoidal input to the output of that system, while the group delay denotes the time delay of the signal envelope. Group delay is an important term for systems that process signals with multiple frequency components, which is the norm in realworld applications [3]. A nonlinear group delay means that different phase delays occur for the different frequency components of the input, resulting in distortion in the output. There have been studies of NGD in both physics and electronics disciplines. The causality and applicability of NGD, as well as its physical aspects, are discussed in Refs. [4–9], ∗Corresponding author. E-mail addresses: [email protected] (O. Baloglu), [email protected] (O. Cicekoglu), [email protected] (N. Herencsar). which show that the system does not violate causality. The output is a reshaped signal such that its peak is ahead of the input. In this article, we presented nine new second-order single Current Feedback Operation Amplifier (CFOA)-based NGD circuits, obtained by computer-aided design method [10], which may be useful for communication or control applications. Section 2introduces the NGD circuit theory, describes the CFOA, a literature review of active NGD topologies, and presents the new circuits. Section 3describes the circuit design method, while a non-ideal study of a selected NGD circuit is given in Section 4. Section 5is focused on the simulation and experimental validations. Performance comparison with selected stateof-the-art solutions is shown in Section 6. Finally, Section 7concludes the study. 2. Description of the theory, CFOA, and active NGD topologies This section introduces the NGD circuit theory. The description of the CFOA and the literature review of active NGD topologies are presented. https://doi.org/10.1016/j.jestch.2023.101590 Received 6 August 2023; Received in revised form 10 November 2023; Accepted 24 November 2023 Engineering Science and Technology, an International Journal 48 (2023) 101590 2 O. Baloglu et al. Fig. 1. (a) Phase response example of a stable NGD circuit and (b) its group delay. Table 1 The NGD circuit topologies in the literature. Reference Circuit topology Transfer function [6] OA Based Active RLC Filter 𝑏2𝑠2+𝑏1𝑠+𝑏0 𝑎2𝑠2+𝑎1𝑠+𝑎0 , 𝑎1=𝑏1, 𝑎0=𝑏0 [11] Passive RLC Network (𝑎1𝑏0+ 1)𝑏1𝑠+𝑎1 𝑏1𝑎1𝑠 [12] OA Based Differentiator 𝑏1𝑠+𝑏0 [14,17] Passive RC Filter 𝑏1𝑠+𝑏0 𝑏1𝑠+𝑎0+𝑏0 [15] OA Based Active RC Filter 𝑏1𝑠+𝑏0 𝑎1𝑠+𝑎0 [16] Cascaded CFOA-Based Active Filter 𝑏2𝑠2+𝑏1𝑠+𝑏0 𝑎1𝑠+𝑎0 2.1. Theory and mathematical description In a linear time-invariant (LTI) system, for the output 𝑦and the input 𝑥, the transfer function (TF) of the system is given as (1). 𝐻(𝑗𝜔) = 𝑌(𝑗𝜔) 𝑋(𝑗𝜔),(1) where 𝑌(𝑗𝜔)and 𝑋(𝑗𝜔)are the output and the input signal’s Laplace transforms, with (𝑠←←→ 𝑗𝜔), respectively. For the given system TF, the phase and group delay are respectively defined as (2) and (3). 𝜙(𝜔) = arg [𝐻(𝑗𝜔)]= arg(𝑌) − arg(𝑋),(2) 𝜏𝑔(𝜔)=−𝑑𝜙(𝜔) 𝑑𝜔 .(3) Eq. (3) indicates that a phase that increases monotonically with frequency results in a negative group delay. This, however, implies an unstable system. A stable system with negative group delay may have a phase response as shown in Fig. 1, where the phase increases to a certain point and then decreases. In this case, the group delay is negative as long as the phase is increasing with frequency [11]. The summary of the previously proposed NGD circuit (NGDC) topologies can be found in Table 1. An intriguing electronic circuit with negative group delay is presented in [12]. There have been several studies on NGD systems utilizing active RC and RLC filters with operational amplifiers (OA) [6,12,13]; passive RC and RLC networks [11,14]; or through mathematical modeling of NGD-based circuits using Taylor series prediction [15]. Only one topology is a cascadable NGD circuit based on CFOA [16]. The NGD values reported in the studies vary from ns to μs. In the next section, novel CFOA-based active NGDCs will be introduced, followed by a design and application example. 2.2. The CFOA and proposed active NGD topologies The mathematical description of the CFOA is given in (4) [18]. ⎡⎢⎢⎣ 𝑣− 𝑖Z 𝑣W⎤⎥⎥⎦ =⎡⎢⎢⎣ 100 010 001⎤⎥⎥⎦⎡⎢⎢⎣ 𝑣+ 𝑖− 𝑣Z⎤⎥⎥⎦ .(4) This article introduces nine novel circuits obtained by computeraided design method [10]. In Fig. 2, all presented circuits have a second-order TF using five passive components, as listed in Table 2. Although, in practice, circuits employing only grounded capacitors are preferred, new IC technologies offer floating capacitor realization possibility as a double poly (poly1-poly2) or metal–insulator–metal (MIM) capacitor [19]. Alternatively, P-channel MOS (PMOS) varactors also implement floating capacitors [3]. In the introduced CFOA-based NGD circuits, the highest-order 𝑠parameter coefficient in the denominator has the same value as the highest-order 𝑠parameter coefficient in the numerator. Moreover, the coefficient of the denominator’s 𝑠parameter can always be made smaller than the coefficient of the numerator’s 𝑠 parameter. The general TF for the second-order 𝐻2(𝑠)system is given by (5). 𝐻2(𝑠) = 𝑎0+𝑎1𝑠+𝑎2𝑠2 𝑏0+𝑏1𝑠+𝑏2𝑠2,(5) while from (5), the phase and group delay responses can be expressed as (6) and (7): 𝜙2(𝜔) = arg [𝐻2(𝑗𝜔)]= arctan (𝑎1𝜔 𝑎0−𝑎2𝜔2)− arctan (𝑏1𝜔 𝑏0−𝑏2𝜔2),(6) 𝜏𝑔2(𝜔)=−𝑑𝜙2(𝜔) 𝑑𝜔 .(7) NGD can be achieved in the second-order TFs where 𝑎1is smaller than 𝑏1and both are positive numbers. The operation ranges and parameters are defined in the design section. 3. NGD circuit design method This section describes a CFOA-based NGD circuit synthesis method. After the topological description, the detailed NGD analysis is introduced. 3.1. Description of the design example The circuit shown in Fig. 2(a) has been selected as an example to demonstrate the design method. Its TF is given in (8). 𝐻2(a)(𝑠) = 𝐺1𝐺2+𝐺1𝐺3+𝐶1𝐺1𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺3+ (𝐶1𝐺1−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2.(8) 3.1.1. Stability constraints First, the stability constraints of the circuit are determined. The stability condition for the TF given in (8) can be found in (9). 𝐶1𝑅2> 𝐶2𝑅1.(9) 3.1.2. The phase and group delay calculation The phase response of the system can be expressed as (10). 𝜙2(a)(𝜔) = arctan (𝐶1𝐺1𝜔 𝐺1𝐺2+𝐺1𝐺3−𝐶1𝐶2𝜔2) − arctan ((𝐶1𝐺1−𝐶2𝐺2)𝜔 𝐺1𝐺3−𝐶1𝐶2𝜔2). (10) Using (3) and (10), the group delay is given in (11). 𝜏𝑔2(a)(𝜔) = (𝐶1𝐺1−𝐶2𝐺2)(𝐺1𝐺3+𝐶1𝐶2𝜔2) (𝐶1𝐺1−𝐶2𝐺2)2𝜔2+ (𝐺1𝐺3−𝐶1𝐶2𝜔2)2 −𝐶1𝐺1[𝐺1(𝐺2+𝐺3) + 𝐶1𝐶2𝜔2] 𝐶2 1𝐺2 1𝜔2+ [𝐺1(𝐺2+𝐺3) − 𝐶1𝐶2𝜔2]2. (11) In the design parameters section, the component values are selected to meet the conditions (12) at low frequencies. 𝐶1𝐺1𝜔 𝐺1𝐺2+𝐺1𝐺3−𝐶1𝐶2𝜔2<1,(𝐶1𝐺1−𝐶2𝐺2)𝜔 𝐺1𝐺3−𝐶1𝐶2𝜔2<1.(12) Engineering Science and Technology, an International Journal 48 (2023) 101590 3 O. Baloglu et al. Fig. 2. (a)–(i) Proposed second-order NGD circuits. Table 2 The transfer functions 𝐻(𝑠)of proposed second-order circuits, depicted in Fig. 2, 1/Gn= Rn. Circuit Transfer function Matching condition # Passive components (a) 𝐺1𝐺2+𝐺1𝐺3+𝐶1𝐺1𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺3+ (𝐶1𝐺1−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1> 𝐶2𝐺25 (b) 𝐺1𝐺2+𝐺2𝐺3+ (𝐶1𝐺2+𝐶2𝐺1)𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺2+ (𝐶1𝐺2+𝐶2𝐺1−𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺2+𝐶2𝐺1> 𝐶2𝐺35 (c) 𝐺1𝐺2+𝐶1𝐺1𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺3−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺3> 𝐶2𝐺25 (d) 𝐺1𝐺2+ 2𝐺1𝐺3+𝐶1𝐺1𝑠+𝐶1𝐶2𝑠2 2𝐺1𝐺3+ (𝐶1𝐺1−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1> 𝐶2𝐺25 (e) 𝐺1𝐺3+𝐺1𝐺2+ (𝐶1𝐺1+𝐶1𝐺3)𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺3−𝐺2𝐺3+ (𝐶1𝐺1+𝐶1𝐺3−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶1𝐺3> 𝐶2𝐺2;𝐺1> 𝐺25 (f) 𝐺1𝐺3+𝐺1𝐺2+ (𝐶1𝐺1+𝐶2𝐺1+𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1+𝐶2𝐺3−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺1+𝐶2𝐺3> 𝐶2𝐺25 (g) 𝐺1𝐺2+𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1)𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺1> 𝐶2𝐺25 (h) 𝐺1𝐺2+ (𝐶1𝐺1+𝐶2𝐺1)𝑠+𝐶1𝐶2𝑠2 𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1−𝐶2𝐺2+𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺1+𝐶2𝐺3> 𝐶2𝐺25 (i) 𝐺1𝐺2+ 2𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1)𝑠+𝐶1𝐶2𝑠2 2𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1−𝐶2𝐺2)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺1> 𝐶2𝐺25 The values of the capacitors are in the order of 10−9Farads, while the conductance values are in the order of 10−4Siemens. The phase response in (10) is approximated as (13): 𝜙2(a)(𝜔) ≅ 𝐶1𝐺1𝜔 𝐺1𝐺2+𝐺1𝐺3−𝐶1𝐶2𝜔2−(𝐶1𝐺1−𝐶2𝐺2)𝜔 𝐺1𝐺3−𝐶1𝐶2𝜔2.(13) 3.1.3. Zero cross frequency calculation Using (3) and (13), the approximate group delay can be expressed as (14). 𝜏𝑔2(a)(𝜔) = (𝐶1𝐺1−𝐶2𝐺2)(𝐺1𝐺3+𝐶1𝐶2𝜔2) (𝐶1𝐶2𝜔2−𝐺1𝐺3)2 −𝐺1𝐶1(𝐺1𝐺2+𝐺1𝐺3+𝐶1𝐶2𝜔2) (𝐶1𝐶2𝜔2−𝐺1𝐺2−𝐺1𝐺3)2 (14) The first term of (14) is positive at low frequencies in accordance with the stability condition (9). Meanwhile, the second term of (14) is negative at low frequencies. The second term of (14) is the dominant factor in our case in terms of the NGD value, and it is assumed to determine the frequency where the group delay changes from negative to positive. The frequency at which the group delay changes from negative to positive is estimated by finding the root of the denominator of the second term and is given in (15). 𝜔𝑧𝑒𝑟𝑜_𝑐𝑟𝑜𝑠𝑠_2(a) ≅√𝑅2+𝑅3 𝑅1𝑅2𝑅3𝐶1𝐶2 .(15) Note that this is a rough estimate of the zero crossing frequency and does not give its actual value. The exact value can be determined from the simulation graph. Considering above given conditions and to simplify the design complexity, (14) is reduced to (16). This reduced form is used in the group delay calculations within the stability region. 𝜏𝑔2(a)(𝜔) ≅ − 𝐶1𝐺1 𝐺1𝐺3+𝐺1𝐺2−𝐶1𝐶2𝜔2+𝐶1𝐺1−𝐶2𝐺2 𝐺1𝐺3−𝐶1𝐶2𝜔2.(16) Engineering Science and Technology, an International Journal 48 (2023) 101590 4 O. Baloglu et al. At low frequencies, the group delay becomes as in (17): 𝜏𝑔2(a)(𝜔)≅− 𝐶1𝐺1 𝐺1𝐺3+𝐺1𝐺2 +𝐶1𝐺1−𝐶2𝐺2 𝐺1𝐺3 .(17) 3.2. Design simplification & constraints To simplify the calculation of NGD, equal resistances are selected, as expressed by Eq. (18): 𝑅1=𝑅2=𝑅3.(18) Moreover, the capacitance values are selected as: 𝐶2=𝛼𝐶1,where 0< 𝛼 ≤1.(19) By rearranging Eqs. (15) and (17) with the assumption of equal resistor values, the expressions (20) are obtained. 𝜏𝑔2(a)(𝜔) ≅ 𝐶1𝑅1(1 2−𝛼), 𝜔𝑧𝑒𝑟𝑜_𝑐𝑟𝑜𝑠𝑠_2(a) ≅√2 𝛼 1 𝑅1𝐶1 .(20) The magnitude of the NGD decreases as the operating frequency increases. Therefore, it is necessary to maximize the magnitude of both values at the same time when the group delay is negative. 3.3. Performance metric The zero crossing of the NGD function is given in (15), where the NGD value changes from negative to positive at that frequency. Therefore, a Figure of Merit (FoM) is determined as [17]: FoM =𝜔𝑧𝑒𝑟𝑜_𝑐𝑟𝑜𝑠𝑠_2(a) ×𝜏𝑔2(a)(𝜔) ≅ √2 𝛼(1 2−𝛼),(21) where 0< 𝛼 ≤1. Note that the product of the zero crossing point and the NGD value is given in (21). By minimizing (21), the NGD can be achieved when 𝛼= 1, which is the stability margin point where the two capacitors are equal in value. Eq. (21) also shows that the stability boundary occurs where the magnitude of the NGD value and the operating frequency range are maximized. To achieve a stable system, 𝑅2is selected to be larger than 𝑅1, when the capacitors are selected equal valued. The parameters for this selection are introduced in the Section 5. It is important to note that in some cases, the gain can be reduced to zero when the group delay is negative. Therefore, the gain of the system at low frequencies is expressed as (22): |𝐻(𝜔≅ 0)|≅ 1 + 𝑅3 𝑅2 .(22) Eq. (22) shows that a gain exists in the frequencies of operation where NGD is achieved. 4. Non-ideal and parasitic effects analysis The present section is focused on a non-ideal study of the proposed NGD circuit. 4.1. Description of non-ideal CFOA An equivalent non-ideal circuit of CFOA, including parasitic impedance, is shown in Fig. 3. Using standard notation, relations between its individual terminals can be described by the following hybrid matrix (23): ⎡⎢⎢⎢⎢⎣ 𝑖+ 𝑣− 𝑖Z 𝑣W ⎤⎥⎥⎥⎥⎦ =⎡⎢⎢⎢⎢⎣ 𝑌+0 0 0 𝛽(𝑠)𝑍−0 0 0𝛼(𝑠)𝑌Z0 0 0 𝛾(𝑠)𝑍W ⎤⎥⎥⎥⎥⎦ ⎡⎢⎢⎢⎢⎣ 𝑣+ 𝑖− 𝑣Z 𝑖W ⎤⎥⎥⎥⎥⎦ ,(23) where 𝑌+=𝑠𝐶++ 1∕𝑅+,𝑌Z=𝑠𝐶Z+ 1∕𝑅Zare parasitic admittances and 𝑍𝑘=𝑅𝑘(𝑘= − and W) are the parasitic resistances at relevant Fig. 3. An equivalent non-ideal circuit of CFOA including parasitic impedances. terminals of the CFOA, respectively. Parameters 𝛼(𝑠),𝛽(𝑠), and 𝛾(𝑠)are, respectively, frequency-dependent non-ideal current and voltage gains. Ideally, these parameters are equal to unity. Using a single-pole model, they can be defined as (24): 𝛼(𝑠) = 𝛼o 1 + 𝜏𝛼𝑠, 𝛽(𝑠) = 𝛽o 1 + 𝜏𝛽𝑠, 𝛾(𝑠) = 𝛾o 1 + 𝜏𝛾𝑠.(24) Here, 𝛼ois DC current, and 𝛽oand 𝛾oare DC voltage gains of the CFOA, respectively. The bandwidths 1∕𝜏𝛼,1∕𝜏𝛽, and 1∕𝜏𝛾depend on the fabrication of devices. In current technologies, also used for the fabrication of Analog Devices AD844AN [20], the order of a few gigarad/s is ideally equal to infinity. Hence, at low and medium frequencies, i.e., 𝑓 ≪ (1∕(2𝜋)) × min{1∕𝜏𝛼,1∕𝜏𝛽,1∕𝜏𝛾},(24) becomes: 𝛼(𝑠) ≅ 𝛼= 1 + 𝜀𝛼i, 𝛽(𝑠) ≅ 𝛽= 1 + 𝜀𝛽v, 𝛾(𝑠) ≅ 𝛾= 1 + 𝜀𝛾v,(25) whereas 𝜀𝛼i,𝜀𝛽v, and 𝜀𝛾vare current and voltage tracking errors, respectively, and satisfy the inequalities |𝜀𝛼i|≪1,|𝜀𝛽v|≪1, and |𝜀𝛾v|≪1. Considering the non-ideal current and voltage gains of the CFOA and re-analyzing the proposed circuits depicted in Fig. 2, a routine analysis yields non-ideal TFs of the circuits, presented in Table 3. 4.2. Non-ideal analysis of the design example For a complete analysis of the circuit, it is also important to consider in detail the non-idealities of the readily available CFOA device Analog Devices AD844AN [20], as also shown in Fig. 3, where: •the parasitic resistance 𝑅+and parasitic capacitance 𝐶+appear between the high-impedance terminal +of the CFOA and ground and their values are 𝑅+= 10 M𝛺∥𝐶+= 2 pF, respectively, •the non-zero parasitic resistance 𝑅−at current input terminal − has value 𝑅−= 50 𝛺, •the parasitic resistance 𝑅Zand parasitic capacitance 𝐶Zappear between the auxiliary terminal Zof the CFOA and ground and their values are 𝑅Z= 3 M𝛺∥𝐶Z= 4.5pF, respectively, •the non-zero parasitic resistance 𝑅Wat voltage output terminal Whas value 𝑅W= 15 𝛺. Taking into account the non-ideal current and voltage gains of the CFOA and simultaneously the effect of non-idealities as mentioned above and re-analyzing the proposed NGD circuit shown in Fig. 2(a), the coefficients 𝑎𝑚and 𝑏𝑚for 𝑚= {0,1,2} of non-ideal TF 𝐻′′ 2(a)(𝑠), phase 𝜙′′ 2(a)(𝜔), and group delay 𝜏′′ 𝑔2(𝜔)responses in (5)–(7) are as Engineering Science and Technology, an International Journal 48 (2023) 101590 5 O. Baloglu et al. Table 3 Non-ideal transfer functions 𝐻′(𝑠)of proposed second-order circuits, depicted in Fig. 2, 1/Gn= Rn. Circuit Transfer function Matching condition # Passive components (a) 𝛾(𝛼𝛽𝐺1𝐺2+𝛼𝛽𝐺1𝐺3+𝐶1𝐺1𝑠+𝐶1𝐶2𝑠2) 𝛼𝛾𝐺1𝐺3+ [𝐶1𝐺1−𝛼𝛽𝛾𝐶2𝐺2+𝛼𝛾𝐶2𝐺3(1 − 𝛽)]𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝛼𝛾𝐶2𝐺3> 𝛼𝛽𝛾𝐶2(𝐺2+𝐺3)5 (b) 𝛾[𝐺1𝐺2+𝛼𝛽𝐺2𝐺3+ (𝐶2𝐺1+𝐶1𝐺2)𝑠+𝐶1𝐶2𝑠2] 𝐺1𝐺2+ (𝐶1𝐺2+𝐶2𝐺1−𝛼𝛽𝛾𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺2+𝐶2𝐺1> 𝛼𝛽𝛾𝐶2𝐺35 (c) 𝛾(𝛼𝛽𝐺1𝐺2+𝐶1𝐺1𝑠+𝐶1𝐶2𝑠2) 𝐺1𝐺3+ (𝐶1𝐺1−𝛼𝛽𝛾𝐶2𝐺2+𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺3> 𝛼𝛽𝛾𝐶2𝐺25 (d) 𝛾(𝛼𝛽𝐺1𝐺2+𝛽𝐺1𝐺3+𝛼𝛽𝐺1𝐺3+𝐶1𝐺1𝑠+𝐶1𝐶2𝑠2) 𝐺1𝐺3+𝛼𝐺1𝐺3+ [𝐶1𝐺1−𝛼𝛽𝛾𝐶2𝐺2+𝐶2𝐺3(1 + 𝛼−𝛽𝛾 −𝛼𝛽𝛾)]𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺3(1 + 𝛼)> 𝛽𝛾𝐶2[𝛼(𝐺2+𝐺3) + 𝐺3]5 (e) 𝛾[𝛼𝛽𝐺1𝐺2+𝐺1𝐺3+ (𝐶1𝐺1+𝐶1𝐺3)𝑠+𝐶1𝐶2𝑠2] 𝐺1𝐺3−𝛼𝛽𝐺2𝐺3+ [𝐶1𝐺1−𝛼𝛽𝛾𝐶2𝐺2+𝐶1𝐺3+𝐶2𝐺3(1 − 𝛾)]𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶1𝐺3+𝐶2𝐺3> 𝛾𝐶2(𝛼𝛽𝐺2+𝐺3);𝐺1> 𝛼𝛽𝐺25 (f) 𝛾[𝛼𝛽𝐺1𝐺2+𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1+𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2] 𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1−𝛼𝛽𝐶2𝐺2+𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺1+𝐶2𝐺3> 𝛼𝛽𝐶2𝐺25 (g) 𝛾[𝛼𝛽𝐺1𝐺2+𝛼𝛽𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1)𝑠+𝐶1𝐶2𝑠2] 𝛼𝛾𝐺1𝐺3+ [𝐶1𝐺1+𝐶2𝐺1−𝛼𝛽𝐶2𝐺2−𝛼𝐶2𝐺3(𝛽−𝛾)]𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺1+𝛼𝛾𝐶2𝐺3> 𝛼𝛽𝐶2(𝐺2+𝐺3)5 (h) 𝛾[𝛼𝛽𝐺1𝐺2+ (𝐶1𝐺1+𝐶2𝐺1)𝑠+𝐶1𝐶2𝑠2] 𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1−𝛼𝛽𝐶2𝐺2+𝐶2𝐺3)𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2𝐺1+𝐶2𝐺3> 𝛼𝛽𝐶2𝐺25 (i) 𝛾[𝛼𝛽𝐺1𝐺2+𝛽𝐺1𝐺3+𝛼𝛽𝐺1𝐺3+ (𝐶1𝐺1+𝐶2𝐺1)𝑠+𝐶1𝐶2𝑠2] 𝐺1𝐺3+𝛼𝐺1𝐺3+ [𝐶1𝐺1+𝐶2𝐺1−𝛼𝛽𝐶2𝐺2+𝐶2𝐺3(1 + 𝛼−𝛽−𝛼𝛽]𝑠+𝐶1𝐶2𝑠2𝐶1𝐺1+𝐶2[𝐺1+𝐺3(1 + 𝛼)] > 𝛽𝐶2[𝛼(𝐺2+𝐺3) + 𝐺3]5 𝑎0=𝛽𝐺1[𝛼𝛾(𝐺2+𝐺3) + 𝐺3𝐺Z𝑅W], 𝑎1=𝛾𝐶1(𝐺1+𝐺+)(𝐺2𝑅−+𝐺3𝑅−+ 1) + 𝐺1𝑅W[𝛽𝐺3(𝐶1+𝐶Z) + 𝐶2𝐺Z(1 + 𝐺2𝑅−+𝐺3𝑅−)], 𝑎2= (𝐺2𝑅−+𝐺3𝑅−+ 1)[𝛾𝐶1(𝐶2+𝐶+) + 𝐶2𝐺1𝑅W(𝐶1+𝐶Z)], 𝑏0= (𝐺1+𝐺+)(𝐺Z+𝛼𝛾𝐺3+𝐺2𝐺Z𝑅−+𝐺3𝐺Z𝑅W+𝐺2𝐺3𝐺Z𝑅W𝑅−+𝐺3𝐺Z𝑅−), 𝑏1=𝐺3{𝑅−{𝑅W{𝐺Z[𝐶2(𝐺1+𝐺2+𝐺+) + 𝐺2𝐶+] + 𝐺2(𝐶1+𝐶Z)(𝐺1+𝐺+)} + 𝐺Z(𝐶2+𝐶+)+(𝐶1+𝐶Z)(𝐺1+𝐺+)} +𝑅W{𝐺Z[𝐶2(1 − 𝛽) + 𝐶+]+(𝐶1+𝐶Z)(𝐺1+𝐺+)} − 𝛼𝛾[𝐶2(𝛽− 1) − 𝐶+]} + 𝐺2𝑅−[𝐶2𝐺Z𝑅W(𝐺1+𝐺+) +𝐺Z(𝐶2+𝐶+)+(𝐶1+𝐶Z)(𝐺1+𝐺+)] + 𝐶2𝐺Z𝑅W(𝐺1+𝐺+) + 𝐺Z(𝐶2+𝐶+) − 𝛼𝛽𝛾𝐶2𝐺2+ (𝐶1+𝐶Z)(𝐺1+𝐺+), 𝑏2=𝐶2{𝑅W{𝑅−{𝐺3[(𝐺1+𝐺2+𝐺+)(𝐶1+𝐶Z) + 𝐺Z𝐶+] + 𝐺2[(𝐺1+𝐺+)(𝐶1+𝐶Z) + 𝐶+𝐺Z]} − 𝐺3(𝐶1+𝐶Z)(𝛽− 1) + (𝐺1+𝐺+)(𝐶1+𝐶Z) + 𝐶+𝐺Z} + (1 + (𝐺2+𝐺3)𝑅−)(𝐶1+𝐶Z)} + 𝐶+(𝐶1+𝐶Z)[𝐺3𝑅W(𝐺2𝑅−+ 1) + 𝑅−(𝐺2+𝐺3) + 1]. (26) Box I. in Box I. The effect of non-idealities on the proposed NGD circuit can be significantly minimized by properly selecting external passive components and/or by the precise design of the CFOA. 5. Simulations and experimental validations The present section is focused on the simulation and experimental validations. 5.1. Simulation results In Fig. 4, it is shown that the negative group delay is almost constant in the stability region with constant 𝑅3. The empty space on the right part of the plot represents positive group delay, while the empty space on the left side represents the unstable region. Additionally, when 𝑅1 and 𝑅2are equal, 𝑅3affects the group delay value. However, it can be seen in Fig. 4 that 𝑅3does not affect whether the group delay is positive or negative when 𝑅1and 𝑅2are equal. For design purposes, let us also assume 𝑅3is equal to 𝑅1and 𝑅2as a starting point. This results in the flexibility of achieving NGD with the single parameter 𝐶1=𝐶2, without dependence on gain. The NGD and NGD range can be seen in Fig. 5. The capacitor values are selected as 2.2 nF, 22 nF, and 220 nF. The higher the capacitor value, the higher the NGD, but this also decreases the operation frequency given in (15). The resistors are selected as: 𝑅1=𝑅2𝛽=𝑅3= 10 kΩ.(27) Table 4 Description of the 4th-order SK-LPF with Bessel response. Pass-band/Stop-band Frequency (Hz) 100/1 k Gain (V/V) 1 Stop-band Attenuation (dB) −65.9 Group Delay (μs) 3400 Using Eq. (22) gives (28): |𝐻(𝜔≅ 0)|≅ 2.(28) To achieve a NGD operation range of up to 650 Hz, the capacitors are selected as follows: 𝐶1=𝐶2= 22 nF.(29) As mentioned, this selection is based on Eq. (15). To mitigate the risk of instability in the system, the value of resistor 𝑅2is set 2% higher than the other resistors, with a scaling factor of 𝛽= 0.98. The parameters specified in (27) and (29) are used to generate the results shown in Fig. 5, which demonstrates that the base-band gain is independent of the NGD value. The simulation results and theoretical calculations of the group delay are in good agreement at low frequencies, up to 650 Hz, as demonstrated in Fig. 6. The simulation was performed using the Analog Devices AD844AN [20] and OP200 [21] SPICE models and LT Spice simulation software. The proposed NGD circuit was tested using a 4th-order Sallen-Key low-pass filter (SK-LPF) topology with Bessel response, as depicted in Engineering Science and Technology, an International Journal 48 (2023) 101590 6 O. Baloglu et al. Fig. 4. Group delay vs. resistors @100 Hz, 𝑅1,𝑅2, and 𝑅3swept from 1 Ωto 20 kΩ, 𝐶1=𝐶2= 22 nF. Fig. 5. AC analysis of the circuit II. 𝑅1=𝑅2𝛽=𝑅3= 10 kΩ,𝐶1=𝐶2is 2.2nF, 22 nF, and 220 nF, 𝛽= 0.98 factor of 𝑅2for the stability. Table 5 4th-Order SK-LPF passive component values. Components Values Simulation Experiments 𝑅1𝑠1,2𝑠1,1𝑠2,2𝑠2(kΩ) 9.76, 11.8, 5.76, 6.65 9.64, 11.76, 5.71, 6.57 𝐶1𝑠1,2𝑠1,1𝑠2,2𝑠2(nF) 110, 100, 261, 100 116, 100, 262, 95 Fig. 7. The simulation was again performed using the Analog Devices AD844AN [20] and OP200 [21] SPICE models and LT Spice simulation software. The parameters of the SK-LPF are summarized in Table 4, and the passive component values selected for the SK-LPF are listed in Table 5. The test was conducted by applying a pulse input signal to the test circuit and operation range of NGD up to 650 Hz was achieved. To illustrate the time advancement at the output of the NGD, a zoom of time-domain responses is provided in Fig. 8(a). To validate the circuit in a practical application, the SK-LPF in the circuit shown in Fig. 7 was substituted with an audio signal. The input audio signal was filtered to be within the operational range of the NGD, up to 500 Hz. The time-domain responses are presented in Fig. 8(b) and Fig. 8(c). The simulation results are in good agreement with theory. Fig. 6. Calculated and simulated (a) group delay-frequency responses, (b) zoom at low frequency. Fig. 7. Block diagram of the test system. Table 6 The component values of NGD circuit shown in Fig. 2(a). Components Values 𝑅1,2,3(kΩ) 9.8, 10.26, 9.8 𝐶1,2(nF) 22, 22 Table 7 Performance comparison of the circuit in Fig. 2(a). Parameter Calculation Simulation Experiment NGD (μs) 108 101.6–112.5 98.4 Flat Group Delay Range (Hz) 1–650 1–650 700 5.2. Experimental verification The experiment was performed to demonstrate the correlation between the simulated and measured values of the NGD circuit. The circuit in Fig. 2(a) was used for the setup, which consisted of an Analog Devices AD844AN [20], an OA OP200 [21] for the SK-LPF, a signal generator AFG3032C Tektronix, a signal analyzer MDO3104 Tektronix, and a voltage supply SPD-3606 GW INSTEK; see Fig. 9. Amplifiers were supplied by ±12 V. The component values used for the 4th-order SKLPF and NGD circuit are listed in Table 5 and Table 6, respectively, and correspond to the circuit schematic in Fig. 7. The measurement results are depicted in Fig. 10. Moreover, to demonstrate the impact of capacitor values (𝐶1=𝐶2= 2.2nF) on the operation range of the NGD circuit, the system was subjected to a sinusoidal input, as shown in Fig. 11. The results are in good agreement with the theory, as demonstrated in Table 7. Engineering Science and Technology, an International Journal 48 (2023) 101590 7 O. Baloglu et al. Fig. 8. Time domain results: (a) Simulated NGDC output with SK-LPF output (zoom in 0.025 <𝑡<0.04 s, (b) audio input and NGDC output with 𝐶1=𝐶2= 22 nF, a 1 second record; (c) its zoom. (Red—square wave input signal, green—output of SK-LPF, blue—output of NGDC.) Fig. 9. Measurement setup. Fig. 10. Measured time domain results of a NGDC with 100 μs value. (Red—square wave input signal, green—output of SK-LPF, blue—output of NGDC.) Table 8 Performance comparison with state-of-the-art solutions. Reference This study [16] [17](a) NGD 100 μs 800 ns 100 μs Flat Group Delay Range 650 Hz 10 kHz ≅150 Hza RMSE (Single Tone) 0.0086 0.0674 0.0013 RMSE (Audio Record) 0.0154 0.0012 0.0053 aThe NGD operation range is 1 kHz [17]. 6. Performance comparison Performance comparison with selected state-of-the-art solutions is given in Table 8. The Root Mean Square Error (RMSE) was calculated as follows: RMSE =√ √ √ √1 𝑏−𝑎 𝑏 ∑ 𝑖=𝑎(𝑥𝑖𝑛[𝑖] − 𝑥𝑜𝑢𝑡[𝑖+𝜏𝑛𝑔𝑑 ∕𝑇𝑠𝑎𝑚𝑝𝑙𝑒])2.(30) In Eq. (30),𝑥𝑖𝑛[𝑖]and 𝑥𝑜𝑢𝑡[𝑖+𝜏𝑛𝑔𝑑 ∕𝑇𝑠𝑎𝑚𝑝𝑙𝑒]represent the normalized input to the NGD circuit and the normalized delayed output of the NGD Fig. 11. Measured time domain results of a NGDC with 98.40 μs value. (Red—input of the NGD circuit, blue—output of the NGD circuit.) circuit, respectively. 𝑎and 𝑏are the starting and ending indices of the sampled signals. The input and output signals of the NGD circuit were sampled with 𝑇𝑠𝑎𝑚𝑝𝑙𝑒 <|𝜏𝑛𝑔𝑑 |to perform the calculations in MATLAB, where 𝑖is the index of the sampled input and output signals. It is noted that the term 𝜏𝑛𝑔𝑑 ∕𝑇𝑠𝑎𝑚𝑝𝑙𝑒 is selected as an integer and 𝜏𝑛𝑔𝑑 is a negative value of the group delay. 7. Conclusion Nine new single CFOA-based second-order NGD topologies, including a comprehensive design methodology, are presented. Presented circuits perform slightly differently in the time and frequency domain due to the real performance of the CFOA and matching conditions. The simulation results demonstrate that these active NGD circuits are suitable for low-frequency applications, with a group delay of approximately 100 μs achieved in the frequency range of 1 Hz to 650 Hz. The proposed parameters offer a unique advantage as the NGD value can be achieved without dependency on gain, providing a specific NGD operation range. Engineering Science and Technology, an International Journal 48 (2023) 101590 8 O. Baloglu et al. CRediT authorship contribution statement Onat Baloglu: Conceptualization, Software, Validation, Formal analysis, Investigation, Data curation, Writing – original draft, Writing – review & editing, Visualization. Oguzhan Cicekoglu: Conceptualization, Methodology, Formal analysis, Writing – original draft, Writing – review & editing, Supervision, Project administration. Norbert Herencsar: Conceptualization, Methodology, Resources, Writing – original draft, Writing – review & editing, Visualization, Supervision, Funding acquisition. Declaration of competing interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Acknowledgment The authors would like to acknowledge the technical support provided by the Information Technologies Institute (BTE) at the Informatics and Information Security Research Center (TUBITAK, BILGEM), Kocaeli, Turkey. References [1] B. Ravelo (Ed.), Negative Group Delay Devices: From concepts to applications, IET, ISBN: 978-1-7856-1640-2, 2018, http://dx.doi.org/10.1049/PBCS043E. [2] C.M. Hymel, M.H. Skolnick, R.A. Stubbers, M.E. Brandt, Temporally advanced signal detection: A review of the technology and potential applications, IEEE Circuits Syst. Mag. 11 (3) (2011) 10–25, http://dx.doi.org/10.1109/MCAS.2011. 941076. [3] M.M. Kizmaz, N. Herencsar, O. Cicekoglu, A 4-bits active inductor-based lattice 24.5–50 ps all-pass filter, Eng. Sci. Technol. Int. J. 35 (2022) 101263, http: //dx.doi.org/10.1016/j.jestch.2022.101263. [4] R. Vauché, R.A.B. Mefteh, F. Haddad, W. Rahajandraibe, F. Wan, S. Lalléchère, G. Fontgalland, P. Thakur, A. Thakur, B. Ravelo, Bandpass NGD time-domain experimental test of double-li microstrip circuit, IEEE Des. Test 39 (2) (2022) 121–128, http://dx.doi.org/10.1109/MDAT.2021.3103457. [5] B. Ravelo, F. Wan, J. Ge, Anticipating actuator arbitrary action with a low-pass negative group delay function, IEEE Trans. Ind. Electron. 68 (1) (2021) 694–702, http://dx.doi.org/10.1109/TIE.2020.2967730. [6] J.N. Munday, R.H. Henderson, Superluminal time advance of a complex audio signal, Appl. Phys. Lett. 85 (3) (2004) 503–505, http://dx.doi.org/10.1063/1. 1773926. [7] F. Wan, T. Gu, B. Li, B. Li, W. Rahajandraibe, M. Guerin, S. Lalléchère, B. Ravelo, Design and experimentation of inductorless low-pass NGD integrated circuit in 180-nm CMOS technology, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 41 (11) (2022) 4965–4974, http://dx.doi.org/10.1109/TCAD.2021.3136982. [8] B. Ravelo, M. Guerin, J. Frnda, F.E. Sahoa, G. Fontgalland, H.S. Silva, S. Ngoho, F. Haddad, W. Rahajandraibe, Design method of constant phase-shifter microwave passive integrated circuit in 130-nm BiCMOS technology with bandpass-type negative group delay, IEEE Access 10 (2022) 93084–93103, http: //dx.doi.org/10.1109/ACCESS.2022.3201137. [9] B. Ravelo, G. Fontgalland, H.S. Silva, J. Nebhen, W. Rahajandraibe, M. Guerin, G. Chan, F. Wan, Original application of stop-band negative group delay microwave passive circuit for two-step stair phase shifter designing, IEEE Access 10 (2022) 1493–1508, http://dx.doi.org/10.1109/ACCESS.2021.3138371. [10] D. Ozenli, E. Alaybeyoglu, H. Kuntman, O. Cicekoglu, MOSFET-only filter design automation based on polynomial regression with exemplary circuits, AEU - Int. J. Electron. Commun. 84 (2018) 342–354, http://dx.doi.org/10.1016/j.aeue.2017. 11.014. [11] H. Choi, Development of negative-group-delay circuit for high-frequency ultrasonic transducer applications, Sensors Actuators A 299 (2019) 111616, http: //dx.doi.org/10.1016/j.sna.2019.111616. [12] M. Kitano, T. Nakanishi, K. Sugiyama, Negative group delay and superluminal propagation: An electronic circuit approach, IEEE J. Sel. Top. Quantum Electron. 9 (1) (2003) 43–51, http://dx.doi.org/10.1109/JSTQE.2002.807979. [13] F. Wan, N. Li, B. Ravelo, J. Ge, B. Li, Time-domain experimentation of NGD ActiveRC-network cell, IEEE Trans. Circuits Syst. II 66 (4) (2019) 562–566, http://dx.doi.org/10.1109/TCSII.2018.2870836. [14] F. Wan, X. Miao, B. Ravelo, Q. Yuan, J. Cheng, Q. Ji, J. Ge, Design of multi-scale negative group delay circuit for sensors signal time-delay cancellation, IEEE Sens. J. 19 (19) (2019) 8951–8962, http://dx.doi.org/10.1109/JSEN.2019.2921834. [15] E. Tamaseviciute, S. Bumeliene, A. Tamasevicius, Using taylor predictor to improve stabilization of steady state in third-order chaotic system, in: Proceedings of the 2007 18th European Conference on Circuit Theory and Design, Seville, Spain, 2007, pp. 719–722, http://dx.doi.org/10.1109/ECCTD.2007.4529697. [16] M.T. Abuelma’atti, Z.J. Khalifa, A new CFOA-based negative group delay cascadable circuit, Analog Integr. Circuits Signal Process. 95 (2) (2018) 351–355, http://dx.doi.org/10.1007/s10470-018-1172-y. [17] F. Wan, Z. Yuan, B. Ravelo, J. Ge, W. Rahajandraibe, Low-pass NGD voice signal sensoring with passive circuit, IEEE Sens. J. 20 (12) (2020) 6762–6775, http://dx.doi.org/10.1109/JSEN.2020.2976531. [18] R. Senani, D.R. Bhaskar, A.K. Singh, V.K. Singh, Current Feedback Operational Amplifiers and their Applications, Springer New York, ISBN: 978-1-4614-5187-7, 2013, pp. 1–249, http://dx.doi.org/10.1007/978-1-4614-5188-4. [19] R.J. Baker (Ed.), CMOS: Circuit Design, Layout, and Simulation, fourth ed., Wiley-IEEE Press, ISBN: 978-1-1194-8151-5, 2019. [20] AD844AN – 60 MHz, 2000 V/μs, Monolithic Op Amp with Quad Low Noise, Analog Devices, 2017, Rev. G. [21] OP200 – Dual Low Offset, Low Power Operational Amplifier, Analog Devices, 2017, Rev. G.