3 d IEEE La in Ame ican Tes Wo kshop. Mon e ideo, U uguay, Feb ua y 10-13, 2002
70
Dynamic Replica ion: The Co e o a T uly Non-In usi e SRAM-based FPGA
S uc u al Concu en Tes Me hodology
Manuel G. Ge ico a, Gus a o R. Al es
Depa men o Elec ical Enginee ing — ISEP
Rua D . An ónio Be na dino de Almeida
4200-072 Po o - PORTUGAL
{mgg, gal es}@dee.isep.ipp.p
Miguel L. Sil a, José M. Fe ei a
Dep. o Compu e s and Elec ical Enginee ing — FEUP
Rua D . Robe o F ias
4200-465 Po o - PORTUGAL
{mlms, jm }@ e.up.p
Abs ac ♦
♦♦
♦
The inc easing use o econ igu able compu ing
pla o ms, employing SRAM-based FPGAs, opens
exci ing new possibili ies since hey enable he
eu iliza ion o he same ha dwa e esou ces o
implemen speed-c i ical compu a ional asks, wi hou
in e up ing sys em ope a ion.
Ne e heless, la ge dies and he use o smalle
submic on scales in he manu ac u ing o his new kind o
FPGAs inc ease he p obabili y o li e ime ope a ion
ailu es, equi ing new es / aul - ole ance me hods
capable o assu ing he eliabili y o he sys em.
S uc u al concu en es p ocedu es become
pa icula ly impo an in his con ex , since i is now
possible o eplica e and elease o es in e nal FPGA
esou ces, concu en ly wi h — bu no a ec ing —
sys em ope a ion. A new dynamic eplica ion p ocess o
ac i e Con igu able Logic Blocks (CLBs) is p esen ed in
his pape , which enables he implemen a ion o a uly
non-in usi e s uc u al concu en es app oach. The
expe imen al esul s p esen ed p o e he e ec i eness o
his solu ion.
1. In oduc ion
The ad en o a new kind o SRAM-based FPGAs
(Field P og ammable Ga e A ays) capable o
♦ This wo k is suppo ed by he Po uguese Founda ion o Science and
Technology (FCT), unde con ac POCTI/33842/ESE/2000
implemen ing as un- ime pa ial econ igu a ion (e. g.
he Vi ex amily om Xilinx), enabling he dynamic
cus omiza ion o ha dwa e unc ions o a pa icula sys em
o applica ion concu en ly wi h sys em ope a ion,
conside ably ein o ced he ad an ages o he use o
complex con igu able logic de ices in econ igu able
compu ing pla o ms.
Un o una ely, he smalle submic on scales used in he
manu ac u ing o hese de ices inc ease he h ea o
elec omig a ion, due o highe elec onic cu en densi y
in me al aces. Also, he co esponding lowe h eshold
ol ages make hem mo e suscep ible o gamma pa icle
adia ion. Radia ion in e e ence is much mo e likely wi h
la ge dies, inc easing he p obabili y o ailu e [1-2].
A e la ge pe iods o ope a ion, ce ain de ec s, namely
hose ela ed o small manu ac u ing impe ec ions no
de ec ed by p oduc ion es ing, become exposed,
eme ging as ei he s uck-a aul s o ansien aul s [3].
A highe FPGA eliabili y le el can he e o e only be
achie ed h ough he con inuous es o all i s blocks
h oughou sys em li e ime, and by he in oduc ion o
aul ole ance ea u es. In [4] he au ho s p oposed a new
me hodology o dynamically o a e and ee- o - es he
CLBs in an FPGA, wi hou dis u bing sys em ope a ion,
and p esen ed some e ec i e esul s conce ning he
adop ed s a egy o implemen he o a ion scheme.
Equally impo an in his me hodology is he eplica ion o
ac i e CLBs, i.e. hose CLBs ha a e pa o a unc ional
block ac ually being used by he sys em. In o de o ee
he CLBs o be es ed, hei unc ion mus be eplica ed in
CLBs p e iously es ed, in a way ha mus be comple ely
anspa en o he sys em.
3 d IEEE La in Ame ican Tes Wo kshop. Mon e ideo, U uguay, Feb ua y 10-13, 2002
71
In his pape a new eplica ion s a egy is p oposed,
which enables he comple e implemen a ion o a uly
non-in usi e s uc u al es o he FPGA CLBs o
pe manen ailu es ha may e en ually eme ge du ing
sys em li e ime. The p oposed s a egy does no equi e
he usage o any FPGA I/O pins, since i euses he IEEE
1149.1 in as uc u e [5] o access he con igu a ion
esou ces and o apply / cap u e es ec o s. While es ing
he a ious CLBs, ou p ocedu e also es s a signi ican
ac ion o all a ailable ou ing esou ces.
This pape is o ganized as ollows: ecen ly p oposed
app oaches o he es o SRAM-based FPGAs a e i s
e iewed, ollowed by a gene al desc ip ion o he
s uc u al concu en es solu ion en isaged o he FPGA
CLBs. The o a ion s a egy employed o ee he CLBs
and he adop ed es app oach a e b ie ly e iewed. The
ollowing sec ion de ails he eplica ion mechanism and
p esen s expe imen al esul s. In he end, some di ec ions
o u he esea ch a e in oduced.
2. Backg ound
Di e en o -line es me hodologies o SRAM-based
FPGAs ha e been p oposed in ecen publica ions,
employing a di e si y o Buil -In Sel -Tes (BIST)
s a egies o ex e nal es p ocedu es. An FPGA es
app oach based on BIST echniques, p esen ed in [6-7],
exploi s he ep og ammabili y o FPGAs in o de o se
up he BIST logic, which exis s only du ing o -line
es ing. Tes abili y is achie ed wi hou any a ea o e head
o pe o mance penal y, since he BIST logic is elimina ed
when he ci cui is econ igu ed o no mal ope a ion. A
di e en BIST a chi ec u e, based on he same s a egy,
was also p oposed o enable aul diagnosis [8-10].
An o -line es based on a non-BIST app oach,
a ge ed o es he FPGA CLBs, is p esen ed in [11-12].
In o de o achie e 100% aul co e age a CLB le el,
di e en es con igu a ions a e se up sequen ially, wi h
se ies o es ec o s being applied o each o hem
h ough he FPGA I/O Blocks (IOBs).
Since aul -de ec ion la ency is much la ge in o -line
es s a egies, hese app oaches a e unsa is ac o y in
highly aul -sensi i e, mission-c i ical applica ions, and as
a consequence a e es ic ed o manu ac u ing es .
In o de o o e come hese limi a ions, on-line es
me hods based on a scanning me hodology we e p esen ed
in [3, 13-15]. The basic concep unde lying hese me hods
consis s o ha ing only a ela i ely small po ion o he
chip being es ed o -line (ins ead o he whole chip as in
p e ious p oposals), while he es con inues i s no mal
ope a ion. I he unc ionali y o a column o FPGA CLBs
can be eplica ed on ano he po ion o he de ice, hen i
can be aken o -line and es ed o aul s in a anspa en
manne (i.e. wi hou in e up ing he sys em unc ionali y).
This aul scanning p ocedu e hen mo es on o copy and
es ano he column o CLBs, sweeping h ough he whole
FPGA, sys ema ically es ing o aul s. In his app oach,
known as Ro ing STARs, he whole sys em mus be
s opped in o de o eplica e he columns. Since
econ igu a ion is pe o med h ough he Bounda y Scan
(BS) in as uc u e, econ igu a ion ime is long, and i
seems likely ha hal ing he sys em will dis u b i s
ope a ion. The new pa ial and dynamic econ igu a ion
ea u es a e no en i ely exploi ed by his app oach,
possibly because dynamic eplica ion o an en i e column
would cause oo many dis u bances o he sys em
ope a ion.
The concu en es app oach p oposed in his pape
euses some o he p e ious concep s, bu elimina es hei
d awbacks by using a much smalle uni o es – he CLB.
The eplica ion o each CLB is accomplished wi hou
hal ing he sys em, e en i he CLB is ac i e.
The use o he BS es in as uc u e o access FPGA
con igu a ion memo y, and o apply he es ec o s and
cap u e he esponses in each CLB, b ings he addi ional
bene i o a educed o e head a boa d le el, since no
o he esou ces ( han hose o he FPGA i sel ) a e used.
Being applica ion-independen , and o ien ed o es he
FPGA s uc u e, he p oposed s a egy gua an ees FPGA
eliabili y a e many econ igu a ions, hus helping o
ensu e he co ec ope a ion h oughou he sys em
li e ime.
3. The p oposed FPGA concu en es
solu ion
In he as majo i y o econ igu able ha dwa e
sys ems, mul iple independen ha dwa e blocks
dynamically sha e he same FPGA de ice a he same
ime. Ne e heless, 100% usage o he FPGA esou ces is
ha dly e e achie ed, so a ew blocks will always be ee.
The DRAFT (Dynamically Ro a e And F ee o Tes )
me hod p esen ed in [4] is based in a scanning echnique
whe e empo a ily unused FPGA CLBs a e s uc u ally
es ed wi hou dis u bing sys em ope a ion, aking
ad an age o he dynamic and pa ially econ igu able
ea u es o e ed by new FPGAs.
Using a dynamic eplica ion and o a ion mechanism,
CLBs cu en ly being used by a gi en applica ion can
ha e hei unc ionali y dynamically eplica ed in one o
he CLBs al eady es ed. A e ans e ing i s
unc ionali y, he eplica ed CLB is ee o be es ed.
Ca ying ou a o a ion scheme ha co e s he whole
FPGA, his solu ion gua an ees ha he whole FPGA can
be es ed, wi hou dis u bing he sys em ope a ion,
p o ided ha a leas one unused CLB is a ailable in he
3 d IEEE La in Ame ican Tes Wo kshop. Mon e ideo, U uguay, Feb ua y 10-13, 2002
72
cu en implemen a ion. The in oduc ion o aul
ole ance ea u es will howe e equi e mo e han one
unused CLB, since a pool o spa e esou ces has o be
con inuously a ailable o eplace hose e en ually ound
de ec i e. Unlike Buil -In Sel -Repai (BISR) echniques
used in manu ac u ing, ou solu ion is able o dynamically
ole a e aul s in he ield. In his way, he sys em can s ill
ope a e in he p esence o aul y CLBs, and dependabili y
is imp o ed wi h easonably low ha dwa e edundancy
and no ex a cos .
4. Ro a ing and es ing
The o a ion s a egy ollowed in o de o ee CLBs
o es should ha e a minimum in luence (p e e ably
none) in he sys em ope a ion, as well as a educed
o e head in e ms o econ igu a ion cos . This cos
depends on he numbe o econ igu a ion ames needed
o eplica e and ee each CLB, since a g ea numbe o
ames would imply a longe es ime and la ge memo y
esou ces. The impac o his p ocess in he o e all sys em
ope a ion is due o a ia ions on ci cui iming, because o
ou ing adjus men s. I he e- ou ing p ocedu e o igina es
a pa h delay highe han he p e ious maximum, he
sys em’s maximum equency o ope a ion is educed and
he o e all sys em pe o mance deg ades.
Th ee possibili ies we e conside ed o es ablishing he
o a ion ule o he ee CLB, among he en i e CLB a ay:
andom, ho izon al and e ical o a ion [4].
The andom s a egy was ejec ed o h ee main
easons:
- i gene a es longe pa hs (and hence inc eases pa h
delays);
- i pu s oo much s ess in he limi ed ou ing
esou ces, by dispe sing g oups o CLBs assigned o
a same unc ion;
- i has unp edic able aul co e age la ency, which is
no accep able.
The second s a egy, ho izon al o a ion, is illus a ed
in igu e 1-a). The ee- o - es CLB (in whi e) would
o a e along a ho izon al pa h co e ing all CLBs in he
a ay. The eplica ion p ocess would ake place be ween
neighbo ing CLBs, due o sca ci y o ou ing esou ces
and o highe pa h delays. The same ule applies as well o
he e ical o a ion s a egy illus a ed in igu e 1-b),
whe e he CLB unde es o a es along a e ical pa h.
Simula ions pe o med wi h he las wo s a egies,
using Vi ex Xilinx FPGAs, o e a subse o 14 ITC’99
Benchma k Ci cui s om he Poli écnico di To ino [16],
ha e shown ha he e ical o a ion s a egy achie es
lowe cos s in e ms o econ igu a ion ile sizes. The size
ob ained by he applica ion o he ho izon al s a egy was
a ound 20% highe han wha was ob ained by he
applica ion o he e ical s a egy o he same ci cui
implemen a ions.
a) Ho izon al s a egy b) Ve ical s a egy
CLB
CLB
CLB
CLB
CLB CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB CLB
CLB
CLB
CLB
Figu e 1. Dynamic o a ion o he ee CLB
The in luence o bo h o a ion s a egies o e he
maximum equency o ope a ion was subs an ially
di e en , mainly due o a pai o dedica ed pa hs pe CLB
ha p opaga e ca y signals e ically o adjacen CLBs.
When he o a ion p ocess b eaks a dedica ed ca y pa h,
due o he inse ion o he ee CLB, he p opaga ion o
his ca y signal be ween he nea es adjacen CLBs
(abo e and below) is e-es ablished h ough gene ic
ou ing esou ces, inc easing he pa h delay. I he
implemen ed ci cui has one o mo e o hese ca y
signals, he ho izon al o a ion would b eak all he ca y
ne s, inc easing pa h delays, bu he e ical o a ion
would only b eak hose in he op o bo om o he CLB
columns. The e ical o a ion s a egy is he e o e
p e e able, i we conside only he deg ada ion in he
maximum equency o ope a ion.
When no ca y signals a e used, wo o he ac o s mus
be conside ed: i) he numbe o signals wi h high anou ,
and ii) he placemen shape ( ec angula , squa e, ci cula ,
e c.) and o ien a ion (ho izon al, e ical) o he ci cui s
implemen ed inside he FPGA. In ec angula / ho izon al
implemen a ions, and when many high anou signals a e
p esen , he ho izon al s a egy becomes p e e able, since
he maximum equency o ope a ion is less deg aded ( his
could be a mo e impo an ac o han econ igu a ion ile
size when dealing wi h high-speed applica ions).
The BS in as uc u e is also eused o access he CLBs
du ing he es p ocess. In o de o c ea e he es model o
he Vi ex CLB s uc u e, some es ic ions had o be
imposed:
- he ca y logic would no be es ed, because i is no
possible o access he CLB ca y inpu and ou pu
po s di ec ly (only by passing h ough he e ically
adjacen CLBs);
- he use o LUTs (Look-Up Tables) as Dis ibu ed
RAM would no be ini ially conside ed.
Each VIRTEX CLB comp ises wo slices exac ly
equal. In o al, he CLB es model has 13 inpu s ( es
ec o s a e applied o bo h slices o each CLB
simul aneously) and 12 ou pu s (six om each slice).
Tes ec o s a e applied and esponses cap u ed
h ough he BS in as uc u e, wi h he ou pu s o he CLB
3 d IEEE La in Ame ican Tes Wo kshop. Mon e ideo, U uguay, Feb ua y 10-13, 2002
73
unde es being ou ed o unused BS egis e cells
associa ed o he IOBs. Howe e , and since he
applica ion o es ec o s h ough he BS egis e would
a ec he alues p esen a each FPGA inpu , an
al e na i e Use Tes Regis e mus be used ( he Vi ex
amily enables he de ini ion o wo use egis e s
con olled h ough he BS in as uc u e), as shown in
igu e 2. This Use Tes Regis e comp ises 13 cells,
co esponding o he equi ed numbe o CLB es
con igu a ion inpu s.
M
U
X
Ou
Bypass egis e
Ins uc ion egis e
Con igu a ion egis e
In
TDO
TDI
...
CLB
unde es
Use Tes Regis e
Figu e 2. Tes o a CLB
The numbe o CLBs occupied by his egis e (se en),
associa ed o he CLB needed o pe o m he o a ion, a e
he only ha dwa e o e head implied by ou p oposed es
me hodology. This accoun s o 0,7% o he CLB
esou ces in a Xilinx XCV200, a medium size complexi y
FPGA (a ay size = 28x42 CLBs). Since he ou pu s o
each slice a e cap u ed independen ly, aul loca ion can
be esol ed o a single slice.
As he implemen a ion s uc u e o he CLBs
mul iplexe s and lip- lops was no known, we conside ed
a hyb id aul model [11]. The analysis o he Vi ex CLB
es model s uc u e led us o conclude ha ou es
con igu a ions we e enough o exe cise all possible CLB
aul s. Since econ igu a ion h ough he BS in as uc u e
is slow, his small numbe o es s eps is a good measu e
o ou educed es ime.
The back-and- o h dynamic ee-CLB o a ion ac oss
he chip implies a a iable es la ency. The ime o again
each a gi en CLB al e na es be ween a maximum and a
minimum alue (acco ding o he o a ion di ec ion),
depending on he size o he de ice:
- he maximum aul de ec ion la ency is gi en by:
)(2)2)#((# es econ columns owsscan CLBCLB
MAX
+××−×=
τ
- he minimum aul de ec ion la ency is in u n gi en
by:
)(2 es econ scan
min
+×=
τ
whe e:
econ : ime needed o comple e a CLB eplica ion
es : ime needed o es a ee CLB
The maximum aul la ency ob ained expe imen ally in
essays pe o med wi h he XCV200, a a BS ope a ion
equency o 30MHz, was 48 seconds.
A e a comple e back-and- o h dynamic ee-CLB
o a ion, he ini ial ou ing is es o ed, and he e o e no
cumula i e pe o mance deg ada ion esul s by
con inuously epea ing his p ocess.
In ou app oach, he con igu a ion memo y is
conside ed aul ee and will no be es ed. Howe e , he
same es in as uc u e could be used o pe o m a
eadback o he con igu a ion da a ha was loaded in o he
FPGA, helping o de ec aul s in he con igu a ion
elemen s. Wi h his aim, a eadback and compa e so wa e
applica ion, capable o pe o ming ull eadback
con igu a ion memo y h ough he S anda d BS es access
po , was de eloped. The eadback ile is compa ed wi h
he o iginal con igu a ion ile, in sea ch o di e ences
indica ing he exis ence o possible aul s in he
con igu a ion memo y.
5. A no el eplica ion p ocess
The o a ion mechanism implies he eplica ion o
ac i e CLBs. This ask is no i ial due o wo majo
issues: i) con igu a ion memo y o ganiza ion, and
ii) in e nal s a e in o ma ion.
The con igu a ion memo y can be isualized as a
ec angula a ay o bi s, which a e g ouped in o one-bi
wide e ical ames ex ending om he op o he bo om
o he a ay. One ame is he a omic uni o con igu a ion
— i is he smalles po ion o he con igu a ion memo y
ha can be w i en o o ead om. These ames a e
g ouped oge he in o la ge uni s called columns. Each
CLB column has a co esponding con igu a ion column,
wi h mul iple ames, ha mixes in e nal CLB
con igu a ion in o ma ion, ou ing in o ma ion and s a e
in o ma ion. The con igu a ion p ocess is a sequen ial
mechanism ha spans h ough some o he whole CLB
con igu a ion columns. When eplica ing an ac i e CLB,
i s inpu and ou pu signals (as well as hose in i s eplica)
may c oss se e al columns be o e eaching i s sou ce o
des ina ion. Any econ igu a ion ac ion mus he e o e
ensu e ha he signals om he eplica ed CLB a e no
b oken be o e being o ally e-es ablished om i s eplica.
Also impo an , o a oid ou pu gli ches, he unc ionali y
o he CLB eplica mus be pe ec ly s able be o e i s
ou pu s a e connec ed o he sys em. A se o expe imen s
3 d IEEE La in Ame ican Tes Wo kshop. Mon e ideo, U uguay, Feb ua y 10-13, 2002
74
pe o med wi h a XCV200 demons a ed ha he only
possible solu ion is o di ide he eplica ion p ocess in
wo phases, as illus a ed in igu e 3. In he i s phase, he
in e nal con igu a ion o he CLB is eplica ed and he
inpu s o bo h CLBs a e placed in pa allel. Due o he
low-speed cha ac e is ics o he (BS) in e ace, he
econ igu a ion ime is ela i ely long when compa ed
wi h he sys em speed o ope a ion. The e o e, he ou pu s
o he CLB eplica will be pe ec ly s able be o e being
connec ed o he ci cui , in he second phase. Bo h CLBs
mus emain in pa allel o a leas one sys em clock cycle
o a oid ou pu gli ches.
1s phase 2nd phase
- Rou ing a ay
eplica ed
CLB
CLB
eplica
eplica ed
CLB
CLB
eplica
In
In
In
In Ou
Ou Ou
Ou
Figu e 3. Two-phase CLB eplica ion p ocess
Ano he majo equi emen o he success o he
eplica ion p ocess is he co ec ans e o s a e
in o ma ion. I he cu en CLB unc ion is pu ely
combina ional, a simple ead-modi y-w i e con igu a ion
p ocedu e will su ice o accomplish he eplica ion
p ocess. Howe e , in he case o a sequen ial unc ion, he
in e nal s a e in o ma ion mus be p ese ed and no w i e-
-ope a ions shall be los du ing he eplica ion p ocess. In
Vi ex FPGA amily, i is possible o ead he alue o a
egis e , bu no o pe o m a di ec w i e ope a ion.
Mo eo e , when dealing wi h ac i e CLBs, s a e
in o ma ion may change be ween he ead and w i e o a
egis e , causing a cohe ency p oblem. By his eason, no
ime gap be ween he wo ope a ions may exis . As a
consequence, he use o empo a y ans e pa hs [13] is
no easible wi h ac i e CLBs. An addi ional
econ igu a ion s ep, in o de o se up he ans e pa h
be ween bo h CLB’s lip- lops, would be needed. The
econ igu a ion o he CLB eplica a e he ans e o i s
unc ionali y would c ea e an unaccep able ime gap
be ween s a e in o ma ion ans e al and i s ac i a ion.
When dealing wi h synch onous ci cui s, a wo-phase
eplica ion p ocess may sol e his p oblem. Be ween he
i s and he second phase, he CLB eplica has he same
inpu s as he eplica ed CLB and acqui es he s a e
in o ma ion, e en i he sys em equency o ope a ion is
an o de o magni ude lowe han he BS in as uc u e
equency used o econ igu a ion pu poses. The
acqui ed s a e in o ma ion is co ec , despi e any aul ha
may a ec he eplica ed CLB lip- lops, since i is
ob ained di ec ly om he inpu s, ins ead o being
ans e ed om hose (e en ually aul y) lip- lops ( his
me hod is no applicable o asynch onous ci cui s).
Se e al expe imen s made using synch onous ci cui s
ha e shown he e ec i eness o his me hod in he
eplica ion o ac i e CLBs. No loss o s a e in o ma ion o
he p esence o ou pu gli ches was epo ed, and he
eplica ion ime is independen o he unc ion
implemen ed by he CLB.
The success ul es o he CLB eplica assu es i s good
unc ionali y, bu he eplica ed CLB could be aul y.
When he inpu s and ou pu s o bo h CLBs a e placed in
pa allel, we may be in e connec ing nodes wi h di e en
ol age le els. Due o he in e nal impedance o he
ou ing swi ches, his appa en “sho -ci cui ” beha es as a
ol age di ide , limi ing he cu en low in he
in e connec ion. The e o e, no damage esul s o he
FPGA, as p o ed by ex ensi e expe imen al essays. Since
we a e dealing wi h digi al ci cui s, he analog alue
esul ing om he ol age di ide ends in a well de ined
alue (logic 0 o logic 1) when i goes h ough a bu e
du ing he ou ing o a he inpu o he nex CLB o IOB.
No logic alue ins abili y was epo ed du ing he essays.
Each CLB has h ee ou ing a ays associa ed: wo
local a ays (inpu and ou pu ); and one global a ay. The
ou ing esou ces in hese a ays may be unidi ec ional o
bi-di ec ional, as indica ed in igu e 4. No ou ing
esou ces a e a ailable in he local a ays o es ablish
di ec in e connec ions wi h o he CLBs, so he
in e connec ions equi ed in he eplica ion p ocess can
only be done h ough he global ou ing a ay.
Inpu ou ing a ay
Ou pu ou ing a ay
Slice 1 Slice 0
CLB
Global
ou ing a ay
Figu e 4. CLB ou ing esou ces
Only unidi ec ional ou ing esou ces a e a ailable
be ween local and global ou ing a ays, as seen in
igu e 4. Fo pa alleling inpu s, in e connec ion segmen s
be ween global a ays may be unidi ec ional ( om he
eplica ed CLB inpu s owa ds he CLB eplica inpu s), o
bi-di ec ional. Conce ning he ou pu s, in e connec ion
segmen s be ween global a ays may also be
unidi ec ional ( om he CLB eplica ou pu s owa ds he
eplica ed CLB ou pu ), o bi-di ec ional, as illus a ed in

3 d IEEE La in Ame ican Tes Wo kshop. Mon e ideo, U uguay, Feb ua y 10-13, 2002
75
igu e 5. O he wise, since signals do no p opaga e
backwa ds, no signals will be p esen ed a he inpu s o
he CLB eplica, and he ou pu s o bo h CLBs will no be
placed in pa allel. As a esul , ou pu gli ches will occu
when CLB eplica ed ou pu s a e disconnec ed om he
sys em and no signals will be p opaga ed o he es o he
ci cui .
eplica ed
CLB
CLB
eplica
- Local ou ing a ay
- Global ou ing a ay
- Manda o y di ec ionali y
- Op ional bi-di ec ionali y
In
In
Ou
Ou
Figu e 5. Replica ion CLB in e connec ion
Since no aul a any o he eplica ed CLB inpu s may
p opaga e backwa ds, he logic alues p esen ed a he
inpu s o he CLB will no be a ec ed by he
in e connec ion, e en i he eplica ed CLB is aul y. As
such, all CLB eplica inpu s will always e lec he co ec
alues and hence he s a e in o ma ion i acqui es is
co ec as well. As a consequence, and a e he
eplica ion p ocess, he ou pu s o he CLB eplica always
display he co ec alue, au oma ically co ec ing any
aul y beha io .
5. Conclusion
This pape p esen ed a no el eplica ion p ocess o
eplica e ac i e CLBs wi hou dis u bing hei ope a ion.
The p oposed p ocedu e enables he implemen a ion o a
uly non-in usi e s uc u al concu en es me hodology
o pa ial and dynamically econ igu able SRAM-based
FPGAs, wi h he ollowing ad an ages:
1. The es me hod is comple ely sys em- anspa en ;
2. The o e head a chip le el is e y low;
3. Tes pa e n gene a ion has low complexi y because
i is done o only a single CLB;
4. Faul loca ion is esol ed o a single CLB slice;
5. Faul ole ance may be added as a complemen o he
p oposed solu ion;
6. The dependabili y o sys ems based on his ype o
FPGAs is imp o ed.
Suppo o sys em designe s h ough he whole p ocess
implied also he de elopmen o speci ic so wa e ools
o he au oma ic gene a ion o pa ial econ igu a ion
bi s eams om hei comple e coun e pa s, o simpli y
FPGA econ igu a ion ope a ions h ough he BS
in as uc u e.
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