FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO
Algo i hm and Ha dwa e Design o
Image Res o a ion
Be na do Manuel Aguia Sil a Teixei a Ca doso
FOR JURY EVALUATION
Mes ado In eg ado em Engenha ia Ele o écnica e de Compu ado es
Supe iso : Ví o Manuel G ade Ta a es
Second Supe iso : Xin Li (Ca negie Mellon Uni e si y)
June 29, 2015
c
Be na do Ca doso, 2015
ii
Resumo
O econhecimen o au omá ico de cená ios com base em in o mações p esen es numa imagem é
uma a e a impo an e pa a disposi i os po á eis com mui as aplicações p á icas (po exemplo, de-
eção acial num sma phone). Po ou o lado, o consumo ene gé ico e a espessu a de disposi i os
po á eis são duas conside ações impo an es subjacen es ao p oje o de ele ones e able s. O p in-
cipal e ei o cola e al des as es ições é um módulo de câma a mais pequeno, que unciona com
len es com pequenas abe u as e senso es com pixéis pequenos - ambos limi ando a quan idade
de luz de e ada pela câma a. Is o esul a numa edução da qualidade de o og a ias em condições
ad e sas de imagem, como po exemplo, pouca luz ou empo de exposição pequeno pa a a de eção
de obje os em mo imen o. A qualidade eduzida mani es a-se num aumen o do uído, aumen o de
blu , e al a de con as e. Po sua ez, es as condições não ideais limi am, em p á ica, a p ecisão
do econhecimen o de cená ios.
Nes e abalho, é ap esen ado um mecanismo pa a a eliminação de uído em imagens (image
denoising), que ope a em empo eal e com pouco es o ço compu acional, melho ando a qualidade
das o og a ias i adas com uma câma a e, consequen emen e, a p ecisão do econhecimen o de
cená ios. Uma no a a qui e u a de ha dwa e é p opos a pa a implemen a o algo i mo de es au-
ação de imagens acima mencionado com o supo e de uma FPGA.
O obje i o p incipal do abalho é melho a d as icamen e a qualidade das imagens e, conse-
quen emen e, a qualidade de classi icação em empo eal, i ando pa ido da implemen ação em
FPGA p opos a.
iii

i
Abs ac
Au oma ic ecogni ion o a scene based on he in o ma ion p esen in an image is an impo an
ask o po able de ices wi h many p ac ical applica ions (e.g., ace de ec ion on a sma phone).
On he o he hand, powe consump ion and hinness o po able de ices a e wo impo an con-
side a ions behind he design o cell phones and able s. A side-e ec o hese cons ain s is a
smalle came a module ha wo ks wi h lenses wi h small ape u es and senso s wi h iny pixels
- bo h limi ing he amoun o ligh sensed by he came a. I esul s in educed quali y o pho-
og aphs unde ad e se imaging condi ions such as low ligh and small exposu e ime o imaging
as mo ing objec s. The educed quali y mani es s i sel in inc eased noise, inc eased blu , and
lack o con as . These non-ideali ies, in u n, limi he accu acy o scene ecogni ion in p ac ice.
In his wo k, i is p oposed o build a eal ime, compu a ionally inexpensi e image denoising
engine ha enhances he quali y o pho og aphs aken by a came a and, consequen ly, he accu acy
o scene ecogni ion. A no el ha dwa e a chi ec u e is p oposed o implemen he a o emen ioned
image es o a ion algo i hm wi h FPGA.
The main goal is o la gely enhance he quali y o images and, hence, he quali y o classi ica-
ion in eal ime by aking ad an age o he p oposed FPGA implemen a ion.
i
Ag adecimen os
Es e abalho ep esen a a conclusão de cinco anos de ap endizagem, acumulação de conheci-
men o, abalho du o e á ios momen os e expe iências inesquecí eis. Todos es es di ididos en e
i e e iaja em á ias cidades po oda a Eu opa e, mais ecen emen e, na Amé ica do No e.
Todas essas expe iências não pode iam se possí eis sem o apoio cons an e e comple o de oda
a minha amília. Que o po isso ag adece a oda a minha amília, especialmen e os meus pais e
a ós. Pa a os meus pais, mui o ob igado po odo o apoio e po semp e p o idencia em odas
as condições pa a o meu desen ol imen o como pessoa, po odas as lições de ida, po oda a
paciência e sac i ícios, po semp e incen i ando-me a se melho e melho , e po apoia em odas
as minhas decisões. Pa a os meus a ós, ob igado po odas as aliosas lições de ida e his ó ias
an ás icas, po semp e me apoia em em oda a minha ida, especialmen e nos úl imos cinco anos,
e po semp e es a em p esen es, de uma manei a ou de ou a.
De seguida, que o ag adece aos meus o ien ado es da disse ação, o P o esso Ví o G ade
Ta a es e o P o esso Xin Li, po odo o apoio p es ado du an e os úl imos seis meses. Pa a
o P o esso Ví o , po cul i a o meu in e esse pela ele ónica, po odas as discussões e ajuda
o necida du an e os úl imos dois anos e especialmen e nos úl imos 6 meses, e po me enco aja
a p ossegui es e p oje o. Pa a o p o esso Xin, po odo o apoio du an e a minha es adia de ês
meses na Ca negie Mellon Uni e si y, po semp e man e um olha a en o sob e o meu abalho,
e po e semp e as melho es ideias e ajuda com odos os p oblemas. Que o, ambém, es ende
um ag adecimen o ao Minho Won, po ajuda com udo quando e a necessá io. Finalmen e, um
ag adecimen o especial a odos os p o esso es que conheci e abalhei nos úl imos cinco anos, o
que con ibuiu ex emamen e pa a o meu u u o como Engenhei o.
Du an e es a iagem de cinco anos i e a so e de conhece mui as pessoas ma a ilhosas, que
eu me o gulho de chama de amigos. Tenho imensa pena, mas po ou o lado so e, de dize que
não é possí el inclui odos nes a pequena página. Po isso, que o aze um ag adecimen o especial
a alguns deles. Pa a o An ónio, po me apoia desde que me lemb o, e po se como um i mão. Pa a
o T io do C eam ields: Xico e Yak, po odos os bons momen os e a en u as que passamos du an e
es es cinco anos (#VaiTodo). Pa a a CMU eam: Xico, JM e Cesá io, pelas ocas de ideias, as
b incadei as ocasionais e as oad ips. Pa a os companhei os de es i ais: Fisgas, Ja o, Joaninha,
Ma alda, po odos os es i ais e e ões inc í eis, e po es a em semp e p esen es, mesmo não
alando ão equen emen e como gos a íamos. E po úl imo, mas não menos impo an e, pa a o
Bi e, Ca los, Tico, Pe e D, Pe ei a, Diogo, Vini, Conde, Duda, um ob igado po es es cinco anos
de es udo e es as, e po odos jun os aze mos de Elec o 2010 um dos melho es anos de semp e!
Be na do Ca doso
ii
xi CONTENTS
4.3.1 Mul iplie -less DCT and IDCT . . . . . . . . . . . . . . . . . . . . . . . 39
4.3.2 Haa T ans o m Modules . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3.3 Ha d Th esholding Module . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3.4 Posi ion Memo y and Decode . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.5 Memo yModule .............................. 45
4.3.6 Con olModule............................... 45
4.4 TopLe elModule.................................. 47
4.4.1 Memo y Modules and Con ol . . . . . . . . . . . . . . . . . . . . . . . 47
4.4.2 Mas e Con ol ............................... 51
4.5 BM3DIPCo e ................................... 53
4.5.1 AXILi eSla e ............................... 54
4.5.2 TheMMCM ................................ 54
5 Tes Me hodology and Resul s 55
5.1 Expe imen alSe up................................. 55
5.1.1 ZYNQBoa dSe up............................. 56
5.1.2 CP og am ................................. 57
5.2 Resul s........................................ 59
5.2.1 FPGAResou ceUsage........................... 59
5.2.2 Denoising Pe o mance . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.2.3 Execu ionTime............................... 63
5.2.4 Powe Consump ion ............................ 65
6 Conclusions and Fu u e Wo k 69
6.1 Conclusions..................................... 69
6.2 Fu u eWo k..................................... 70
A Resul Images 71
Re e ences 79

Lis o Figu es
2.1 One s ep o a wa ele decomposi ion and econs uc ion. Taken om [7]..... 9
2.2 2D sepa able implemen ion o DWT and i s in e se. Taken om [8] ....... 10
2.3 Basis unc ions o a 8x8 2D DCT . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 a) Ha d h esholding ope a o . b) So h esholding ope a o . Adap ed om [7] . . 12
2.5 The K-SVD algo i hm. Taken om [18]...................... 14
3.1 a) O iginal Came aman image wi h size 256x256; b) Noisy image wi h σ=25
(PSNR=20.18 dB); c) Basic es ima e image ob ained by modi ied BM3D (PSNR=27.16
dB); d) Basic es ima e ob ained by o iginal BM3D (PSNR=29.14 dB) . . . . . . 27
3.2 a) O iginal Lena image wi h size 512x512; b) Noisy image wi h σ=25 (PSNR=20.19
dB); c) Basic es ima e image ob ained by modi ied BM3D (PSNR=30.32 dB); d)
Basic es ima e ob ained by o iginal BM3D (PSNR=31.37 dB) . . . . . . . . . . 28
4.1 BM3D Sys em A chi ec u e Block Diag am . . . . . . . . . . . . . . . . . . . . 30
4.2 Ma ching P ocesso Schema ic . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3 RTL schema ic o he `1no muni ......................... 34
4.4 RTL schema ic o one so e cell . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 S a e diag am o he ma ching p ocesso ’s memo y con ol module . . . . . . . . 36
4.6 S a e diag am o he ma ching p ocesso ’s con ol module . . . . . . . . . . . . . 37
4.7 Denoising Pipeline Schema ic . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.8 IDCT Flow g aph algo i hm. Taken om [49]................... 40
4.9 T anspose s uc u e. Adap ed om [51]...................... 41
4.10 RTL schema ics o he haa and in e se haa ans o m modules . . . . . . . . . 43
4.11 RTL schema ics o he ha d h esholding module . . . . . . . . . . . . . . . . . 44
4.12 S a e diag am o he denoising pipeline con ol module . . . . . . . . . . . . . . 46
4.13 S a e diag am o he mas e con ol module . . . . . . . . . . . . . . . . . . . . 51
4.14BM3DIPco eblock ................................ 53
5.1 Boa dDesignSchema ic .............................. 56
5.2 a) Basic es ima e image ob ained by modi ied BM3D (PSNR=27.16 dB) in MAT-
LAB; b) Basic es ima e ob ained by modi ied BM3D (PSNR=27.17 dB) in ha d-
wa e. Noisy image was co up ed wi h noise powe o 25. . . . . . . . . . . . . . 60
5.3 a) Basic es ima e image ob ained by modi ied BM3D (PSNR=30.32 dB) in MAT-
LAB; b) Basic es ima e ob ained by modi ied BM3D (PSNR=30.35 dB) in ha d-
wa e. Noisy image was co up ed wi h noise powe o 25. . . . . . . . . . . . . . 62
5.4 a) A e age PSNR (dB) o 512x512 images wi h noise powe s om 5 o 50. b)
A e age SSIM o 512x512 images wi h noise powe s om 5 o 50. . . . . . . . 66
x
x i LIST OF FIGURES
5.5 a) FPGA s CPU1 speedup o inc easing image esolu ions. b) FPGA s CPU2
speedup o inc easing image esolu ions. Images a e in he same o de as in ables
5.6 and 5.7. ..................................... 67
5.6 Powe consump ion dis ibu ion o he BM3D sys em o di e en ope a ing e-
quencies. ...................................... 68
A.1 a) O iginal image Ci y wi h 1MP esolu ion (1280x960). b) O iginal image Coa
wi h 2MP esolu ion (1920x1080). c) O iginal image B idge wi h 3MP esolu ion
(2048x1536). d) O iginal image Palace wi h 5MP esolu ion (2560x1920). e)
O iginal image NYC wi h 8MP esolu ion (3264x2448). . . . . . . . . . . . . . . 72
A.2 a) Noisy image Ci y wi h noise powe o 40. b) Denoised image wi h PSNR=24.88
dBandSSIM=0.761. ................................ 73
A.3 a) Noisy image Coa wi h noise powe o 20. b) Denoised image wi h PSNR=33.29
dBandSSIM=0.882. ................................ 74
A.4 a) Noisy image B idge wi h noise powe o 50. b) Denoised image wi h PSNR=23.98
dBandSSIM=0.740. ................................ 75
A.5 a) Noisy image Palace wi h noise powe o 30. b) Denoised image wi h PSNR=28.21
dBandSSIM=0.811. ................................ 76
A.6 a) Noisy image NYC wi h noise powe o 40. b) Denoised image wi h PSNR=29.38
dBandSSIM=0.848. ................................ 77
Lis o Tables
3.1 PSNR (dB) esul s o 256x256 Came aman Image . . . . . . . . . . . . . . . . 26
3.2 PSNR (dB) esul s o 512x512 Lena Image . . . . . . . . . . . . . . . . . . . . 26
4.1 Ha dcodedimagewid hs.............................. 48
5.1 FPGAResou ceUsage ............................... 59
5.2 PSNR (dB) esul s o 256x256 Came aman Image . . . . . . . . . . . . . . . . 60
5.3 PSNR (dB) esul s o 512x512 Lena Image . . . . . . . . . . . . . . . . . . . . 61
5.4 PSNR (dB) esul s compa ison o 1,2,3,5 and 8 MP images. . . . . . . . . . . . 62
5.5 SSIM esul s compa ison o 1,2,3,5 and 8 MP images. . . . . . . . . . . . . . . 63
5.6 FPGA execu ion ime esul s (in seconds) o images o inc easing esolu ions and
equencies...................................... 63
5.7 Compa ison o CPU and FPGA @125MHz execu ion ime esul s (in seconds) o
images o inc easing esolu ions. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.8 PL and PS powe consump ion (W) o di e en equencies o ope a ion. . . . . 65
x ii
x iii LIST OF TABLES
Abb e ia ions
ADC Analog o Digi al Con e e
ALU A i hme ic Logic Uni
AMBA Ad anced Mic ocon olle Bus A chi ec u e
ASIC Applica ion-Speci ic In eg a ed Ci cui
AWGN Addi i e Whi e Gaussian Noise
AXI Ad anced eX ensible In e ace
BM3D Block Ma ching and 3D Fil e ing
BRAM Block RAM
CAN Con olle A ea Ne wo k
CMOS Complemen a y Me al Oxide Semiconduc o
CPU Cen al P ocessing Uni
CS Comp essed Sensing
CSR Cen alized Spa se Rep esen a ion
CWT Con inuous Wa ele T ans o m
DCT Disc e e Cosine T ans o m
DDR3 Double Da a Ra e Type 3
DFT Disc e e Fou ie T ans o m
DMA Di ec Memo y Access
DSP Digi al Signal P ocesso
DWT Disc e e Wa ele T ans o m
FCT Fas Cosine T ans o m
FF Flip-Flop
FFT Fas Fou ie T ans o m
FGA Flow G aph Algo i hm
FPGA Field P og ammable Ga e A ay
ps F ames pe Second
FSM Fini e S a e Machine
GPU G aphics P ocessing Uni
IDCT In e se Disc e e Cosine T ans o m
I/O Inpu /Ou pu
IP In ellec ual P ope y
xix

xx ABBREVIATIONS
JPEG Join Pho og aphic Expe s G oup
JTAG Join Tes Ac ion G oup
LUT Look-up Table
MAD Median Absolu e De ia ion
MMCM Mixed-Mode Clock Manage
MP Mega Pixel
MRA Mul i esolu ion Analysis
MSB Mos Signi ican Bi
MSE Mean Squa ed E o
NCSR Nonlocally Cen alized Spa se Rep esen a ion
OS Ope a ing Sys em
PCA P inciple Componen Analysis
PL P og ammable Logic
PS P ocessing Sys em
PSNR Peak Signal o Noise Ra io
RAM Random Access Memo y
RGB Red Blue G een
RTL Regis e T ans e Le el
SAPCA Shape Adap i e P inciple Componen Analysis
SCN Spa se Coding Noise
SNR Signal o Noise Ra io
SoC Sys em on Chip
SPI Se ial Pe iphe al In e ace
SSH Secu e Shell
SSIM S uc u al Simila i y Index
SVD Singula Value Decomposi ion
UART Uni e sal Asynch onous Recei e /T ansmi e
USB Uni e sal Se ial Bus
Chap e 1
In oduc ion
1.1 Mo i a ion
In he ising ma ke o po able de ices, hinness and powe consump ion a e wo main conside a-
ions when p oducing a compe i i e and success ul de ice, o example, a cell phone o a able . A
nega i e side e ec o hese cons ain s is a smalle came a module, which in u n has lenses wi h
small ape u es and senso s wi h iny pixels. Bo h hese cha ac e is ics limi he amoun o ligh
ha is sensed by he came a, esul ing in a educed quali y o pho og aphs unde ad e se condi-
ions, such as, low ligh en i onmen s and small exposu e imes when dealing wi h as mo ing
objec s. This educed quali y appea s in he image as inc eased mo ion blu , lack o con as and
inc eased noise, all non-ideali ies ha limi he accu acy o scene ecogni ion.
Au oma ic scene ecogni ion based on he in o ma ion p esen in an image is an impo an
ask o po able de ices wi h many p ac ical applica ions, o example, ace de ec ion on a sma
phone. This way, he co up ed image needs o be es o ed in o de o achie e be e esul s
o ecogni ion, which mo i a es he use o an image es o a ion algo i hm o p ocess he image
be o e he ecogni ion ask. Hence, i is o majo impo ance o ha e as and e ec i e es o a ion
o an image in o de o p ocess he ecogni ion ask in eal ime.
The image es o a ion ask is a hea ily esea ched subjec , wi h many algo i hms being p o-
posed in he pas ew yea s, o igina ing om a ious a eas o esea ch such as p obabili y heo y,
s a is ics, linea and nonlinea il e ing, and spec al analysis. On he o he hand, all hese algo-
i hms sha e a simila concep : hey ely on implici o explici assump ions abou he ue image,
in o de o sepa a e i p ope ly om he noise. This sepa a ion is made possible by applying ans-
o ms o image pa ches o using dic iona ies, in o de o make he esul ing image ep esen a ion
spa se. Then, a simple h esholding ope a ion can be applied, disca ding he smalle coe icien s,
which a e assumed o be noise.
None heless, mos o he hese algo i hms a e highly compu a ional demanding, due o he use
o ans o ms o dic iona ies (which in u n in ol e aining). Hence, hey ake a la ge amoun o
ime o p oduce a es o ed image, when implemen ed in so wa e on a gene al pu pose CPU. This
1
2In oduc ion
mo i a es he implemen a ion o specialized ha dwa e o deal wi h a co up ed image in eal ime,
p oducing he es o ed image in he as es ime possible and wi h enhanced quali y.
In his wo k, a compu a ionally inexpensi e, low powe and eal ime image denoising ap-
p oach will be p esen ed, based on modi ica ions o he BM3D image denoising algo i hm, p o-
posed in [1]. This algo i hm enhances he quali y o pho og aphs aken by a came a and, conse-
quen ly, he accu acy o scene ecogni ion. A no el ha dwa e a chi ec u e will be p esen ed o
implemen he a o emen ioned image denoising algo i hm using an FPGA.
1.2 Objec i es
Image denoising algo i hms can be implemen ed using gene al pu pose CPUs, GPUs o special-
ized co es. The easies solu ion is he implemen a ion in a high le el language such as C o C++
in a CPU, howe e i is also he slowes . A GPU is specialized o deal wi h g aphics and he e o e
i is mo e adequa e o use as an image p ocesso . On he o he hand, mos GPUs consume a lo o
powe when aced wi h he kind o asks posed by mos denoising algo i hms. The e o e, he bes
solu ion is he de elopmen o a specialized co e, able o denoise an image in eal ime and wi h
low powe consump ion, wi hou comp omising he quali y o he es o ed image.
Wi h he educ ion o cos s in he ab ica ion o CMOS ci cui s, he FPGA pla o ms a e a e y
appealing solu ion o he as p o o yping o no el ha dwa e implemen a ions. Hence, he main
objec i es o his wo k a e: he de elopmen , on an FPGA, o a ully specialized co e o image
denoising using he BM3D algo i hm; achie e ex ensi e imp o emen s o he quali y o images;
and gua an ee eal ime pe o mance, wi h low powe consump ion.
1.3 Challenges
The ha dwa e implemen a ion o an image denoising algo i hm poses many challenges. To he
bes o he au ho ’s knowledge, he e is no wo k on he li e a u e add essing he ha dwa e imple-
men a ion o he BM3D image denoising algo i hm, which es ablishes he main challenge o his
wo k. Fu he mo e, a second challenge is ha he BM3D algo i hm is highly complex, con aining
in ensi e a i hme ic ope a ions ha need o be op imized. This is a challenge o designing as
ha dwa e ha can pe o m such ope a ions wi hou a loss o p ecision in he esul s ob ained. The
hi d challenge is he small amoun o wo k ound in he li e a u e ega ding he implemen a ion o
o he denoising algo i hms in ha dwa e. Hence, he a chi ec u e mus be de eloped almos om
sc a ch. The inal challenge ega ds he eal ime pe o mance and powe consump ion ade-o .
I is necessa y o push he limi s when designing ha dwa e ha needs simul aneously o be he
as es possible, while ope a ing wi h minimal powe consump ion.
1.4 S uc u e 3
1.4 S uc u e
In addi ion o he In oduc ion, his documen con ains i e mo e chap e s. In chap e 2, he back-
g ound on image denoising concep s is p esen ed. This is done in a op down app oach, s a ing
om mo e gene al concep s and owa ds mo e specialized ones wi h di ec applica ions in he al-
go i hm implemen ed. Fu he mo e, in his chap e , he cu en s a e o he a in image denoising
algo i hms and hei ha dwa e implemen a ions is p esen ed. In chap e 3, he chosen image de-
noising algo i hm is analyzed, as well as i s so wa e implemen a ion in MATLAB. The esul s o
his implemen a ion a e also p esen ed and discussed. Follows chap e 4, in which he ha dwa e
implemen a ion is analyzed in ex ensi e de ail, since his is he main ocus o his wo k. In chap-
e 5, he pe o mance o he implemen ed design is e alua ed, and se e al esul s a e p esen ed.
Finally, in chap e 6, he esul s and con ibu ions o his wo k a e summa ized, and possibili ies
o u u e wo k a e p esen ed.
10 Image Denoising and cu en S a e o he A
Figu e 2.2: 2D sepa able implemen ion o DWT and i s in e se. Taken om [8]
In o de o analyze images, i is necessa y o use a 2D DWT. This can be done by simply
applying he DWT on all ows and hen on all columns o he image, which esul s in ou ypes
o coe icien s, o sub-bands. These sub-bands con ain di e en image in o ma ion acco ding
o he il e ing applied, o example, he HH sub-band con ains diagonal ea u es o he image,
because i co esponds o high pass il e ing in bo h di ec ions and he LH sub-band con ains
e ical s uc u es, co esponding o low pass il e ing he columns and high pass il e ing he
ows. The same logic applies o he emaining sub-bands HL and LL. A sepa able implemen a ion
o he 2D DWT using il e banks can be seen in igu e 2.2.
Choosing he wa ele unc ion and he co esponding scaling unc ion (o equi alen ly he
decomposi ion and econs uc ion il e s) can be a cumbe some ask. To his end, he ex ensi e
s udies on wa ele s o igina ed se e al amilies o wa ele unc ions ha a e used in all wa ele
ela ed applica ions. Examples o his amilies a e he Haa -Wa ele , which is he i s wa ele
e e de ined; he Daubechies wa ele s, Dbpwi h p anishing momen s; and he bi-o hogonal
wa ele s Bio Nd.N wi h Nd anishing momen in he decomposi ion and N in he econs uc ion.
2.2.2 DCT
The disc e e cosine ans o m (DCT) is a equency domain ans o m, ha decomposes a gi en
signal in o a sum o cosine unc ions wi h di e en equencies [9]. By disca ding small high
equency componen s, he DCT is used o do lossy comp ession o audio (MP3 s anda d) and
images (JPEG s anda d). The DCT is e y simila o he amilia DFT, wi h he ob ious dis inc ion
being ha i uses only cosine unc ions o decompose a signal, ins ead o bo h cosines and sines.
The e a e eigh ypes o DCTs, howe e , he mos commonly used is he ype II DCT, which is
e e ed o as " he DCT" and is gi en by
Xk=
N−1
∑
n=0
xncosπ
Nn+1
2kk=0,...,N−1 (2.12)
This ans o m is equi alen o a DFT o 4N eal inpu s whe e he e en indexed elemen s a e
ze o. The co esponding in e se ans o m is he ype III DCT, which is e e ed o as IDCT, and

2.2 T ans o m domain denoising 11
is gi en by
Xk=1
2x0+
N−1
∑
n=1
xncosπ
Nk+1
2nk=0,...,N−1 (2.13)
The 2D DCT is simply a sepa able p oduc o he DCT along each dimension o an image,
i.e., he 1D DCT pe o med along he ows and hen he columns o he image. Fas compu a ion
o he DCT can be done by a special as cosine ans o m (FCT) which is simply an adap a ion
o he DFT coun e pa , he FFT. In image p ocessing, he 2D DCT is used o p ocess blocks,
commonly o size 8x8 (as in JPEG), which p oduces a ma ix o 64 coe icien s ha ep esen s
how much o each basis unc ions he image con ains. A isual ep esen a ion o his basis unc-
ions o g ayscale images can be seen in igu e 2.3. The i s coe icien ep esen s he lowes
equency (DC), and a eling in a zig-zag pa e n om he uppe le co ne o he lowe igh
co ne ep esen s an inc ease in equency o bo h dimensions.
Figu e 2.3: Basis unc ions o a 8x8 2D DCT
2.2.3 Ha d h esholding
The ha d h esholding ope a o is necessa y o il e ing he ans o m domain coe icien s o an
image, when a good es ima ion o he o iginal image powe spec um is no a ailable. Ha d
h esholding is he simples sh inkage ope a o and i can be seen as a "keep o kill" p ocedu e [7],
because all alues below a ce ain h eshold λa e se o ze o, while alues abo e he h eshold
emain he same. This is gi en by he ollowing exp ession
wλ=


wi |w|≥λ
0 i |w|<λ
(2.14)
A simila sh inkage ope a o is so h esholding, whe e coe icien s abo e he h eshold a e
sh unk in alue by he amoun o he h eshold λ. This means ha he so h esholding unc ion
is con inuous, which is an ad an age o some algo i hms whe e discon inuous ope a o s cause
p oblems. Plo s o bo h ope a o s can be seen in igu e 2.4.
12 Image Denoising and cu en S a e o he A
Figu e 2.4: a) Ha d h esholding ope a o . b) So h esholding ope a o . Adap ed om [7]
2.2.4 Wiene il e ing
Wiene il e ing is a s a is ical based app oach used o p oduce an es ima e o a a ge andom
p ocess, when a noisy measu emen is a ailable, as well as he signal and noise spec a. This way,
he Wiene il e minimizes MSE be ween he es ima ed p ocess and he desi ed one [10]. De i ing
he exp ession o he Wiene il e equi es a s a is ical app oach o images. In his app oach, an
image is modeled as a andom noise ield whose expec ed magni ude a each equency is gi en
by [8]
E[S(wx,wy)2] = Ps(wx,wy),(2.15)
whe e Ps(wx,wy)is he powe spec um o he image, and E[·]deno es he expec ed alue. Us-
ing his exp ession and p obabilis ic a gumen s, o example, he Bayes’ Rule, he 2D Fou ie
ans o m o he op imum Wiene il e needed o denoise an image, can be exp essed as
W(wx,wy) = Ps(wx,wy)
Ps(wx,wy)+σ2
n
,(2.16)
whe e σ2
nis he powe o he AWGN ha co up s he image. This way, he Wiene il e can be
used o denoising an image, when a good es ima ion o i s o iginal powe spec um is a ailable.
Fo in e es ed eade s, he comple e analysis o de i e he Wiene il e exp ession can be ound in
[8].
2.3 Comp essed Sensing based denoising
Spa se ep esen a ion o signals has been a hea ily esea ched subjec in he pas decade. The
b ie in oduc ion o his subjec p esen ed he e is based on M. Elad’s book, Spa se and Redun-
dan Rep esen a ions [11]. The main concep consis s in using an o e comple e dic iona y ma ix
D∈Rn×K, con aining Kp o o ype signal a oms, o ep esen a signal y∈Rnas a spa se linea
combina ion o hese a oms. Using his dic iona y, an exac ep esen a ion o he signal is gi en
2.3 Comp essed Sensing based denoising 13
as y=Dx. Howe e , in many applica ions, an exac ep esen a ion is ha d o ob ain, and hus, an
app oxima e solu ion is y≈Dx, subjec o ky−Dxkp≤ε. Measu ing he app oxima ion e o is
usually done using he `pno ms wi h p=1,2, and ∞.
When using o e comple e dic iona ies, i.e., n<K, an in ini e numbe o solu ions a e a ailable
o he ep esen a ion p oblem. This way, i is necessa y o impose cons ain s on he solu ion, and
since high spa si y is desi ed, he solu ion wi h ewes nonze o coe icien s is he mos appealing.
This spa ses app oxima e ep esen a ion is he solu ion o
(P0,ε)min
xkxk0subjec o ky−Dxk2≤ε,(2.17)
whe e k·k0is he `0no m, coun ing he nonze o en ies o a ec o .
As was al eady discussed, images can be spa sely ep esen ed using o example a wa ele
ans o m, leading o e ec i e denoising algo i hms using wa ele s ha exploi o e comple e ep-
esen a ions. In he case o wa ele s, he dic iona y is comple ely de ined when choosing he
wa ele and scaling unc ions and hei childs. Howe e , in he case o comp essed sensing (CS),
he goal is o achie e he spa ses ep esen a ion o an image in he spa ial domain, i.e., he dic-
iona y has o con ain he building blocks (a oms) necessa y o ep esen any image. This equi es
sol ing 2.17, which is p o en o be an NP-ha d p oblem [12]. The e o e, app oxima e solu ions
o he p oblem a e conside ed ins ead, wi h many app oxima ion algo i hms being p oposed in he
las ew yea s. These algo i hms a e in gene al g eedy and examples a e he ma ching pu sui and
o hogonal ma ching pu sui . The e is also he basis pu sui , which elaxes he `0no m in 2.17 o
an `1no m, con exi ying he p oblem. De ails abou hese algo i hms ex end beyond he scope o
his wo k, hence, de ailed desc ip ions can be ound, espec i ely in [13], [14] and [15].
In o de o de elop an e icien denoising algo i hm using a CS p io , he choice o dic iona y
is o pa icula impo ance. Fo his choice he e a e wo op ions: a se o p e-speci ied unc ions,
as is he case when using wa ele s, DCT o o he ans o ms; design he dic iona y by adap ing i
o i a gi en se o signal examples, as is he case when using aining based me hods, such as he
PCA and K-SVD.
2.3.1 PCA
P inciple componen analysis (PCA) is a s a is ical p ocedu e ha "ex ac s" he p incipal compo-
nen s o a se o obse a ions wi h co ela ed a iables using an o hogonal ans o ma ion. This
p incipal componen s a e linea ly unco ela ed, and hus PCA can e ec i ely deco ela e a signal.
I was i s o mula ed by Pea son in [16], and was u he de eloped by Ho elling in [17].
As desc ibed in he o iginal wo k o Pea son, he PCA can be seen as he line o plane ha
closes i s a sys em o poin s in an n-dimensional space. Each componen o he PCA "explains"
he a iance in he da a ha he p e ious componen is unable o i o, i.e., he i s componen is
a linea combina ion o o iginal a iables weigh ed so ha i ep esen s he maximum a iance in
he da a, he second accoun s o he a iance no ep esen ed in he i s , and so on.
14 Image Denoising and cu en S a e o he A
The PCA can be used o de elop a dic iona y o he da ase i is applied o, so i can be used
o ob ain such a dic iona y ha leads o a spa se ep esen a ion o an image, which can hen be
used o denoise said image. Usually he PCA is done by a singula alue decomposi ion (SVD),
which means i is a highly compu a ionally in ensi e me hod.
2.3.2 K-SVD
The K-SVD is a dic iona y aining algo i hm, ha u ilizes e ec i e spa se coding and a Gauss-
Seidel like accele a ed dic iona y upda e me hod. I is an ex ension o he popula k-means algo-
i hm, which is used o ain da a se s in clus e ing p oblems. The ull ope a ion o his algo i hm
is complex and so, i will no be p esen ed he e. The algo i hm i sel is p esen ed in igu e 2.5 and
was aken om he o iginal pape o M. Aha on, M. Elad and A. B ucks ein, K-SVD: An Algo i hm
o Designing O e comple e Dic iona ies o Spa se Rep esen a ion [18]. Fo hose in e es ed in
he algo i hm, please e e o his a icle o a de ailed explana ion.
Figu e 2.5: The K-SVD algo i hm. Taken om [18]
2.4 Rela ed Wo k 15
2.4 Rela ed Wo k
2.4.1 Denoising Algo i hms
Donoho and Johns one we e he i s o explo e he wa ele based denoising and he de elopmen
o he sh inkage algo i hm. In hei wo ks, hey applied wa ele heo y o signals in gene al, and o
di e en concep s o signal p ocessing and ma hema ics, such as minimax es ima ion [19], spa ial
adap a ion [20], and smoo h unc ions [21]. In Donoho’s wo k [22] he sh inkage o wa ele
coe icien s by applying so h esholding is used o denoise signals. O he wo ks using wa ele
sh inkage ound in he li e a u e a e [7], [23] and [24]. The wa ele ans o m can be used o
o m edundan ep esen a ions o blocks in an image, which esul s in a shi in a ian p ope y,
as desc ibed in [25].
Regula wa ele ans o ms a e no e ec i e when ep esen ing ce ain image ea u es, such
as smoo h ex u es. This esul s in blu ing when econs uc ing o denoising an image om i s
wa ele coe icien s. Taking his in o accoun , new me hods o denoise an image we e de el-
oped, using new mul iscale and di ec ional (aniso opic) ans o ms, such as he wedgele [26],
con ou le [27], cu ele [28], bandele [29] and s ee able wa ele [30].
Dabo e al. [1] p oposed in 2007 a no el me hod o image denoising based on collabo a i e
il e ing in ans o m domain. This algo i hm is called block ma ching and 3D il e ing (BM3D)
and comp ises h ee majo s eps. Fi s , a se o simila 2D image agmen s (i.e. blocks) is g ouped
in o 3D da a a ays ha a e e e ed o as g oups. This s ep is e e ed o as block ma ching.
Second, a 3D ans o m is applied o he g oups, esul ing in a spa se ep esen a ion, ha is il e ed
in he ans o m domain, and a e in e sion o he ans o m, p oduces he noise- ee p edic ed
blocks. This s ep is e e ed o as collabo a i e il e ing. Finally, he p edic ed noise- ee blocks a e
e u ned o hei o iginal posi ions o o m he eco e ed image. BM3D elies on he e ec i eness
o he block ma ching and collabo a i e il e ing o p oduce good denoising esul s.
Chen and Wu [31] p oposed a modi ica ion o he BM3D algo i hm ha achie es be e PSNR
and isual esul s o images con amina ed wi h high le els o noise. The me hod is called bounded
BM3D and i di e s om he o iginal BM3D in he block ma ching and collabo a i e il e ing o
he second s age o he algo i hm, i.e., he basic es ima e is compu ed in he same way o gene a e
a pilo signal o he second s age. The di e ence s a s in he beginning o he second s ep, whe e
he basic es ima e is pa i ioned in o egions (image segmen a ion) and he bounda ies be ween
hose egions a e de ec ed. This allows o a bounded sea ch in he block ma ching, i.e., only
blocks in he same image egion o he e e ence block a e candida es o g ouping. Howe e ,
a block can be con ained in wo o mo e egions (cohe en segmen s), and in his case, pa ial
block ma ching is applied, whe e blocks ha belong o se e al egions a e pa i ioned using bi-
na y masks o sepa a e he segmen s. This poses a g ea ad an age when compa ed o BM3D: he
pa i ioning a oids dealing wi h edges, hence a oiding p oblems when ep esen ing hem in 3D
ans o m domain. Ne e heless, in o de o do he wiene il e ing o hese non squa e segmen s,
shape adap i e DCT has o be applied as he 2D ans o m, which is mo e compu a ionally in-
ensi e. As p oposed, his me hod achie es be e PSNR, wi h gains o 0.23 - 1.33 dB compa ed

16 Image Denoising and cu en S a e o he A
o BM3D, and be e isual esul s, specially in edges and ex u es. I is wo h o ema k ha a
simila app oach was also aken by Dabo e al. in [32] wi h he de elopmen o shape adap i e
BM3D. Con inuing his esea ch, in [33], Dabo e al. p esen ed an imp o emen o hei p e ious
SA-BM3D algo i hm, called BM3D-SAPCA, whe e SAPCA s ands o shape adap i e p inciple
componen analysis. The PCA is applied ins ead o wa ele s o DCT o he 2D ans o m, and i
achie es be e denoising esul s han he p e ious BM3D me hods.
Elad and Aha on [34] de ised an image denoising me hod based on spa se ep esen a ions o e
lea ned dic iona ies. In he ans o m domain me hods, he e is also an implici dic iona y, gi en
by he a oms de ined by he 2D DCT o a wa ele ans o m. Howe e , his dic iona ies, in spi e o
being o e comple e, canno ep esen e icien ly all he in o ma ion in an image. This way, Elad
and Aha on esea ched he possibili y o using K-SVD o ain a global dic iona y, using a da abase
o noise ee images. They ound ha o he ask o image denoising, he choice o images o ain
on is c ucial, and while a good gene al dic iona y ha i s all images well can be ound, in o de o
achie e high denoising pe o mance (compa able o BM3D and o he me hods), a mo e complex
model is necessa y using se e al dic iona ies swi ched by con en . The e o e, in hei wo k, hey
adop ed a di e en di ec ion, by aining he dic iona y di ec ly on he noisy image. A a i s
sigh , his seems o ha e no impac in he o e all quali y o he algo i hm. Howe e , Elad and
Aha on ound a way o combine he denoising and aining s eps in o he same amewo k. The
algo i hm s a s wi h he DCT dic iona y and hen pe o ms Ji e a ions o spa se coding ollowed
by dic iona y aining, minimizing he ep esen a ion e o in each i e a ion. The esul s using his
adap i e dic iona y we e a mo e p omising han hose using a gene al dic iona y, which makes
his a e y a ac i e and obus me hod o image denoising.
Dong e al. [35] p esen ed a no el spa se ep esen a ion model o image es o a ion asks,
called cen alized spa se ep esen a ion (CSR). They in oduce he concep o spa se coding noise
(SCN), which is simply de ined as he di e ence be ween he coding ec o o he noisy image and
he coding ec o o he o iginal noise ee image. Howe e , in mos cases, he o iginal image is
no a ailable, and so, i s coding ec o is no known. Ne e heless, a good es ima o o his ec o
is i s mean alue, which in u n can be app oxima ed by he mean alue o he coding ec o o he
noisy image, by assuming ha he SCN has nea ly ze o mean (which is con i med empi ically in
hei wo k). This model is named cen alized spa se ep esen a ion because i en o ces he coding
ec o o app oach i s dis ibu ion cen e , i.e., he mean alue. In o de o compu e he mean
alue o he coding ec o , g oups o simila pa ches a e c ea ed, so ha hei spa se codes can be
a e aged, o each pa ch in he image. This way, he CSR model can be w i en as a minimiza ion
p oblem, uni ying he local spa si y o each pa ch and he nonlocal simila i y induced spa si y
( om simila pa ches) in o a a ia ional o mula ion ( wo a iable pa ame e s con ol he weigh o
each ype o spa si y). This model can be i e a ed un il con e gence: by se ing he ini ial es ima e
o he mean alue o he coding ec o o ze o, an ini ial es ima e is ob ained, om which he
g oups a e o med and he new mean alue is compu ed and used in he ollowing i e a ion. Being
a spa se ep esen a ion based model, CSR elies on a dic iona y, ha in his wo k is ob ained by
PCA. The CSR model con e ges o he desi ed spa se code when he join spa se coding and non-
2.4 Rela ed Wo k 17
local clus e ing alls in o a local minimum. Resul s o his me hod o image denoising a e e y
simila o hose achie ed by BM3D. In 2013, Dong e al. [36] p oposed a modi ica ion o hei
p e ious wo k on CSR, by adding he idea o nonlocali y o he spa se model, allowing o emo e
he local spa si y e m. This way, he nonlocally cen alized spa se ep esen a ion (NCSR) model
achie es be e denoising pe o mance wi h he same compu a ional e o .
One o he mos ecen wo ks on image denoising ound in he li e a u e is by Zhong e al.
[37]. In hei wo k a combina ion be ween he BM3D algo i hm and he nonlocal cen aliza ion
p io exploi ed in [35] allows o e y compe i i e esul s, pa icula ly o images co up ed wi h
high le els o noise. The main idea is o eplace he 1D ans o m wi h a sh inkage model based on
he nonlocal cen aliza ion p io . This allows he combina ion o he e iciency and e ec i eness
o wa ele o DCT ans o ms (when compa ed wi h he i e a ed app oach o he CSR model) and
he nonlocal and local spa si y uni ica ion p o ided by he CSR model. Mo eo e , he CSR model
is expanded by allowing he no ms used in he sh inkage unc ion o a y. This way, h ee di e -
en sh inkage unc ions a e p oposed: one aking ad an age o he `1no m o he local spa si y
and he `2no m o he nonlocal, o he wi h a double `1no m, and a inal one using a nonlocal
p io o emo e he local spa si y e m (as p oposed by [36]). In concluding ema ks, essen ially,
his wo k p oposes an e icien combina ion o he ans o m domain app oach o spa se ep e-
sen a ion o images and g oup ma ching ( om BM3D), wi h mo e op ions o ad anced sh inkage
unc ions (based on CSR and NCSR) o eplace he 1D ans o m and he ha d h esholding o
wiene il e ing used in BM3D.
F om he me hods p esen ed in his sec ion, he algo i hm chosen o his wo k was he o ig-
inal BM3D, because o i s high e iciency and e y good denoising pe o mance, wi h a e age
compu a ional bu den (when compa ed wi h dic iona y based me hods o example). This way, in
chap e 3 he BM3D algo i hm will be analyzed in ull ex en .
2.4.2 Ha dwa e Implemen a ions
Memik e al. [38],[39] we e among he i s o p opose an FPGA implemen a ion o an image
es o a ion algo i hm. The algo i hm used is a simple neighbo hood i e a i e es o a ion algo-
i hm, ha o each pixel in he image applies a con olu ion wi h a ke nel ha uses he eigh
neighbo pixels o es o e he ac ual pixel alue. The algo i hm is un o he numbe o i e a ions
necessa y so ha he esidual is unde a speci ied h eshold, and in each i e a ion, all he image
pixels a e p ocessed. Howe e , his is he so wa e app oach o he algo i hm, ha is e y slow,
which mo i a es he ha dwa e implemen a ion in o de o achie e a as e solu ion. The se up o
he ha dwa e consis s on a memo y o s o e he image, a pixel p ocesso ha execu es he algo-
i hm, and he channel o communica ion be ween bo h. Since he communica ion in his channel
is he bo leneck o he sys em, he e is no gain in execu ing he algo i hm as i is done in so -
wa e, by sending nine pixel alues a a ime and w i ing back o memo y. Ins ead, pa allelism o
he algo i hm is exploi ed, and an a ay o pixel p ocesso s allows o a pa allel compu a ion o
se e al pixel alues. Ne e heless, space in an FPGA is usually limi ed, and he numbe o pixel
p ocesso s usually is lowe han he numbe o pixels in an image ( o usual image esolu ions o
18 Image Denoising and cu en S a e o he A
256x256 o 512x512). This way, he image is segmen ed in o egions, and each egion is loaded
in o he FPGA, p ocessed, and s o ed back in o memo y. To a oid bo de e ec s and block a -
i ac s, he segmen s o he image a e allowed o o e lap, and he o e lapping es o ed po ions
a e disca ded. The ha dwa e implemen a ion desc ibed achie es up o a en imes speedup in he
un ime o he image es o a ion algo i hm.
Saldaña and A ias-Es ada [40] de eloped a econ igu able sys olic-based a chi ec u e o low
le el image p ocessing asks on an FPGA. The a chi ec u e is uned o allow he e icien con o-
lu ion o a il e ke nel wi h an image, in a windowing based app oach. The main module is a
2D cus omizable sys olic a ay, wi h he size o he window o be used, o p ocessing elemen s
(PEs). The image pixels a e ead om an ex e nal memo y and a e placed on in e nal memo ies
implemen ed as Block RAM’s, using a Rou e o manage he da a ans e s. The 2D sys olic a ay
is buil by in e connec ing se e al PEs, which a e ac i a ed e e y clock cycle, ollowing a pipeline
scheme. The PEs a e specially designed in o de o suppo he ope a ions in ol ed in mos win-
dow based ope a o s, and hei a chi ec u e consis s o an ALU, a shi egis e and an accumula o .
Each p ocessing elemen execu es h ee ope a ions in e e y clock cycle: compu a ion o he pixel
alue o be passed o he nex cycle, accumula ion o he ou pu egis e calcula ed a he p e i-
ous cycle wi h he new alue a he ou pu o he ALU and loading he new mask coe icien and
ansmission o he p e ious o he nex PE. Wi h he pipelined sys olic a chi ec u e, a h oughpu
o one window ou pu pe clock cycle is achie ed. Finally, he a chi ec u e was syn hesized in
a Xilinx Vi exE FPGA, wi h a 7x7 sys olic a ay (and co esponding sized window ope a ion),
esul ing in 49 PEs and an o e all a ea occupancy o 37%. The clock equency achie ed was
66MHz, esul ing in 200 ps o 640x480 esolu ion g ay le el images.
Joshi e al. [41] p esen ed an FPGA implemen a ion o a wa ele based image denoising al-
go i hm. This implemen a ion consis s o ou chained main modules: he li ing scheme based
wa ele module, he windowing module, he denoising module and he in e se wa ele module.
The i s module compu es he 2D DWT on he ows and columns o he image, by applying a
li ing scheme implemen a ion o he Daubechies 9/7 bio hogonal wa ele . Each wa ele module
compu es 4 ows and 4 columns a a ime hanks o 4 pa allel ow and column modules. The
second module is he windowing module, which con ains a ious shi egis e s in o de o im-
plemen neighbo hood obse a ion and o analyze he wa ele coe icien s o he di e en image
sub-bands. Then, he denoising module compu es he denoised coe icien , using di e en a i h-
me ic ope a ions implemen ed as a 10 inpu squa ing module, ollowed by a sub ac ion module,
a summa ion uni and a compa a o . Finally, he in e se wa ele module applies he in e se DWT
o he denoised coe icien s and s o es he denoised image in he image memo y. The esul s a e
p esen ed in e ms o ames pe second ( ps), i.e., how many images can be denoised pe second,
and he alues a e 83 ps o a 256x256 size image and 28 ps o 512x512.
B ylski and S zelecki [42] p oposed he implemen a ion o a pa allel image p ocesso . The
main idea o he implemen a ion consis s o a ma ix o ac i e nodes, which co espond o he
image pixels, connec ed wi h each o he by weigh s ha depend on he neighbo ing pixels. The
implemen a ion is in ended o pe o m segmen a ion ope a ions in bina y images. The design con-
2.4 Rela ed Wo k 19
sis s o a mic ocon olle connec ed wi h he PC by E he ne and wi h an FPGA by SPI. The FPGA
con ains a con ol uni and he ac i e ma ix o NxN nodes. The cen al uni block implemen s he
SPI connec ion and he clock manage ha con ols he ma ix o nodes. The node block con ains
se e al inpu /ou pu signals in o de o communica e wi h neighbo ing nodes, and i s s uc u e is
ai ly complex. The main block is he C d i e , ha pe o ms he node algo i hm and con ols he
wo k o o he node uni . The comple e module was syn hesized in a Xilinx FPGA wi h 17x17
ma ix elemen s and uses app oxima ely 85% o he slices in he FPGA.
In he wo k o Di Ca lo e al. [43], an adap i e image denoising IP co e (AIDI) is p esen ed,
in ended o eal ime applica ions. The algo i hm implemen ed is based on an adap i e gaussian
il e , which adap s i s a iance pixel by pixel acco ding o es ima es o he gaussian noise co -
up ing he image and he local a iance o he expec ed noise ee image. This way, he AIDI
co e con ains h ee main modules: he noise a iance es ima o (NVE), he local a iance es i-
ma o (LVE) and he adap i e gaussian il e . Fi s , he image pixels a e sen in pa allel o he
NVE and an ex e nal memo y h ough a 32 bi in e ace, and he NVE compu es he es ima ion
o he Gaussian noise a ec ing he image. Then, when his s ep is comple e, he image is loaded
o he LVE, ha compu es he local a iance associa ed wi h each pixel and ou pu s one o his
alues pe clock cycle, hanks o i s pipelined a chi ec u e. Finally, he ou pu s o he LVE and
NVE a e ed in o he adap i e gaussian il e , which compu es he op imal il e a iance and hen
il e s he image applying Gaussian smoo hing. The AIDI co e was syn hesized in a Xilinx Vi ex
6 FPGA, occupying close o 20% o he LUTs and 1.7% o he block RAMs, and achie ing 68 ps
o images wi h 1024x1024 pixels.
In Gabige -Rose e al. [44], image denoising is done in eal ime by a bila e al il e im-
plemen ed in a ully synch onized a chi ec u e on an FPGA. The implemen a ion p esen ed has
h ee main ad an ages, enabling eal ime p ocessing and e ec i e u iliza ion o esou ces: da a is
so ed in o equal g oups assigned o sepa a e pipelines, he clock equency is aised acco dingly
o he da a low and no ex e nal image bu e is necessa y. Each unc ional uni o he bila e al
il e consis s o a egis e ma ix, a pho ome ic il e and a geome ic il e . The egis e ma ix
is composed by se e al cascaded egis e s and mul iplexe s, allowing he pa allel calcula ion o
24 weigh s used by he ollowing il e s ages, and i s ou pu consis s o six g oups which a e ed
o he pho ome ic il e s age a ou imes he pixel clock. The pho ome ic il e consis s o six
iden ical pipelines, each p ocessing a g oup o pixels a e e y clock cycle, and he ou pu consis s
o he weigh ed pixels so ed in o six g oups, he cu en cen e pixel being compu ed and he pho-
ome ic coe icien s o each g oup. The inal s age is he geome ic il e , ha is implemen ed as
a sepa able 1D il e o he e ical and ho izon al di ec ions, and i s ou pu consis s o he il e ed
ke nel esul and a no maliza ion ac o . The no maliza ion o he esul s is done by a simple di i-
sion s age a he end o he da a pa h. The algo i hm was syn hesized in a Xilinx Vi ex 5 FPGA,
achie ing 52 ps o a 1024x1024 esolu ion image, and occupying 14% o slices, 23% o block
RAMs and 60% o DSP slices. In e ms o he denoising esul s, an app oxima e 0.2 dB loss was
e i ied when compa ing wi h he MATLAB implemen a ion o he algo i hm.
In all he wo ks p esen ed, some simila i y in he ha dwa e implemen a ion o image denoising
26 BM3D Denoising Algo i hm
3.3.4 Resul s
Wi h he MATLAB implemen a ion comple e, i s pe o mance is es ed on wo di e en images
(Came aman and Lena) and compa ed agains he o iginal BM3D.
Table 3.1: PSNR (dB) esul s o 256x256 Came aman Image
σNoisy Image O iginal BM3D Modi ied BM3D
5 34.16 38.20 34.79
10 28.13 33.94 31.25
15 24.62 31.67 29.42
20 22.12 30.24 28.18
25 20.18 29.14 27.16
30 18.60 28.25 26.28
35 17.30 27.41 25.53
40 16.10 26.33 24.83
45 15.08 26.07 24.21
50 14.16 25.55 23.65
Table 3.1 shows he PSNR esul s in dB o he image Came aman o bo h o iginal and modi-
ied BM3D. As expec ed, i can be seen ha he modi ied BM3D achie es wo se denoising esul s,
mainly due o he loss o spa si y by only using one le el o he haa wa ele decomposi ion. This
esul s amoun o an a e age absolu e PSNR loss o 2.13 dB ( ela i e loss o 7.11%). The di-
minished pe o mance o he modi ied BM3D can be con i med by he lowe isual quali y o he
esul image, which can be seen in igu e 3.1.
Table 3.2: PSNR (dB) esul s o 512x512 Lena Image
σNoisy Image O iginal BM3D Modi ied BM3D
5 34.15 38.63 36.84
10 28.14 35.65 34.30
15 24.62 33.83 32.58
20 22.12 32.47 31.32
25 20.19 31.37 30.32
30 18.60 30.46 29.52
35 17.26 29.65 28.84
40 16.10 28.72 28.24
45 15.08 28.45 27.72
50 14.16 27.92 27.24
Table 3.2 shows he PSNR esul s in dB o he image Lena o bo h o iginal and modi ied
BM3D. Once again, he modi ied BM3D achie es wo se denoising esul s. Howe e , his esul s
amoun o a smalle a e age absolu e PSNR loss o only 1 dB ( ela i e loss o 3.08%). This
smalle di e ence can be explained by he ac ha he Lena image is bigge (512x512 e sus

3.3 MATLAB Implemen a ion 27
256x256 o Came aman), meaning ha he e a e mo e simila blocks in he image, which en-
hances he spa si y o he ans o m domain coe icien s o each g oup, consequen ly imp o ing
il e ing. The esul images can be seen in igu e 3.2.
(a) O iginal Image (b) Noisy Image
(c) Modi ied BM3D (d) O iginal BM3D
Figu e 3.1: a) O iginal Came aman image wi h size 256x256; b) Noisy image wi h σ=25
(PSNR=20.18 dB); c) Basic es ima e image ob ained by modi ied BM3D (PSNR=27.16 dB); d)
Basic es ima e ob ained by o iginal BM3D (PSNR=29.14 dB)
28 BM3D Denoising Algo i hm
(a) O iginal Image (b) Noisy Image
(c) Modi ied BM3D (d) O iginal BM3D
Figu e 3.2: a) O iginal Lena image wi h size 512x512; b) Noisy image wi h σ=25 (PSNR=20.19
dB); c) Basic es ima e image ob ained by modi ied BM3D (PSNR=30.32 dB); d) Basic es ima e
ob ained by o iginal BM3D (PSNR=31.37 dB)
Chap e 4
Ha dwa e Implemen a ion
In his chap e , he ha dwa e implemen a ion o he modi ied BM3D algo i hm will be desc ibed
in de ail. This will be done in a op o bo om app oach, s a ing om he sys em a chi ec u e and
high le el desc ip ion, ollowed by a comple e cha ac e iza ion o each indi idual block and i s
ope a ion.
4.1 Sys em A chi ec u e
This sec ion p esen s a simple analysis o each block con ained in he sys em a chi ec u e, and i s
ope a ion. An o e iew o he sys em a chi ec u e is shown in igu e 4.1. The a chi ec u e can
be di ided in ou main elemen s: he a ay o ma ching p ocesso s; he denoising pipeline; he
a ious memo y modules, wi h di e en unc ions; and he mul i ude o con ol modules, which
a e no shown in he igu e o simpli ica ion pu poses.
The a ay o ma ching p ocesso s is esponsible o he block ma ching s ep o he BM3D
algo i hm. Each o he 16 ma ching p ocesso s pe o ms block ma ching o a di e en e e ence
block in pa allel. This e e ence blocks ha e o e lapping neighbo hoods ( wo consecu i e e e -
ence blocks ha e a shi o 4 pixels), meaning ha he a ay o p ocesso s ope a es on a "big"
neighbo hood, which is a conca ena ion o all neighbo hoods o each indi idual e e ence block,
and o e lapping da a is sha ed by successi e p ocesso s. When he a ay o p ocesso s comple es
i s ope a ion, each p ocesso ou pu s he posi ions o he 16 blocks ha ha e ma ched he e e -
ence block ( he i s posi ion is he e e ence block i sel ), and, since he e a e 16 p ocesso s, his
posi ions a e conca ena ed in a 16x16 bus.
Wi h he ma ching s ep done, and he g oup posi ions a ailable, ollows he collabo a i e il e -
ing s ep. This s ep is pe o med in he denoising pipeline, which ope a es as ollows: he posi ions
ou pu ed by he ma ching p ocesso s a e s o ed in a i o; hen, he blocks co esponding o wo
posi ions a e ex ac ed om an in e nal memo y con aining he "big" neighbo hood, a a a e o 1
ow pe clock cycle; hen, he collabo a i e il e ing is pe o med on hese blocks by an e icien
pipelined a chi ec u e ha implemen s he 2D DCT and Haa ans o ms, ha d h esholding and
29
30 Ha dwa e Implemen a ion
Figu e 4.1: BM3D Sys em A chi ec u e Block Diag am
he in e sion o said ans o ms; inally, he denoised blocks, hei posi ions and he g oup weigh
a e ou pu ed and s o ed in memo y blocks.
As can be seen in igu e 4.1, he e a e 8 memo y modules in he sys em a chi ec u e:
•Inpu Block RAM (BRAM), size 128 KBy es, 32 bi wide: holds he image da a in line
o de , i.e. consecu i e memo y posi ions con ain 4 consecu i e pixels o a line o he image.
•Nex neighbo hood memo y, size 104x39 pixels (4056 by es), inpu 32 bi wide, ou pu
104 pixels wide (832 bi ): con ains he nex neighbo hood o be p ocessed by he ma ching
p ocesso s.
•Bu e neighbo hood memo y, size 104x39 pixels (4056 by es), 104 pixels wide (832 bi ):
holds he neighbo hood cu en ly being p ocessed and eeds i o he denoising pipeline
when he ma ching s ep inishes.
•Posi ions ou pu memo y, size 512 By es, 32 bi wide: each memo y posi ion con ains wo
ela i e posi ions o i s co esponding image block.
•Weigh s ou pu memo y, size 16 By es, inpu 8 bi wide, ou pu 32 bi wide: each memo y
posi ion holds he weigh o a g oup.
•Two da a ou pu memo ies, size 8 KBy es each, inpu 64 bi wide, ou pu 32 bi wide: each
memo y posi ion con ains a ow o a denoised image block.
•Ou pu BRAM, size 32 KBy es, 32 bi wide: holds he ou pu da a o he BM3D algo i hm:
he denoised blocks, hei posi ions in he o iginal image and he g oup weigh s.
4.2 The Ma ching P ocesso 31
All he blocks desc ibed abo e need e y s ic con ol in o de o ope a e p ope ly. This is
achie ed by he ollowing 7 con ol modules:
•Nex memo y con ol module: esponsible o con olling da a ans e s be ween he inpu
BRAM and he nex neighbo hood memo y.
•Load denoise memo y con ol module: esponsible o loading he con en s o he bu e
memo y o he denoising pipeline.
•Posi ions memo y con ol module: esponsible o s o ing posi ions da a in he posi ions
memo y.
•Weigh s memo y con ol module: esponsible o s o ing weigh da a in he weigh s mem-
o y.
•Da a memo y con ol module: esponsible o s o ing denoised blocks da a in he pa allel
da a ou pu memo ies.
•Copy memo y con ol module: esponsible o con olling da a ans e s be ween he 4
ou pu memo ies and he ou pu BRAM.
•Mas e con ol module: as indica ed by he name, his module is esponsible o he con ol
o he whole sys em, i.e. i con ols all he modules desc ibed abo e, plus he in e nal con ol
modules p esen in he a ay o p ocesso s and he denoising pipeline.
Wi h he sys em a chi ec u e explained, he ollowing sec ions con ain a me iculous desc ip-
ion o he ope a ion o each module in he sys em.
4.2 The Ma ching P ocesso
This sec ion elabo a es on he ope a ion and design o he ma ching p ocesso . The schema ic o
he p ocesso is p esen ed in igu e 4.2. As can be seen, he p ocesso consis s o h ee modules:
a memo y; an a i hme ic uni ha calcula es he `1dis ance be ween wo blocks; and a so e uni
ha o de s and s o es he 16 smalle dis ances and espec i e block posi ions.
The ma ching p ocesso needs wo con ol modules in o de o ope a e co ec ly: a memo y
con ol module and a p ocesso con ol module. Howe e , as al eady men ioned, he BM3D sys-
em uses an a ay o 16 ma ching p ocesso s ope a ing in pa allel, meaning ha only one o each
con ol modules is necessa y in o de o con ol all p ocesso s a he same ime.
4.2.1 Memo y Module
The memo y module is esponsible o eeding he 8x8 blocks o he `1no m uni . The memo y is
s uc u ed in a speci ic way such ha i is possible o p o ide each consecu i e 8x8 block. This is
achie ed by using i e, 64 bi wide memo y LUTs ha ha e 39 posi ions and a e by e add essable.

32 Ha dwa e Implemen a ion
Figu e 4.2: Ma ching P ocesso Schema ic
The wid h is se o 64 bi s because his is exac ly he size o one block ow (8 pixels = 8x8 bi s).
Hence, i e memo ies in pa allel con ain 40 pixels, which means ha 8 bi s (1 pixel) a e ne e used,
since he neighbo hood size is 39x39. Howe e , his s uc u e is necessa y and e y e ec i e o a
sliding window app oach as will be explained nex .
Fi s ly, he numbe o bi s o each coo dina e needs o be de ined. Wi hin a 39x39 neighbo -
hood, 32x32 dis inc 8x8 blocks can be ound. The e o e, 5 bi s a e enough o code each coo dina e
o he block, i.e., each posi ion has 10 bi s: he ycoo dina e in he 5 mos signi ican bi s (MSBs)
and he xcoo dina e in he emaining 5 bi s. Now, le us conside o example ha he cu en
block being p ocessed is a x=13 and y=25. The 8x8 block de ined by his coo dina es spans
om x=13 o 20 and y=25 o 32. The ycoo dina e simply chooses he memo y posi ion, 25 in
his case, o he i s ow o be ex ac ed, meaning ha 8 clock cycles a e necessa y o p o ide a
ull 8x8 block. This, as i will be seen la e , is no a p oblem, since he `1no m uni accep s block
ows as inpu . The xcoo dina e howe e , has a di e en ea men : he 2 MSBs de ine a signal
called block and he emainde 3 bi s de ine a signal called shi . The alue 13 in bina y is gi en,
in 5 bi s, by 01101, meaning ha block =1 and shi =5. The block signal chooses he pai o
memo ies o be ead, i.e., in his case, he alue 1 indica es ha he desi ed block is ead om
memo ies 2 and 3 (memo ies a e numbe ed 1 o 5). Then, he shi signal indica es how many
by es (pixels) o each memo y should be selec ed, i.e., in his case, he alue 5 indica es he 3 leas
signi ican by es om memo y 2 and he 5 mos signi ican by es om memo y 3.
Ano he ad an age o his memo y s uc u e is ha a ull neighbo hood ow can be loaded
in o memo y a each clock cycle, because he i e in e nal memo ies can be loaded in pa allel.
This sa es some clock cycles when ini ializing he memo y, and p ocessing can e en s a a e he
i s ow ha con ains he e e ence block is loaded. This will be u he explained in he con ol
modules subsec ion (4.2.4).
4.2 The Ma ching P ocesso 33
4.2.2 `1no m Uni
In he block ma ching s ep, he dis ance ha needs o be calcula ed is gi en by:
d=
8
∑
i=1
8
∑
j=1|Xi,j
REF −Xi,j|,(4.1)
whe e Xi,j
REF is line numbe iand column numbe jo he e e ence block, and, acco dingly, Xi,jis
he same line and column om he block being ma ched.
Le us conside wo consecu i e 8x8 blocks in he e ical di ec ion o he image, X1and X2.
The dis ances o hese blocks a e gi en, espec i ely, by:
d1=
8
∑
i=1
8
∑
j=1|Xi,j
REF −Xi,j
1|and d2=
8
∑
i=1
8
∑
j=1|Xi,j
REF −Xi,j
2|(4.2)
Howe e , as he blocks a e consecu i e, i.e., hey only di e in one ow om one ano he , we can
w i e he ollowing ela ion:
X2=
8
[
i=1
Xi
2=
7
[
i=1
Xi+1
1∪X8
2(4.3)
This way, combining equa ions 4.2 and 4.3, we ge he ollowing exp ession o d2:
d2=
7
∑
i=1
8
∑
j=1|Xi,j
REF −Xi+1,j
1|+
8
∑
j=1|X8,j
REF −X8,j
2|(4.4)
Wi h his esul , i is possible o see, ha o calcula e he dis ance o each new 8x8 block, 7 ows
om he p e ious block can be eused. This is o majo impo ance o he design o he `1no m
uni , because i means ha a pipelined a chi ec u e can be de eloped, aking ad an age o se en
shi egis e s in o de o s o e he old ows o p e ious blocks. Wi h his a chi ec u e, an ou pu o
a new block dis ance pe clock can be achie ed, a e a lag o eigh clocks o he i s 8x8 block
o each neighbo hood column. As g ayscale images a e used, he maximum alue possible o
he dis ance is 64 ×255 <26×28=214, meaning ha he `1no m uni is designed wi h 14 bi
ope a ions, in o de o a oid o e lows.
Taking in o accoun he design conside a ions desc ibed, he `1no m uni ope a es as ollows:
1. The e e ence block is loaded line by line in o 8 egis e s connec ed in se ies (shi egis e ),
meaning ha in he end, he i s line is a he las egis e .
2. The same is done o he i s block o he i s neighbo hood column, wi h he di e ence
ha he e a e only 7 shi egis e s o s o e he 7 p e ious lines, while he cu en line is
di ec ly a he inpu o he module.
3. Follows an a ay o sub ac ions and a modulus ope a ion ha p ocess each pai o ow
egis e s, p oducing he `1no m o each pixel o each ow.
34 Ha dwa e Implemen a ion
4. Then, an adde ee wi h in e media e pipeline s ages sums each pixel dis ances o p oduce
he inal dis ance o he block being p ocessed. This ee s a s wi h 32 adde s (since he e
a e 64 pixels) and 32 egis e s and hen a each s age he numbe o blocks is hal ed.
The egis e ans e le el (RTL) schema ic o he `1no m uni can be seen in igu e 4.3. Wi h
his pipelined a chi ec u e, he `1no m uni in oduces a delay o 5 clock cycles, plus he ini ial
8 clock cycles o loading he i s block o each column. Hence, he e is a 13 clock cycle delay
be ween he s a o p ocessing and he cycle when he i s co ec dis ance is a he inpu o he
so e uni .
R0 R1 R2 R3 R4 R5 R6 R7
X1 X2 X3 X4 X5 X6 X7
|.| |.| |.| |.| |.| |.| |.| |.|
DATA
REF
LOAD
EN
… …
DIST
Figu e 4.3: RTL schema ic o he `1no m uni
4.2.3 So e Uni
The so e uni is esponsible o choosing he 16 smalle dis ances, om he 1024 (39x39 neigh-
bo hood has 32x32 dis inc 8x8 blocks) ha a e p oduced by he `1no m uni . The design o his
uni was adap ed om he wo k o Hussain e . al [46]. I consis s o 16 so e cells in se ies and
each cell con ains wo egis e s, one o s o e he dis ance and ano he o s o e he block posi ion
associa ed o ha dis ance, and a compa a o , ha checks i he inpu dis ance o he cell is smalle
han he cu en ly s o ed one. I i is indeed smalle , he inpu dis ance is s o ed in he cell, and he
p e iously s o ed one is passed on o he nex so e cell, o he wise, i he inpu dis ance is la ge , i
4.2 The Ma ching P ocesso 35
is di ec ly passed on o he nex so e cell. This way, a each clock cycle all he so e cells ope a e
in his manne and a new dis ance is inpu ed o he i s cell o he chain, e ec i ely so ing he
16 smalle dis ances. Hence, a e all dis ances ha e been compu ed, he e is a delay o 16 clock
cycles, a he wo s case. This happens when he las dis ance a ailable is he 16 h smalle and
needs o be passed by all he so e cells un il i eaches he las and i s inally s o ed. The RTL
schema ic o one single so e cell can be seen in igu e 4.4.
A he end o his 16 clock cycles, he i s cell in he chain con ains he smalle dis ance,
he second con ains he second smalle dis ance, and so o h. Each cell has a pa allel ou pu
connec ed o he posi ions egis e , and a he end o he so ing, he ou pu o each cell is ga he ed
in o a bus, ha now con ains he 16 posi ions o all he blocks ha ma ched he e e ence one,
e ec i ely o ming a g oup. In o de o allow a co ec so ing, each cell’s egis e is ini ialized
wi h he maximum possible alue (14 bi s a 1), so ha a ini ial s ages any dis ance compa ed
is always smalle . Due o he `1no m uni ’s a chi ec u e, he alues a he inpu o he so e
a e no always co ec . Hence, an holding mechanism was implemen ed, consis ing o a simple
mul iplexe con olled by an inpu denomina ed hold, ha when is se o one, inpu s he maximum
possible alue o he so e , so ha no egis e is changed.
Figu e 4.4: RTL schema ic o one so e cell
4.2.4 Con ol Modules
As p e iously men ioned, he a ay o ma ching p ocesso s is con olled by wo con ol modules:
he memo y con ol module and he p ocesso con ol module.
The memo y con ol module is modeled as a ini e s a e machine (FSM) wi h ou s a es and
i s s a e diag am can be seen on igu e 4.5. I ope a es as ollows:
42 Ha dwa e Implemen a ion
new da a is always lowing om he 1D ans o m in o he anspose , which s a s i s ope a ion
om he beginning ( he selec signal o he mul iplexe o e lows and s a s om 0), e ec i ely
pipelining his p ocess. This means ha he anspose con ibu es wi h a delay o 9 clock cycles
o he denoising pipeline.
Using 8 bi s o he g ayscale ep esen a ion o he inpu noisy image means ha all he alues
a e be ween 0 and 255. Howe e , when il e ing is pe o med, he ans o m domain coe icien s
o each pa ch a e modi ied (some a e disca ded), esul ing in he possibili y o p oducing nega i e
alues and alues la ge han 255 when in e ing he haa and DCT ans o ms. Hence, a ounding
module is necessa y in o de o a oid o e low/unde low when unca ing he 32 bi ep esen a ion
used in he denoising pipeline o he 8 bi one used in g ayscale images. The ounding module
analyses he 32 bi alue, and i i is bigge han 255, i is unca ed o 255. On he o he hand, i i
is smalle han 0, i is unca ed o 0. Values be ween 0 and 255 a e ounded o he nea es in ege ,
and ies (decimal pa equal o 0.5) a e ounded owa ds he nea es e en numbe .
Finally, he clock delay o he 2D DCT and IDCT modules can be compu ed by adding he
indi idual delays o each componen o he module. Each module has an inpu pipeline s age,
ollowed by he 1D ans o m, he anspose , and ano he 1D ans o m. This yields a delay
con ibu ion o 1+3+9+3=16 clock cycles o he denoising pipeline.
4.3.2 Haa T ans o m Modules
As p e iously men ioned, he e a e wo haa ela ed modules in he pipeline: he haa ans o m
and he in e se haa ans o m modules. The design o bo h modules is e y simple, since he haa
ans o m i sel is also e y simple.
As i is applied on he 3 d dimension o he g oup, and only one le el o decomposi ion is
possible, he haa ans o m akes he same pixel posi ion om each column o he wo blocks and
compu es i s sum and di e ence. This o igina es 8 sums and 8 di e ences, which a e di ided by
2 and co espond, espec i ely, o he low pass and high pass coe icien s. This can be exp essed,
o each column pixel, by he ollowing equa ions:
CLP =X1+X2
2and CHP =X1−X2
2(4.6)
This way, he haa ans o m module con ains: wo inpu egis e s, one o each block’s col-
umn; hen, eigh adde s and eigh sub ac o s ha compu e he coe icien s; and an ou pu egis e .
This means ha he haa ans o m con ibu es wi h a delay o 2 clock cycles o he denoising
pipeline.
The in e se haa module is a pu ely combina ional module, ha econs uc s he column da a
om he low pass and high pass coe icien s. This econs uc ion simply equi es addi ions and
sub ac ions o he co ec high pass and low pass coe icien s. Conside ing again each column
pixel, we ha e he ollowing exp essions:
X1=CLP +CHP and X2=CLP −CHP (4.7)

4.3 The Denoising Pipeline 43
This way, he in e se haa module con ains eigh adde s and eigh sub ac o s ha ope a e on
each pai o high pass and low pass coe icien s, ou pu ing he wo block’s columns. The RTL
schema ics o bo h he haa ans o m module and in e se haa ans o m module can be seen on
igu e 4.10.
DCT1
DCT2
HAAR
DCT1
DCT2
…
LP1
LP2
…
LP8
HP1
HP2
…
HP8
Figu e 4.10: RTL schema ics o he haa and in e se haa ans o m modules
4.3.3 Ha d Th esholding Module
The ha d h esholding module is esponsible o il e ing he ans o m domain coe icien s ha a e
conside ed o be noise. As p e iously explained, his is done by se ing o ze o he coe icien s ha
a e lowe , in absolu e alue, han a ce ain h eshold. Fu he mo e, he ha d h esholding module
is also esponsible o coun ing he numbe o non-ze o coe icien s in each g oup. The module
ope a es as ollows:
•The modulus o each o he 16 coe icien s is compu ed and a e he esul is compa ed o
he h eshold, using a less han ope a o .
•The ou pu o each o he compa a o s d i es he ese signal o a egis e , so ha i he alue
is 1, he egis e is se o ze o, o he wise i holds he o iginal alue o he coe icien .
44 Ha dwa e Implemen a ion
•In pa allel, he compa a o s ou pu s a e nega ed and summed by a ee o adde s, in o de o
coun he numbe o non-ze o coe icien s. This alue is added o an accumula o egis e ,
ha a he end o 64 clock cycles (16 blocks pe g oup, 8 ows pe block, 2 blocks in pa allel,
yields 16*8/2=64) holds he alue o he g oup weigh .
•This egis e is hen ese a he end o p ocessing o each g oup.
The ha d h esholding module only con ains 1 egis e o each inpu , meaning ha i con-
ibu es wi h a single clock cycle delay o he denoising pipeline. The RTL schema ic o he ha d
h esholding module can be seen in igu e 4.11.
HAAR
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
|.|
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
LP1
LP2
…
LP8
RST
…
HP1
HP2
…
HP8
RST
…
NNZ
……
…
…
RST
HT
WEIGHT
THRESHOLD
Figu e 4.11: RTL schema ics o he ha d h esholding module
4.3.4 Posi ion Memo y and Decode
The posi ions memo y consis s o a wide egis e , ha holds all he posi ions o he 16 g oups
o med in he block ma ching s ep, and ou pu s wo posi ions in pa allel. Since each pai o
coo dina es has 10 bi s, and each g oup has 16 blocks, he egis e has 10x16x16=2560 bi s. In
o de o ou pu he co ec posi ions, he posi ion memo y also has wo coun e s: a 3 bi clock
coun e and a 7 bi posi ion coun e . The clock coun e is necessa y so ha he posi ions a e
ou pu ed o 8 clock cycles, since he memo y module ou pu s one block ow pe clock cycle.
4.3 The Denoising Pipeline 45
Then, when he clock coun e eaches 7, he posi ion coun e is inc emen ed. Finally, he e is a
mul iplexe ha selec s he posi ions om he egis e acco ding o he posi ion coun e , i.e., when
he posi ion coun e is ze o, he 1s and 2nd posi ions o he egis e a e ou pu ed, and o each
inc emen in he coun e , he ollowing wo posi ions a e ou pu ed. This means ha o p ocess
all he g oups he numbe o clock cycles necessa y is 8*16*16/2=1024. The posi ion memo y is
con olled by wo signals: load ha enables he inpu o he egis e , and en, which enables he
clock coun e .
In be ween he ou pu o he posi ions memo y and he da a memo y, he e is a posi ion decode
module. This module is pu ely combina ional and con e s he posi ions o he co ec add esses
and shi s in he memo y module. This is done by summing he clock coun e alue o he yco-
o dina e (in o de o selec he co ec ow). Since each ma ching p ocesso ope a es on a local
neighbo hood, i s posi ions a e also local, meaning ha he xcoo dina e needs o be ansla ed o
he "big" neighbo hood ha con ains all he 16 ma ching p ocesso s. The s ep be ween each e e -
ence block is 4 pixels, which means ha his ansla ion is simply a sum o he local xcoo dina e
wi h 4 imes he ma ching p ocesso ID ( om 0 o 15). This way, i is assu ed ha he co ec
blocks a e ex ac ed om he da a memo y module.
4.3.5 Memo y Module
The da a memo y module used in he denoising pipeline ollows he same design as he mem-
o y in each ma ching p ocesso . Howe e , he e a e wo main di e ences. The i s is he size:
in he ma ching p ocesso each memo y holds a 39x39 neighbo hood, meaning ha i e, 64 bi
wide, memo ies wi h 39 posi ions a e used. Howe e , o he denoising pipeline, he mem-
o y needs o hold he ull neighbo hood o all he 16 ma ching p ocesso s, which is o size
(39+4*15)x39=99x39. In o de o s o e 99 pixels wi hou modi ying he size o each indi id-
ual memo y (8 pixels, i.e. a block ow), 13 memo ies a e necessa y, which amoun s o 104 pixels.
This means ha he las 5 pixels o he las memo y a e no ele an .
The second main di e ence is he ac ha his memo y module can ou pu wo ows in pa -
allel. This is needed due o he pa allelism necessa y o he haa ans o m o be applied in he
3 d dimension. To achie e his, he memo y con ains wo po s, each accep ing a line add ess
and shi and block signals, as in he ma ching p ocesso memo y. Fu he mo e, as happened in
he ma ching p ocesso ’s memo y, a ull neighbo hood ow can be loaded in a single clock cycle,
because all 13 in e nal memo ies ope a e in pa allel.
4.3.6 Con ol Module
The con ol module is ex emely impo an o he co ec ope a ion o he denoising pipeline,
because i needs o enable each module a he co ec clock cycle, in o de no o b eak he pipeline.
The clock cycle delay ha each module con ibu es o he pipeline was add essed in each module’s
46 Ha dwa e Implemen a ion
subsec ion. Hence, he o al delay o he pipeline is gi en by:
NCLK =16 +2+1+16 =35 (4.8)
RST
FIFO_DCT
FIFO_EN =1
DCT_EN=1
CNT_RST=0
POS_FLAG=1
START
IDLE
FIFO_EN=0
DCT_EN =0
CNT_RST=1
POS_FLAG=0
HAAR
HT_RST=1
HAAR_EN=1
POS_FLAG=0
CNT=15
IDCT
HT_RST=0
IDCT_EN=1
CNT=18
IDCT_DATA
VALID
DATA_VALID=1
HT_RST=0
FLAG=0
RST_HT
HT_RST=1
FLAG=1
GROUP++
FINAL
HOLD=1
POSX++
CNT=34
GROUP=0 & FLAG
CNT=17
CNT=34
Figu e 4.12: S a e diag am o he denoising pipeline con ol module
The denoising pipeline con ol module is modeled as an FSM wi h se en s a es and i s s a e
diag am can be seen on igu e 4.12. I ope a es as ollows:
1. Wai ing in IDLE o he s a signal, sen by he p ocesso con ol module in he a ay o
ma ching p ocesso s, ha signals he end o he block ma ching s ep.
2. When he s a signal is de ec ed wi h he alue 1, he s a e machine changes o s a e
FIFO_DCT, ha enables he posi ions memo y and he wo 2D DCT modules, as well as a
posi ion lag. Fu he mo e, an in e nal coun e is ac i a ed.
3. When he coun e eaches 15, he s a e machine changes o s a e HAAR, ha enables he
haa ans o m module. Al hough he 2D DCT in oduces a delay o 16 clock cycles, he
ansi ion alue o he coun e is 15, because he enable signal will only be seen wi h he
co ec alue a he haa ans o m module one clock la e o being changed in he con ol
module.
4. When he coun e eaches 18, he s a e machine changes o s a e IDCT, ha enables he
IDCT module, and disables he ese signal o he accumula o ha s o es he g oup weigh
in he ha d h esholding module.
4.4 Top Le el Module 47
5. When he coun e eaches 34, he s a e machine changes o s a e IDCT_DATA_VALID, ha
ac i a es he da a_ alid signal, indica ing ha he da a ou pu o he pipeline is al eady
alid.
6. When he coun e eaches 17, a e in ended o e lowing, he s a e machine changes o s a e
RST_HT, ha is a single clock s a e esponsible o ese ing he g oup weigh accumula o .
In his s a e, he e is also an ac i e lag, ha enables a egis e , which s o es he cu en g oup
weigh , be o e being ese . A e one clock cycle, he s a e e u ns o IDCT_DATA_VALID.
7. This p ocess is epea ed o e e y g oup, and when a g oup coun e o e lows ( eaches 0 o
he second ime), he s a e machine changes o s a e FINAL.
8. In his las s a e, he e is s ill a need o wai 16 clock cycles, so ha he las da a ows can
each he end o he pipeline ( om he ha d h esholding module o he end he e is a delay
o 16, in oduced by he 2D IDCT module). When his happens, he s a e machine changes
o s a e IDLE, and he collabo a i e il e ing s ep is done.
4.4 Top Le el Module
This sec ion elabo a es on he ope a ion and design o he op le el module. This module is
esponsible o connec ing he a ay o ma ching p ocesso s wi h he denoising pipeline, plus
he memo y and con ol modules necessa y o he co ec ope a ion o he sys em. The e a e six
memo y modules and se en con ol modules, which will all be explained in he ollowing sec ions.
4.4.1 Memo y Modules and Con ol
The i s memo y module is he nex neighbo hood memo y, which is esponsible o holding he
nex da a o be p ocessed, while he ma ching p ocesso s a e wo king on he cu en neighbo hood.
This memo y con ains 26 pa allel, 32 bi wide memo ies wi h 39 posi ions, so ha i holds a ull
104x39 neighbo hood. Each indi idual memo y is loaded sequen ially, selec ed by he shi inpu .
Howe e , he ou pu po o he memo y ga he s he ou pu o he same posi ion o all indi idual
memo ies. This way, he ou pu o he memo y can p o ide a ull neighbo hood ow (104 pixels)
a each clock cycle.
This memo y module is con olled by he nex con ol module. This module is an FSM wi h
ou s a es and ope a es as ollows:
1. Wai ing in s a e IDLE o he s a signal sen by he mas e con ol module, which signals
ha a new neighbo hood should be loaded om he inpu BRAM.
2. When he s a signal is de ec ed wi h he alue 1, he s a e machine changes o s a e
LOAD_ROW, ha ac i a es he w i e enable o he memo y, and s a s he coun e o
he shi signal.

48 Ha dwa e Implemen a ion
3. When he shi signal eaches he alue 24, he s a e machine changes o s a e ADDR_INC,
ha inc emen s he w i e add ess and ese s he shi alue.
4. I he w i e add ess is smalle han 38, meaning ha he e a e s ill ows o be loaded, he
s a e goes back o LOAD_ROW, and he p e ious s ep is epea ed. O he wise, he s a e
goes o FINAL, which is jus a single clock cycle bu e s a e ha ese s he s a e machine
a iables and sends he end pulse o he mas e con ol module. Finally, he s a e machine
mo es back o s a e IDLE.
This con ol module is also esponsible o de e mining he co ec ead add ess om he inpu
BRAM, in o de o e ch he co ec da a. The ead add ess is calcula ed om 5 o he a iables: he
w i e add ess, he shi signal, he wo coo dina es o he cu en neighbo hood being p ocessed
and a pa ame e called line_wid h. The ead add ess is gi en by:
ead_add =x_add +(K+8)∗y_add ,(4.9)
whe e x_add is he add ess pa due o he xcoo dina e, y_add is due o he ycoo dina e and
Kis he image wid h di ided by 4 (32 bi posi ions can hold 4 pixels). This mul iplica ion simply
"skips" he numbe o ows, so ha he co ec ow is selec ed. In o de o a oid his mul iplica ion,
he allowed alues o image wid hs a e ha d coded, and he line_wid h pa ame e con ols a
mul iplexe ha adds di e en shi s o he y_add o achie e he co ec esul . The allowed
image wid hs and co esponding line_wid h and K alues can be ound in able 4.1. These alues
a e he usually ound in es images (256x256 and 512x512) and eal images wi h 1, 2, 3, 5 and 8
megapixels.
Table 4.1: Ha d coded image wid hs
line_wid h Wid h K
0 256 64
1 512 128
2 1280 320
3 1920 480
4 2048 512
5 2560 640
6 3264 816
The cons an alue 8 in equa ion 4.9 is due o ze o padding he image. The image is padded
wi h a ame o ze os o size 15 in he op and le sides, and 17 in he igh and bo om sides. This
means an addi ional 32 (hence, 8 memo y posi ions) pixels in each image ow. The mul iplica ion
by (K+8)is hen implemen ed as addi ions and shi s, by inding he co ec sum o powe s o 2
ha sum o K. Fo he image wid hs conside ed, he shi s om 3 o 9 a e ha d coded, and hen
line_wid h con ols a mul iplexe ha sums he co ec shi s. Fo example, i he image wid h is
1280, Kis 320, which means ha he shi s 6 and 8 need o be summed, plus he ze o pad (shi o
3), which is independen o he image wid h.
4.4 Top Le el Module 49
The alues o x_add and y_add a e gi en by he ollowing equa ions:
x_add =x_cu << 4+shi ,
y_add =y_cu << 2+w_add ,
whe e x_cu and y_cu a e he coo dina es o he cu en neighbo hood ( hese a e signals sen
by he mas e con ol module). The shi o 2 in he ycoo dina e is due o s ep o 4 pixels be ween
e e ence blocks. Howe e , in he xcoo dina e, he shi is 4, since 16 p ocesso s in pa allel mean
ha he i s e e ence block om consecu i e neighbo hoods a e 16*4=64 pixels apa .
The second memo y module in he op le el is he bu e memo y. This memo y is he simples
in he a chi ec u e, because i only se es as a bu e be ween he ma ching p ocesso and he
denoising pipeline. When he neighbo hood o be p ocessed is loaded om he nex memo y o
he ma ching p ocesso s, i is pa allely loaded in o he bu e memo y. Then, when he p ocesso
con ol ac i a es he load_den_mem, he bu e con ol loads he con en s o he bu e memo y
in o he in e nal memo y o he denoising pipeline.
The bu e con ol module is a e y simple FSM wi h only wo s a es: IDLE and LOAD_MEM.
The s a e is IDLE un il he load_den_mem signal has he alue o 1. Then he s a e machine
changes o s a e LOAD_MEM and a coun e is ac i a ed. When his coun e eaches 38, he s a e
goes back o IDLE and he denoising pipeline memo y has he con en s o he bu e memo y.
The hi d memo y module is he posi ions memo y. This memo y s o es he posi ions o he
blocks ha a e ou pu ed by he denoising pipeline. The e a e 16x16=256 posi ions o be s o ed,
and each posi ion occupies 16 bi s, which means ha he posi ions memo y has a dep h o 128 and
is 32 bi wide. The wo mos signi ican by es o a memo y posi ion hold he posi ion o he block
ou pu ed by he second 2D IDCT module, and he emainde by es hold he o he posi ion.
The posi ion memo y is con olled by he posi ion con ol module. This module is an FSM
wi h ou s a es and ope a es as ollows:
1. Wai ing in s a e IDLE o he pos_ lag signal, sen by he denoising pipeline con ol when
he i s posi ions a e being ou pu ed.
2. When he pos_ lag signal is de ec ed wi h he alue 1, he s a e machine changes o s a e
WRITE, ha enables he w i e enable o he memo y and s a s a coun e , w i ing he i s
posi ions alue in he memo y. On he nex clock cycle, he s a e changes o WAIT and he
w i e enable is se o ze o.
3. When he coun e eaches he alue 7, meaning ha he posi ions a e going o change, he
s a e goes back o WRITE and he new posi ions a e w i en o memo y.
4. This s eps a e epea ed un il he add ess o e lows. When his happens, he s a e machine
changes o s a e FINAL, which is a bu e s a e, and hen back o IDLE.
The ou h memo y module is he weigh s memo y. This memo y s o es he g oup weigh s
ou pu ed by he denoising pipeline. Since he e a e 16 g oups, and each weigh occupies 8 bi s,
50 Ha dwa e Implemen a ion
he weigh s memo y is composed by 4 smalle memo ies, 8 bi wide and wi h 4 posi ions. The
memo y inpu is only 8 bi s and he e is a by e enable o choose in which memo y o s o e da a.
Howe e , as he ou pu will go o he ou pu BRAM, da a is ead om all ou memo ies in pa allel
in o de o ha e 32 bi s wid h.
This memo y is con olled by he weigh s con ol module. This module is an FSM wi h h ee
s a es: IDLE, WRITE and INC_ADDR. When in s a e IDLE, he s a e machine wai s o he
weigh lag, ha signals a new weigh is a ailable, and hen mo es o he WRITE s a e. In his
s a e he w i e enable o he memo y is ac i a ed and he weigh is s o ed. Fu he mo e, he by e
enable is inc emen ed, so ha he nex weigh is s o ed in he nex smalle memo y inside he
weigh memo y. I he by e enable has he alue o 3, he s a e changes o INC_ADDR, and he
w i e add ess is inc emen ed, and hen he s a e changes back o IDLE. This p ocess is epea ed
each ime he weigh lag as he alue 1. O he wise, i he by e enable is no 3, he s a e goes
di ec ly o IDLE, because an inc emen o he w i e add ess is s ill no necessa y.
The i h and six h memo y modules a e he same: da a memo y. This memo y s o es he
ac ual denoised blocks o he image. The e is a need o wo modules in pa allel because he
denoising pipeline ou pu s wo block ows pe clock cycle. The da a memo y consis s o wo 32
bi wide memo ies in pa allel, wi h 1024 posi ions. This alue is due o he size o he da a in 8x8
block ows, which is 16x16x8=2048, and each ow occupies 64 bi s (8 pixels). This way, each o
he memo ies is loaded wi h hal o a ow a he same add ess. When eading he da a ou o he
memo y, he LSB o he ead add ess ac s as he memo y selec o , in o de o consecu i ely ou pu
he co ec hal ows. These memo ies a e con olled by he da a con ol module. This module is a
simple coun e wi h he same bi s as he add ess o he memo ies (10 bi s). This coun e is enabled
by he da a_ alid signal, meaning ha while he da a ou pu ed om he denoising pipeline is
co ec , he add ess is inc emen ed and he da a is co ec ly s o ed in he da a memo ies.
Finally, he e is an addi ional module ega ding he memo y in e aces and i s con ol. This
is he copy con ol module, which is esponsible o copying he da a om he posi ions, weigh s
and da a memo ies in o he ou pu BRAM. I is modeled as an FSM wi h eigh s a es, ha con ols
he ead add ess o each memo y and he w i e add ess o he ou pu BRAM. The e is also a
mul iplexe ha is changed acco ding o which memo y is being copied. The ou memo ies a e
copied sequen ially, s a ing by he i s da a memo y, hen he second da a memo y, he posi ions
memo y, and inally he weigh s memo y. Be ween each copy he e is a s a e ha ese s he
ead add ess and inc emen s he mul iplexe selec signal. The w i e add ess howe e , is always
inc emen ed so ha da a is no o e w i en in he ou pu BRAM. The inal composi ion o he
ou pu BRAM is hen: all he da a om e en numbe ed blocks o he g oups (8 KB), ollowed
by all he da a om odd numbe ed blocks (8 KB), ollowed by all he posi ions (512 By es), and
inally all he g oup weigh s (16 By es).
4.4 Top Le el Module 51
4.4.2 Mas e Con ol
The las module o he op le el design is he mas e con ol module. As he name s a es, his
module is esponsible o con olling all he emaining con ol modules and he BM3D sys em
in gene al. This module has h ee egis e s o communica e wi h he ou side: a s a us egis e , a
con ol egis e and an image size egis e . The con ol egis e is used o issue commands o he
BM3D module, while he s a us egis e con ains he cu en s a us o ope a ion o he sys em, and
he image size egis e is used o inpu he image size, so ha he mas e con ol can compu e how
many neighbo hoods he image is di ided in o. The mas e con ol module is modeled as an FSM
wi h 12 s a es and i s s a e diag am can be seen on igu e 4.13. I ope a es as ollows:
RST
LOAD_FIRST
REQ_DATA
IDLE
FLAG_FIRST=1
RST_ALL=1
FSM_IDLE
COPY_FIRST
RST_ALL=0
START_NEXT=1
FSM_COPY
LOAD_NEXT
REQ_DATA
LAST_PROC
FLAG_LAST=1
START_PROCE
SSOR=1
FSM_PROC
FINAL
BM3D_DONE
COPY_NEXT
START_NEXT=1
FSM_COPY
COPY_MEM
START_COPY=1
FSM_COPY
WAIT
FSM_WAIT
START_PROC
START_PROCE
SSOR=1
FSM_PROC
DECIDE
FSM_IDLE
DATA_DONE
REQ_WRITE
BM3D_INIT DATA_AVLB
END
CURR_INC
INIT DATA_AVLB
! LAST_NEIGH
END
CURR_INC:
i (CURR_X=
WIDTH/32-1)
CURR_Y++
CURR_X=0
else
CURR_X++
DATA_VALIDCOPY_DONE
TRANSF_CMPLT
LAST_NEIGH:
CURR_X=0 & CURR_Y=
HEIGHT/4-1
LAST_NEIGH
LAST_NEIGH
& FLAG_LAST
LAST_NEIGH &
! FLAG_LAST
CLEAR
INIT
Figu e 4.13: S a e diag am o he mas e con ol module
1. Wai ing in s a e IDLE o he BM3D_INIT command in he con ol egis e . When his
command is de ec ed he s a e changes o LOAD_FIRST, ha se s he s a us egis e o he
alue REQ_DATA. This ells he use o he BM3D sys em ha he inpu BRAM can be
illed wi h da a.
58 Tes Me hodology and Resul s
2. The poin e s o w i ing/ eading o/ om he BRAMs and he AXI Li e egis e s a e c ea ed,
by using he ge add unc ion. Then, an unsigned cha a ay called da a, whe e he da a
om he ou pu BRAM is going o be s o ed, is alloca ed in memo y. Fu he mo e, wo
2D loa a ays wi h he size o he image a e alloca ed in memo y, in o de o pe o m he
agg ega ion p ocess, as desc ibed in sec ion 3.1.
3. The image size egis e is loaded wi h he image wid h and heigh and he sys em is ese by
w i ing 0xFF o he con ol egis e . Then, he BM3D_INIT alue is w i en o he con ol
egis e , as well as he es ima ed noise powe o he image.
4. The BM3D sys em s a s, and he p og am wai s o he ACK alue on he s a us egis e .
Then, i wai s o he REQ_DATA alue, which signals he i s da a eques om he sys em.
Wai ing is implemen ed as busy polling, i.e., a while con ol loop checking he alue o he
s a us egis e .
5. The i s 39 ows o he image a e loaded in o he inpu BRAM, by di ec ly copying he da a
om RAM o he BRAM, inside a o loop. Once he ans e is comple e, he DATA_AVLB
command is w i en o he con ol egis e , ollowed by wai ing o he ACK.
6. The p og am en e s a while loop, wi h exi condi ion being ha he s a us egis e has he
alue BM3D_DONE, which signals ha p ocessing is done. Inside he loop he e a e wo i
blocks: one o da a eques s and ano he o w i e eques s.
7. I a da a eques is de ec ed (con ol egis e wi h alue REQ_DATA), he p og am loads he
nex 4 ows o he image in o he inpu BRAM. Then, he same p ocedu e as in s ep 5 is
epea ed.
8. I a w i e eques is de ec ed (con ol egis e wi h alue REQ_WRITE), he p og am s o es
he da a om he ou pu BRAM sequen ially in he da a a ay. This is done in a o loop, by
di ec ly copying om he ou pu BRAM add ess poin e o each posi ion io he da a a ay.
Then, he agg ega ion s ep is pe o med o he da a a ailable.
9. The agg ega ion s ep consis s o a chain o o loops. The i s loop uns h ough each o
he 16 ma ching p ocesso s (16 g oups). Inside his loop, ano he one uns o each pai o
blocks in he g oup (1 o 8). Finally, he e a e wo mo e loops o each pixel o each block.
In he mos inne loop, each pixel alue is mul iplied by he kaise window and he g oup
weigh , and hen added o he co ec posi ion o he image bu e . A he same posi ion
o he weigh bu e , he mul iplica ion o he kaise window wi h he g oup weigh is also
added.
10. Once he agg ega ion is comple e, he TRANSF_CMPLT command is w i en o he con ol
egis e , ollowed by wai ing o he ACK.
11. When he BM3D sys em inishes p ocessing, he BM3D_DONE alue is placed in he s a us
egis e , and he while loop inishes. Follows a w i e in he con ol egis e o ese he

5.2 Resul s 59
sys em, and he inal cleanup o he C p og am (closing iles and clea ing memo y). Then,
he di ision o he image and weigh bu e s is compu ed, in o de o gene a e he esul
image. This is done by a loop, doing an elemen -wise di ision and w i ing he esul ing pixel
alue in o an ou pu ile. A he end o he p og am’s execu ion, his bina y ile con ains he
pixel alues o he whole image.
Du ing he execu ion o he C p og am, he clock unc ion is used o keep ack o he ime
spen in p ocessing asks by he CPU (agg ega ion) and in da a ans e s, as well as he o al ime.
This way, he ime spen by he algo i hm on he BM3D co-p ocesso is compu ed as he di e ence
be ween he o al ime and he p ocessing and da a ans e s imes.
5.2 Resul s
5.2.1 FPGA Resou ce Usage
As e e ed in sec ion 5.1, he ZYNQ boa d’s p og ammable logic has di e en esou ces a ailable
in di e en quan i ies o he implemen a ion o econ igu able designs. Table 5.1 shows he e-
sou ce usage o he BM3D sys em in e ms o absolu e alues and also pe cen age o u iliza ion o
he ZYNQ boa d.
Table 5.1: FPGA Resou ce Usage
Resou ce U iliza ion A ailable U iliza ion (%)
FF 87251 437200 19.96
LUT 89270 218600 40.84
Memo y LUT 15081 70400 21.42
BRAM 40.5 545 7.43
MMCM 1 8 12.50
As can be seen, he BM3D sys em needs a high numbe o ha dwa e esou ces, due o he
complexi y o he ope a ions pe o med. Howe e , he highes u iliza ion pe cen age is o LUTs
a a ound 41%, meaning ha he ZYNQ PL is unde 50% u iliza ion in all esou ces. Ne e heless,
he ZYNQ PL con ains a la ge numbe o esou ces, which can be misleading when analyzing he
occupa ion o he BM3D sys em. The high numbe o LUTs is due o he a i hme ic ope a ions
pe o med in bo h he ma ching p ocesso ’s `1no m uni s and he denoising pipeline’s 2D DCT
and IDCT modules. The lip- lop u iliza ion is mainly due o he pipeline s ages ha a e used in he
whole a chi ec u e, while he memo y LUT usage can be explained by all he special memo ies
included in he design, ha canno be syn hesized in BRAMs. The inpu and ou pu BRAM’s
occupy 40.5 o he BRAMs in he PL, while only 1 ou o 8 MMCMs is used. The alues p esen ed
a e o a equency o 50 MHz in he whole sys em. Wi h o he es ed equencies o he BM3D
sys em (75, 100 and 125 MHz) he occupa ion is i ually he same, as only he numbe o LUTs
changes, wi h a maximum a ia ion o 3 LUTs, which is negligible.
60 Tes Me hodology and Resul s
(a) Modi ied BM3D (MATLAB) (b) Modi ied BM3D (HW)
Figu e 5.2: a) Basic es ima e image ob ained by modi ied BM3D (PSNR=27.16 dB) in MATLAB;
b) Basic es ima e ob ained by modi ied BM3D (PSNR=27.17 dB) in ha dwa e. Noisy image was
co up ed wi h noise powe o 25.
5.2.2 Denoising Pe o mance
In o de o es he denoising pe o mance o he BM3D sys em, he ou pu aw image ile is
downloaded om he ZYNQ boa d o he PC and ead in o an a ay by a MATLAB sc ip . This
sc ip hen compu es he PSNR o he esul image, by compa ing i wi h he o iginal image.
Table 5.2: PSNR (dB) esul s o 256x256 Came aman Image
σNoisy Image O iginal BM3D Modi ied BM3D (MATLAB) Modi ied BM3D (HW)
5 34.16 38.20 34.79 34.82
10 28.13 33.94 31.25 31.31
15 24.62 31.67 29.42 29.46
20 22.12 30.24 28.18 28.19
25 20.18 29.14 27.16 27.17
30 18.60 28.25 26.28 26.29
35 17.30 27.41 25.53 25.52
40 16.10 26.33 24.83 24.83
45 15.08 26.07 24.21 24.23
50 14.16 25.55 23.65 23.65
Table 5.2 shows he PSNR esul s in dB o he image Came aman o he o iginal BM3D
algo i hm, as well as bo h he modi ied e sions: implemen a ion in MATLAB and ha dwa e. As
men ioned in subsec ion 3.3.4, he modi ied BM3D achie es wo se denoising pe o mance. In
he able, i can be seen ha he ha dwa e implemen a ion esul s a e as expec ed by he alues
ob ained in MATLAB, wi h he majo i y o imes e en being sligh ly be e . Howe e , he PSNR
di e ence is minimal (in he ange o 0 o 0.03 dB), meaning ha in e ms o isual quali y he
5.2 Resul s 61
images a e i ually he same. This can be con i med by compa ing bo h images side by side,
as shown in igu e 5.2. Ne e heless, his small PSNR di e ence can be explained by he ac
ha di e en ounding is used in he MATLAB and ha dwa e implemen a ions. In MATLAB,
each pixel is ounded o an 8 bi g ayscale ep esen a ion a e he agg ega ion s ep, i.e., he e is a
possibili y ha some pixels a e la ge han 255 o smalle han 0, because each pixel o each il e ed
block is no indi idually ounded. Howe e , in he ha dwa e implemen a ion, his is exac ly wha
happens, wi h each pixel being ounded a he ou pu o he denoising pipeline. This way, i is
gua an eed ha du ing he agg ega ion s ep, since a weigh ed a e age is used, he pixel alues
ne e go ou side he 0 o 255 ange.
Table 5.3: PSNR (dB) esul s o 512x512 Lena Image
σNoisy Image O iginal BM3D Modi ied BM3D (MATLAB) Modi ied BM3D (HW)
5 34.15 38.63 36.84 36.86
10 28.14 35.65 34.30 34.33
15 24.62 33.83 32.58 32.61
20 22.12 32.47 31.32 31.36
25 20.19 31.37 30.32 30.35
30 18.60 30.46 29.52 29.55
35 17.26 29.65 28.84 28.87
40 16.10 28.72 28.24 28.25
45 15.08 28.45 27.72 27.73
50 14.16 27.92 27.24 27.24
Table 5.3 shows he PSNR esul s in dB o he image Lena o he o iginal BM3D algo i hm,
as well as bo h he modi ied e sions: implemen a ion in MATLAB and ha dwa e. Once again,
he modi ied BM3D achie es wo se denoising esul s, and he implemen a ions in MATLAB and
ha dwa e ha e he same esul s. Figu e 5.3 shows he esul images o bo h implemen a ions o
he modi ied BM3D algo i hm.
Wi h he BM3D sys em alida ed agains he MATLAB implemen a ion, a mo e ex ensi e
expe ience was pe o med. This expe imen consis ed o es ing all 512x512 images in he image
da ase used by he o iginal BM3D pape wi h he same noise powe s om he expe iences be o e:
5 o 50 in s eps o 5. Then, all he esul s ob ained o each noise powe a e a e aged o all he
images in he da ase . This da ase consis s o 6 images wi h 512x512 esolu ion: Lena, Ba ba a,
Boa s, Man, Couple and Hill. These a e all s anda d images used o es ing in image p ocessing.
The PSNR and SSIM o each image was measu ed, and a compa ison o he esul s o he noisy
image, he o iginal BM3D and he modi ied BM3D on ha dwa e can be seen in he g aphs shown
in igu e 5.4.
The esul s show ha bo h he PSNR and SSIM measu emen s o he ha dwa e implemen a-
ion ha e a ela i ely la ge dec ease when compa ed o he o iginal BM3D algo i hm o low noise
powe s, wi h a sligh inc ease when compa ed wi h he noisy image measu emen s. Howe e ,
as he noise powe inc eases, he esul s o he ha dwa e implemen a ion s a o ge on pa wi h
62 Tes Me hodology and Resul s
(a) Modi ied BM3D (MATLAB) (b) Modi ied BM3D (HW)
Figu e 5.3: a) Basic es ima e image ob ained by modi ied BM3D (PSNR=30.32 dB) in MATLAB;
b) Basic es ima e ob ained by modi ied BM3D (PSNR=30.35 dB) in ha dwa e. Noisy image was
co up ed wi h noise powe o 25.
hose o he o iginal BM3D, and bo h o hem a e ex emely la ge when compa ed o he noisy
image. The PSNR di e ence be ween bo h implemen a ions anges om an absolu e maximum
o 2.48 dB o noise powe o 5 o a minimum o 0.81 o noise powe o 50, which co esponds,
espec i ely o 6.58% and 2.97% in ela i e di e ence. Rega ding he SSIM measu emen s, he
di e ence anges om a maximum o 0.046 o noise powe o 15 o a minimum o 0.011 o
noise powe o 50, which co esponds, espec i ely o 5.46% and 1.61% in ela i e di e ence.
Table 5.4: PSNR (dB) esul s compa ison o 1,2,3,5 and 8 MP images.
σNoisy Ci y Coa B idge Palace NYC
SW HW SW HW SW HW SW HW SW HW
10 28.14 34.27 31.95 37.61 36.59 35.21 33.02 35.83 34.29 38.08 37.29
20 22.11 30.31 28.28 34.32 33.29 31.45 29.24 32.23 30.44 34.29 33.59
30 18.59 28.15 26.28 32.28 30.85 29.18 26.97 30.14 28.21 32.02 31.25
40 16.09 26.01 24.88 30.70 28.84 27.02 25.30 28.47 26.56 30.24 29.38
50 14.14 25.30 23.83 29.83 27.06 26.11 23.98 27.43 25.20 29.31 27.76
Now ha he good pe o mance o he BM3D sys em o images o low esolu ions is es ab-
lished, mo e es s a e necessa y o images o highe esolu ions. Since he e a e no s anda d
es images wi h high esolu ions a ailable, an 8MP came a was used o ake some pic u es and
hen hese pic u es we e downsampled o he ollowing esolu ions: 1MP - 1280x960, 2MP -
1920x1080, 3MP - 2048x1536, 5MP - 2560x1920 and he o iginal esolu ion o 8MP - 3264x2448.
In o de o main ain he quali y o he pic u es, he downsampling was pe o med in a ee image
p ocessing so wa e. This expe imen consis ed o es ing hese images wi h noise powe s o 10 o
5.2 Resul s 63
50 in s eps o 10, in bo h he o iginal BM3D algo i hm and ha dwa e implemen a ion, and com-
pa ing he esul s by measu ing PSNR and SSIM. The esul s o his expe imen can be ound in
ables 5.4 and 5.5.
Table 5.5: SSIM esul s compa ison o 1,2,3,5 and 8 MP images.
σNoisy Ci y Coa B idge Palace NYC
SW HW SW HW SW HW SW HW SW HW
10 0.582 0.944 0.920 0.927 0.920 0.941 0.921 0.940 0.924 0.951 0.949
20 0.331 0.882 0.856 0.874 0.882 0.889 0.871 0.878 0.858 0.896 0.910
30 0.222 0.819 0.804 0.817 0.844 0.831 0.824 0.818 0.811 0.834 0.877
40 0.162 0.748 0.761 0.759 0.809 0.766 0.780 0.759 0.776 0.770 0.848
50 0.124 0.715 0.725 0.739 0.775 0.737 0.740 0.727 0.747 0.746 0.821
The esul s show ha o la ge image esolu ions he BM3D sys em con inues o unde -
pe o m he o iginal implemen a ion’s PSNR esul s a abou 1 o 2 dB. Howe e , o high noise
powe s, i can be seen ha he SSIM alues achie ed by he BM3D sys em su pass he ones ob-
ained by he so wa e implemen a ion. Some esul images ob ained in his expe imen can be
ound in appendix A, as well as he o iginal images.
5.2.3 Execu ion Time
Rega ding he execu ion ime o he algo i hm, es ing was done on wo di e en CPUs and on he
ZYNQ boa d. In he CPUs, he o iginal C so wa e p o ided by he au ho s o he o iginal BM3D
pape was used 1.
Table 5.6: FPGA execu ion ime esul s (in seconds) o images o inc easing esolu ions and
equencies.
Image (Resolu ion) FPGA @50MHz @75MHz @100MHz @125MHz
Came aman (256x256) 0.02883 0.01962 0.01492 0.01216
Lena (512x512) 0.11640 0.07911 0.06008 0.04864
Ci y (1MP - 1280x960) 0.54903 0.37282 0.28280 0.22884
Coa (2MP - 1920x1080) 0.92683 0.62986 0.47768 0.38681
B idge (3MP - 2048x1536) 1.40597 0.95502 0.72380 0.58497
Palace (5MP - 2560x1920) 2.20020 1.49499 1.13421 0.91690
NYC (8MP - 3264x2448) 3.58071 2.43341 1.84608 1.49307
Table 5.6 con ains he execu ion imes o images o inc easing esolu ions wi h cons an noise
powe o 20, unning on he ZYNQ boa d, wi h he BM3D sys em ope a ing a 50,75,100 and 125
MHz. Table 5.7 con ains he esul s o he execu ion imes o he same images on wo CPUs:
CPU1, which is an In el i5-3317U p ocesso , unning a 1.7 GHz, and CPU2, an In el i5-4570
p ocesso , unning a 3.2 GHz. Be e esul s a e expec ed om CPU2, since i is a desk op
1So wa e a ailable a h p://www.cs. u . i/ oi/GCF-BM3D/

64 Tes Me hodology and Resul s
p ocesso , wi h mo e p ocessing powe and unning a a highe equency, while CPU1 is a low
powe lap op p ocesso .
Table 5.7: Compa ison o CPU and FPGA @125MHz execu ion ime esul s (in seconds) o
images o inc easing esolu ions.
Image (Resolu ion) CPU1 @1.7GHz CPU2 @3.2GHz FPGA @125MHz
Came aman (256x256) 0.59360 0.35580 0.01216
Lena (512x512) 2.38350 1.49210 0.04864
Ci y (1MP - 1280x960) 11.2099 7.26179 0.22884
Coa (2MP - 1920x1080) 20.3389 12.9978 0.38681
B idge (3MP - 2048x1536) 30.0177 19.3971 0.58497
Palace (5MP - 2560x1920) 47.5931 30.8079 0.91690
NYC (8MP - 3264x2448) 82.4164 51.3583 1.49307
As can be seen by hese esul s, he BM3D sys em is signi ican ly as e han bo h CPUs es ed.
To be e e alua e hese esul s, he speedup alue is compu ed, which is simply he di ision o he
execu ion ime on he CPUs and on he ZYNQ boa d. This alue was compu ed o all equencies
o ope a ion and compa ing wi h bo h CPUs and he esul s a e p esen ed in he g aphs shown in
igu e 5.5.
As can be seen in he g aphs, he p o ile o he speedup esul s is qui e simila , wi h an almos
mono onic inc ease wi h he esolu ion o he image. Fo he BM3D sys em unning a 50 MHz
(blue) and compa ing wi h CPU1, he speedup alues ange om 20.6 o 23.0, a e aging 21.4. Fo
inc easing equencies, he alues a e e en highe : a e age o 31.4 o 75 MHz (g ey), 41.4 o
100 MHz (o ange) and 51.1 o 125 MHz (yellow). When compa ing wi h CPU2, he alues a e
smalle , due o he highe pe o mance o his p ocesso . E en so, he speedup anges om 12.3 o
14.3 in he slowe equency o 50 MHz, up o 29.3 o 34.4 o he highes equency (125 MHz).
These esul s a e e y sa is ac o y, since he ZYNQ boa d uns a a much lowe equency han he
CPUs. I is also wo h no ing ha as he image esolu ion inc eases, he speedup also inc eases,
meaning ha he BM3D sys em can handle bigge images wi h mo e ease han he CPUs.
No included in he execu ion ime esul s a e he da a ans e imes and agg ega ion imes.
The da a ans e s using he expe imen al se up a ailable a e qui e slow. This is due o a bo leneck
in using he AXI gene al pu pose mas e po s o he PS, which can only ope a e a 50 MHz, and
he in e connec o he PL is no an high bandwid h one (only 32 bi wide). A solu ion o his
would be o use one o he high pe o mance (HP) AXI po s a ailable in he connec ion be ween
he PS and he PL, which allow 64 bi wide di ec access o he sys em’s RAM. Howe e , hese
a e AXI sla e po s, meaning ha he BM3D IP would ha e o implemen an AXI ull Mas e in
o de o con ol all he da a ans e s i sel . While his is an ad an age, because he BM3D IP
ope a es wi hou supe ision o he CPU, di ec ly e ching da a om he RAM h ough he HP
sla e po s, he AXI Mas e logic is ha de and mo e ime consuming o implemen and i is no
a ailable in he IP ca alog o he Xilinx Vi ado ool. Since his a e da a ans e s, and hei ime is
no coun ed as ime ac ually pe o ming he BM3D algo i hm, he easie and as e app oach was
5.2 Resul s 65
aken, and he da a ans e imes dis ega ded. The same applies o he agg ega ion p ocess, which
is done simul aneously by he ARM CPU while he BM3D sys em is ope a ing. The ARM CPU
ope a es a a equency o 666 MHz, and has much less p ocessing powe han he CPUs used o
un he BM3D algo i hm on a PC. This way, a di ec compa ison o he wo imes wouldn’ be
possible. Fu he mo e, he agg ega ion only con ibu es o abou 2% o he ime consump ion in
he BM3D algo i hm, since he block ma ching and collabo a i e il e ing s eps a e much mo e
compu a ionally in ensi e.
5.2.4 Powe Consump ion
The powe consump ion dis ibu ion o he BM3D sys em o he di e en syn hesized equencies
is shown in igu e 5.6. These alues we e ob ained using he analysis p o ided by he Vi ado
Design Sui e a e he design is implemen ed.
Fo all equencies, powe consump ion is be ween 2 and 3 Wa s, which is low conside ing
he amoun o FPGA esou ces used and he complexi y o he BM3D algo i hm. Fu he mo e, i
is possible o see ha a good dis ibu ion o dynamic e sus s a ic powe is achie ed, wi h 89 o
91% o dynamic powe and 11 o 9% s a ic powe . The s a ic powe inc ease wi h equency is
comple ely negligible, wi h only an inc ease o 4 mW be ween 50 and 125 MHz. On he o he
hand, he dynamic powe inc eases ai ly wi h he equency, which amoun s o he o al inc ease
o he powe consump ion. This inc ease is pe cep ible in he Clocks, Signals and Logic ca ego ies
o he dynamic powe , whils he BRAM and MMCM modules powe usage s ays cons an . This
is due o he ac ha he inc eased equency is applied o he BM3D IP co e, and no o he
emainde o he design (AXI Li e, BRAM, PS), meaning ha all he signals and logic will ha e
inc eased swi ching, he e o e consuming mo e powe .
F om he powe dis ibu ion cha s, i can be seen ha he alues o each ca ego y do no add
up o he dynamic powe shown. When his disc epancy was de ec ed, he alues o each ca ego y
we e summed and hen he sum was sub ac ed om he alue shown. Fo all equencies his
calcula ion always yielded he same alue, 1.568 W, which is he dynamic powe consump ion
es ima ion o he PS o he ZYNQ boa d, because his alue ne e changes. Fu he mo e, when
syn hesizing only he BM3D IP co e, he s a ic powe consump ion s ayed abou he same alue
o 0.25 W. This is belie ed o be he s a ic powe consump ion o he PL pa o he ZYNQ SoC.
This way, he powe consump ion can be ecalcula ed o spli he powe usage o he PS and he
PL. The esul s o his ecalcula ion can be ound in able 5.8.
Table 5.8: PL and PS powe consump ion (W) o di e en equencies o ope a ion.
F equency @50MHz @75MHz @100MHz @125MHz
Powe Usage 2.350 2.538 2.748 2.928
PS Powe 1.568 1.568 1.568 1.568
PL Powe 0.782 0.970 1.180 1.360
66 Tes Me hodology and Resul s
(a) A e age PSNR
(b) A e age SSIM
Figu e 5.4: a) A e age PSNR (dB) o 512x512 images wi h noise powe s om 5 o 50. b) A e age
SSIM o 512x512 images wi h noise powe s om 5 o 50.
5.2 Resul s 67
(a) FPGA s CPU1
(b) FPGA s CPU2
Figu e 5.5: a) FPGA s CPU1 speedup o inc easing image esolu ions. b) FPGA s CPU2
speedup o inc easing image esolu ions. Images a e in he same o de as in ables 5.6 and 5.7.
74 Resul Images
(a) Noisy Image wi h sigma=20
(b) Denoised Image
Figu e A.3: a) Noisy image Coa wi h noise powe o 20. b) Denoised image wi h PSNR=33.29
dB and SSIM=0.882.

Resul Images 75
(a) Noisy Image wi h sigma=50
(b) Denoised Image
Figu e A.4: a) Noisy image B idge wi h noise powe o 50. b) Denoised image wi h PSNR=23.98
dB and SSIM=0.740.
76 Resul Images
(a) Noisy Image wi h sigma=30
(b) Denoised Image
Figu e A.5: a) Noisy image Palace wi h noise powe o 30. b) Denoised image wi h PSNR=28.21
dB and SSIM=0.811.
Resul Images 77
(a) Noisy Image wi h sigma=40
(b) Denoised Image
Figu e A.6: a) Noisy image NYC wi h noise powe o 40. b) Denoised image wi h PSNR=29.38
dB and SSIM=0.848.
78 Resul Images
Re e ences
[1] K. Dabo , A. Foi, V. Ka ko nik, and K. Egiaza ian. Image Denoising by Spa se 3-
D T ans o m-Domain Collabo a i e Fil e ing. IEEE T ansac ions on Image P ocessing,
16(8):2080–2095, Augus 2007.
[2] S Asha, S Bhu ana, and R Radhak ishnan. A Su ey on Con en Based Image Re ie al
Based on Fea u e Ex ac ion. In . J. No el. Res. Eng & Pha m. Sci, 1(06):29–34, 2014.
[3] Alan C. Bo ik. Handbook o Image and Video P ocessing. Academic P ess, 2010.
[4] A Buades, B Coll, and J Mo el. A Re iew o Image Denoising Algo i hms, wi h a New One.
Mul iscale Modeling & Simula ion, 4(2):490–530, 2005.
[5] Z. Wang, A.C. Bo ik, H.R. Sheikh, and E.P. Simoncelli. Image Quali y Assessmen : F om
E o Visibili y o S uc u al Simila i y. IEEE T ansac ions on Image P ocessing, 13(4):600–
612, Ap il 2004.
[6] I Daubechies. Ten Lec u es on Wa ele s. Socie y o Indus ial and Applied Ma hema ics,
1992.
[7] Maa en Jansen. Noise Reduc ion by Wa ele Th esholding, olume 161 o Lec u e No es in
S a is ics. Sp inge New Yo k, New Yo k, NY, 2001.
[8] Richa d Szeliski. Compu e ision: algo i hms and applica ions. 2010.
[9] N. Ahmed, T. Na a ajan, and K.R. Rao. Disc e e Cosine T ans o m. IEEE T ansac ions on
Compu e s, C-23(1):90–93, Janua y 1974.
[10] Robe G o e B own and Pa ick Y. C. Hwang. In oduc ion o Random Signals and Applied
Kalman Fil e ing. John Wiley & Sons, 2012.
[11] Michael Elad. Spa se and Redundan Rep esen a ions: F om Theo y o Applica ions in
Signal and Image P ocessing. 2010.
[12] G. Da is, S. Malla , and M. A ellaneda. Adap i e g eedy app oxima ions. Cons uc i e
App oxima ion, 13(1):57–98, Ma ch 1997.
[13] S.G. Malla . Ma ching pu sui s wi h ime- equency dic iona ies. IEEE T ansac ions on
Signal P ocessing, 41(12):3397–3415, 1993.
[14] Y.C. Pa i, R. Rezaii a , and P.S. K ishnap asad. O hogonal ma ching pu sui : ecu si e
unc ion app oxima ion wi h applica ions o wa ele decomposi ion. In P oceedings o 27 h
Asiloma Con e ence on Signals, Sys ems and Compu e s, pages 40–44. IEEE Compu . Soc.
P ess, 1993.
79

80 REFERENCES
[15] Sco Shaobing Chen, Da id L. Donoho, and Michael A. Saunde s. A omic Decomposi ion
by Basis Pu sui . SIAM Jou nal on Scien i ic Compu ing, 20(1):33–61, Janua y 1998.
[16] K Pea son. On lines and planes o closes i o sys ems o poin s in space. Philosophical
Magazine, 2(6):559 – 572, 1901.
[17] H. Ho elling. Analysis o a complex o s a is ical a iables in o p incipal componen s. Jou -
nal o Educa ional Psychology, 24(6):417–441, 1933.
[18] M. Aha on, M. Elad, and A. B ucks ein. K-SVD: An Algo i hm o Designing O e com-
ple e Dic iona ies o Spa se Rep esen a ion. IEEE T ansac ions on Signal P ocessing,
54(11):4311–4322, No embe 2006.
[19] Da id L. Donoho and Iain M. Johns one. Minimax es ima ion ia wa ele sh inkage. The
Annals o S a is ics, 26(3):879–921, June 1998.
[20] Da id L. Donoho and Iain M. Johns one. Ideal spa ial adap a ion by wa ele sh inkage.
Biome ika, 81(3):425–455, Sep embe 1994.
[21] Da id L. Donoho and Iain M. Johns one. Adap ing o Unknown Smoo hness ia Wa ele
Sh inkage. Jou nal o he Ame ican S a is ical Associa ion, 90(432):1200–1224, Feb ua y
1995.
[22] D.L. Donoho. De-noising by so - h esholding. IEEE T ansac ions on In o ma ion Theo y,
41(3):613–627, May 1995.
[23] A Cha nbolle, R A DeVo e, N Y Lee, and B J Lucie . Nonlinea wa ele image p ocessing:
a ia ional p oblems, comp ession, and noise emo al h ough wa ele sh inkage. IEEE
ansac ions on image p ocessing : a publica ion o he IEEE Signal P ocessing Socie y,
7(3):319–35, Janua y 1998.
[24] P. Moulin. Analysis o mul i esolu ion image denoising schemes using gene alized-Gaussian
p io s. In P oceedings o he IEEE-SP In e na ional Symposium on Time-F equency and
Time-Scale Analysis (Ca . No.98TH8380), pages 633–636. IEEE, 1998.
[25] D. L. Donoho and R. R. Coi man. T ansla ion in a ian denoising. In Wa ele s and S a is ics,
pages 125–150. Sp inge -Ve lag New Yo k, New Yo k, NY, 1995.
[26] Da id L. Donoho. Wedgele s: nea ly minimax es ima ion o edges. The Annals o S a is ics,
27(3):859–897, June 1999.
[27] Minh Do and Ma in Ve e li. Con ou le s. In Beyond Wa ele s, pages 1–27. Academic P ess,
New Yo k, NY, 2001.
[28] Emmanuel J Candès and Da id L Donoho. New igh ames o cu ele s and op imal ep e-
sen a ions o objec s wi h piecewise C2 singula i ies. Communica ions on Pu e and Applied
Ma hema ics, 57(2):219–266, 2004.
[29] E. Le Pennec and S. Malla . Spa se geome ic image ep esen a ions wi h bandele s. IEEE
T ansac ions on Image P ocessing, 14(4):423–438, Ap il 2005.
[30] W.T. F eeman and E.H. Adelson. The design and use o s ee able il e s. IEEE T ansac ions
on Pa e n Analysis and Machine In elligence, 13(9):891–906, 1991.
REFERENCES 81
[31] Qian Chen and Dapeng Wu. Image denoising by bounded block ma ching and 3D il e ing.
Signal P ocessing, 90(9):2778–2783, Sep embe 2010.
[32] K Dabo , A Foi, V Ka ko nik, and K Egiaza ian. A nonlocal and shape-adap i e ans o m-
domain collabo a i e il e ing. . . . In . Wo kshop on Local and Non . . . , 2008.
[33] K Dabo , A Foi, V Ka ko nik, and K Egiaza ian. BM3D image denoising wi h shape-
adap i e p incipal componen analysis. SPARS’09-Signal P ocessing . . . , 2009.
[34] Michael Elad and Michal Aha on. Image Denoising Via Spa se and Redundan Rep esen-
a ions O e Lea ned Dic iona ies. IEEE T ansac ions on Image P ocessing, 15(12):3736–
3745, Decembe 2006.
[35] Weisheng Dong, Lei Zhang, and Guangming Shi. Cen alized spa se ep esen a ion o im-
age es o a ion. In 2011 In e na ional Con e ence on Compu e Vision, pages 1259–1266.
IEEE, No embe 2011.
[36] Weisheng Dong, Lei Zhang, Guangming Shi, and Xin Li. Nonlocally cen alized spa se
ep esen a ion o image es o a ion. IEEE ansac ions on image p ocessing : a publica ion
o he IEEE Signal P ocessing Socie y, 22(4):1620–30, Ap il 2013.
[37] Hua Zhong, Ke Ma, and Yang Zhou. Modi ied BM3D algo i hm o image denoising using
nonlocal cen aliza ion p io . Signal P ocessing, 106:342–347, Janua y 2015.
[38] S.O. Memik, K. Baza gan, and M. Sa a zadeh. Image analysis and pa i ioning o FPGA
implemen a ion o image es o a ion. In 2000 IEEE Wo kshop on SiGNAL PROCESSING
SYSTEMS. SiPS 2000. Design and Implemen a ion (Ca . No.00TH8528), pages 346–355.
IEEE, 2000.
[39] S.O. Memik, A.K. Ka saggelos, and M. Sa a zadeh. Analysis and FPGA implemen a ion o
image es o a ion unde esou ce cons ain s. IEEE T ansac ions on Compu e s, 52(3):390–
399, Ma ch 2003.
[40] G. Saldana and M. A ias-Es ada. FPGA-Based Cus omizable Sys olic A chi ec u e o Im-
age P ocessing Applica ions. In 2005 In e na ional Con e ence on Recon igu able Compu -
ing and FPGAs (ReConFig’05), pages 3–3. IEEE, 2005.
[41] Jona han Joshi, Nisseem Naba , and Pa ul Ba a. Recon igu able Implemen a ion o Wa ele
based Image Denoising. In 2006 49 h IEEE In e na ional Midwes Symposium on Ci cui s
and Sys ems, olume 1, pages 475–478. IEEE, Augus 2006.
[42] P. B ylski and M. S zelecki. FPGA implemen a ion o pa allel digi al image p ocesso . In
Signal P ocessing Algo i hms, A chi ec u es, A angemen s, and Applica ions Con e ence
P oceedings (SPA), 2010, pages 25–28, 2010.
[43] S e ano Di Ca lo, Paolo P ine o, Daniele Rol o, and Pascal T o a. AIDI: An adap i e image
denoising FPGA-based IP-co e o eal- ime applica ions. In 2013 NASA/ESA Con e ence
on Adap i e Ha dwa e and Sys ems (AHS-2013), pages 99–106. IEEE, June 2013.
[44] Anna Gabige -Rose, Ma hias Kube, Robe Weigel, and Richa d Rose. An FPGA-Based
Fully Synch onized Design o a Bila e al Fil e o Real-Time Image Denoising. IEEE T ans-
ac ions on Indus ial Elec onics, 61(8):4093–4104, Augus 2014.
82 REFERENCES
[45] Pe e J. Rousseeuw and Ch is ophe C oux. Al e na i es o he Median Absolu e De ia ion.
Jou nal o he Ame ican S a is ical Associa ion, 88(424), Feb ua y 1993.
[46] Hanaa Hussain, Khaled Benk id, Chuan Hong, and Huseyin Seke . An adap i e FPGA im-
plemen a ion o mul i-co e K-nea es neighbou ensemble classi ie using dynamic pa ial
econ igu a ion. In 22nd In e na ional Con e ence on Field P og ammable Logic and Appli-
ca ions (FPL), pages 627–630. IEEE, Augus 2012.
[47] C. Loe le , A. Lig enbe g, and G.S. Moschy z. P ac ical as 1-D DCT algo i hms wi h 11
mul iplica ions. In In e na ional Con e ence on Acous ics, Speech, and Signal P ocessing,,
pages 988–991. IEEE, 1989.
[48] Zhang-jin Chen and Zhi-gao Zhang. A High-Speed 2-D IDCT P ocesso o Image/Video
Decoding. In 2009 2nd In e na ional Cong ess on Image and Signal P ocessing, pages 1–4.
IEEE, Oc obe 2009.
[49] M. El Aaki , S. Belkouch, and M. M. Hassani. An e icien pipelined as and mul iplie -
less 2-D IDCT o image/ ideo decoding. In 2011 In e na ional Con e ence on Mul imedia
Compu ing and Sys ems, pages 1–5. IEEE, Ap il 2011.
[50] IEEE S anda d Speci ica ions o he Implemen a ions o 8X8 In e se Disc e e Cosine T ans-
o m, 1991.
[51] A. Aggoun and I. Jalloh. Two-dimensional DCT/IDCT a chi ec u e. IEE P oceedings -
Compu e s and Digi al Techniques, 150(1):2, 2003.