0-7695-1290-9/01 $10.00  2001 IEEE 34
DRAFT: An On-Line Faul De ec ion Me hod o Dynamic and Pa ially
Recon igu able FPGAs
Manuel G. Ge ico a, Gus a o R. Al es
Depa men o Elec ical Enginee ing
ISEP
{mgg, gal es}@dee.isep.ipp.p
Miguel L. Sil a, José M. Fe ei a
Dep. o Compu e s and Elec ical Enginee ing
FEUP
{mlms, jm }@ e.up.p
Abs ac
Recon igu able sys ems ha e bene i ed o he no el
pa ial dynamic econ igu a ion ea u es o ecen FPGA
de ices. Enabling he concu en econ igu a ion wi hou
dis u bing sys em ope a ion, his echnology has aised a
new es challenge: o assu e a con inuously aul ee
ope a ion, independen ly o he ci cui p esen a e many
econ igu a ion p ocesses, es ing he FPGA wi hou
dis u bing he whole sys em ope a ion.
Re-using he IEEE 1149.1 in as uc u e, al eady
widely used o In-Sys em P og amming, and exploi ing
he same dynamic and pa ially econ igu able ea u es
unde lying his es challenge, his pape de elops a new
s uc u al concu en es app oach able o de ec aul s
and in oduce aul ole ance ea u es, wi hou dis u bing
sys em ope a ion, in he ield and h oughou i s li e ime.
1. In oduc ion♦
♦♦
♦
The ad an ages o he use o Field P og ammable Ga e
A ays (FPGAs) we e conside ably ein o ced wi h he
new dynamic and pa ially econ igu able SRAM-based
FPGAs (e. g. Xilinx’s Vi ex amily), capable o
implemen ing as un- ime pa ial econ igu a ion,
enabling he dynamic cus omiza ion o ha dwa e unc ions
concu en ly wi h sys em ope a ion.
Un o una ely, cu en echnology ends o make
FPGAs less eliable, because smalle submic on scales
inc ease he h ea o elec omig a ion, due o highe
elec onic cu en densi y in me al aces. La ge FPGA
dies is ano he ac o ha inc eases he p obabili y o
ailu e [1]. Ce ain de ec s ela ed o manu ac u ing
♦ This wo k is suppo ed by he Po uguese Founda ion o
Science and Technology (FCT), unde con ac
POCTI/33842/ESE/2000
impe ec ions a e no la ge enough o in luence ini ial
es ing, bu hey become exposed a e la ge pe iods o
ope a ion, eme ging as ei he s uck-a aul s o ansien
aul s [2].
A highe eliabili y le el can he e o e only be
achie ed h ough he con inuous es o all FPGA blocks
and he in oduc ion o aul ole ance ea u es. In his
pape we p opose a s uc u al concu en es me hod, he
DRAFT me hod (Dynamically Ro a e And F ee o Tes ),
which uses he dynamic and pa ially econ igu able
ea u es in oduced by hese de ices, and he IEEE 1149.1
Bounda y Scan Tes (BST) in as uc u e [3] o FPGA
econ igu a ion, ec o es applica ion and esponse
cap u ing, hus p esen ing a e y low es o e head a chip
and boa d le el.
2. The DRAFT me hod
In he as majo i y o applica ions, only a pa o he
en i e FPGA esou ces is used o implemen a gi en
unc ional speci ica ion ( he desi ed unc ionali y). E en
when independen ha dwa e blocks dynamically sha e he
same FPGA de ice (in he case o a dynamically
econ igu able ha dwa e sys em), 100% usage o i s
esou ces is ha dly e e achie ed, so a ew blocks will
always be ee. The e o e, i is possible o conside a
s a egy o es empo a ily unused blocks, wi hou
dis u bing sys em ope a ion, aking ad an age o he
dynamic and pa ially econ igu able ea u es o e ed by
new FPGAs.
Using a dynamic o a ion mechanism, each
Con igu able Logic Block (CLB) cu en ly being used by
a gi en applica ion can ha e hei unc ionali y eplica ed
in one o he CLBs al eady es ed. Bo h CLBs mus
emain ac i e wi h he same s a e, inpu s, ou pu s, and
unc ionali y, o a leas one clock cycle, in o de o a oid
ou pu gli ches.
I he cu en CLB unc ion is pu ely combina ional, a
simple ead-modi y-w i e con igu a ion p ocedu e is
35
su icien o accomplish he eplica ion p ocess. Howe e ,
and in he case o a CLB implemen ing a sequen ial
unc ion, he in e nal s a e in o ma ion has o be p ese ed
du ing he eplica ion p ocess. In FPGA de ices
belonging o he Vi ex FPGA amily, i is possible o ead
he alue o a egis e , bu no o pe o m a di ec w i e
ope a ion. The e o e, a empo a y ans e pa h should be
es ablished be ween he egis e s in he wo CLBs, o
allow s a e in o ma ion o be copied be ween hem, and a
leas one clock pulse applied o bo h, as desc ibed in [4].
This solu ion gua an ees ha he whole FPGA can be
es ed, wi hou dis u bing he sys em ope a ion, p o ided
ha a leas one unused CLB is a ailable in he cu en
implemen a ion.
3. The dynamic o a ion p ocess
The o a ion mecanism used in o de o ee CLBs o
es should ha e a minimum in luence in he sys em
ope a ion, as well as a educed o e head in e ms o
econ igu a ion cos . This cos depends on he numbe o
econ igu a ion ames needed o eplica e and ee each
CLB, since a g ea numbe o ames would imply a
longe es ime. The impac o his p ocess in he o e all
sys em ope a ion is mainly due o a ia ions on ci cui
iming, because o he changes in ou ing. Thus, i he e-
ou ing p ocedu e o igina es a pa h delay highe han he
p e ious maximum, he maximum equency o ope a ion
is educed, leading o an undesi able impac in he sys em
ope a ion.
Th ee possibili ies we e conside ed o es ablishing a
ule o he o a ion o he ee CLB, among he en i e
CLB a ay: andom, ho izon al and e ical o a ion.
The andom s a egy was ejec ed o se e al easons.
I he placemen algo i hm (in an a emp o educe pa h
delays) concen a ed in he same a ea he logic needed o
implemen he componen s o a gi en applica ion, i
would be unwise o dispe se he blocks: i s ly, i would
gene a e longe pa hs (and hence, an inc ease in pa h
delays); secondly, i would pu oo much s ess in he
limi ed ou ing esou ces. Fu he mo e, a andom o a ion
s a egy would imply an unp edic able de ec co e age
la ency, which is no accep able.
The second s a egy, ho izon al o a ion, is illus a ed
in igu e 2-a. The ee CLB would o a e along an
ho izon al pa h ha would co e all he CLBs in he a ay.
The eplica ion p ocess would ake place be ween
neighbou ing CLBs, due o sca ci y o ou ing esou ces
and o p e en highe pa h delays. The same ule applies
o he e ical o a ion s a egy illus a ed in igu e 2-b,
whe e he ee CLB is o a ed along a e ical pa h.
Simula ions pe o med wi h he las wo s a egies
using Xilinx’s Vi ex FPGAs, wi h esul s p esen ed in
[5], ha e shown ha he e ical o a ion s a egy achie es
lowe cos s. The size o he econ igu a ion iles ob ained
by he applica ion o bo h s a egies o he same ci cui
implemen a ion was ela i ely close (app oxima ely 20%
highe when using he ho izon al s a egy), bu he
in luence o each one in he maximum equency o
ope a ion was subs an ially di e en , mainly due o a pai
o dedica ed pa hs pe CLB ha p opaga e ca y signals
e ically o adjacen CLBs. When he o a ion p ocess
b eaks a dedica ed ca y pa h, due o he inse ion o he
ee CLB, he p opaga ion o his ca y signal be ween he
nea es adjacen CLBs (abo e and below) is e-es ablished
h ough gene ic ou ing esou ces, inc easing he pa h
delay. When long coun e s o shi egis e s a e
implemen ed, he ho izon al o a ion would b eak all he
ca y ne s, inc easing pa h delays, while he e ical
o a ion would b eak only hose in he op o bo om o he
CLB columns. Conside ing bo h cos s, he educ ion on
he maximum equency and he size o he
econ igu a ion iles, he e ical s a egy is p e e able o
he ho izon al one.
CLB CLB CLB CLB
CLBCLBCLBCLB
CLB
CLBCLB CLB
CLBCLB
CLB
CLB
CLB CLB CLB CLB
CLBCLBCLBCLB
CLB
CLBCLB CLB
CLBCLB
CLB
CLB
a) Ho izon al s a egy b) Ve ical s a egy
Figu e 2. Dynamic o a ion o he ee CLB
This back and o h dynamic ee-CLB o a ion ac oss
he chip implies a a iable es la ency. The ime o again
each a gi en CLB al e na es be ween a maximum and a
minimum alue (acco ding o he o a ion di ec ion),
depending on he size o he de ice.
The maximum aul de ec ion la ency is gi en by
)(2)2)#((# es econ columns owsscan CLBCLB
MAX
+××−×=
τ
The minimum aul de ec ion la ency is in u n gi en by
)(2 es econ scan
min
+×=
τ
whe e:
econ : ime needed o comple e a CLB eplica ion
es : ime needed o es a ee CLB
A e a comple e o a ion, he ini ial ou ing is es o ed.
4. The es session
Each Vi ex CLB comp ises wo exac ly equal slices.
One o hem, ep esen ing he es model, is shown in
igu e 3. In o al, he CLB es model has 13 inpu s ( es
36
ec o s a e applied o bo h slices o each CLB
simul aneously) and 12 ou pu s (6 om each slice).
G
LUT
F
LUT
Y
X
Figu e 3. Tes model o one Vi ex slice s uc u e
The BST in as uc u e is used o apply es ec o s
and o cap u e es esponses, wi h he ou pu s o he CLB
unde es being ou ed o unused BST egis e cells (BST
egis e cells associa ed o ou pu o i-s a e lines in IOBs
con igu ed as inpu s, o BST egis e cells associa ed o
inpu s lines in IOBs con igu ed as i-s a e ou pu s). I is
no possible o apply he es ec o s h ough he BST
egis e wi hou a ec ing he alues p esen a each FPGA
inpu , so an al e na i e Use Tes Regis e mus be used
( he Vi ex amily enables he de ini ion o wo use
egis e s con olled h ough he BST in as uc u e). This
Use Tes Regis e comp ises 13 cells, co esponding o
he equi ed numbe o CLB es con igu a ion inpu s. The
se en CLBs occupied by his egis e and he CLB needed
o pe o m he o a ion make up o he 0,7% es
o e head, calcula ed o he CLB esou ces o a medium
size XCV200 Vi ex de ice. Figu e 4 illus a es he
implemen a ion o ou es p ocedu e.
ou pu s
Use Tes Regis e
Bypass egis e
Ins uc ion egis e
Con igu a ion egis e
inpu s
TDO
TDI
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOBIOBIOBIOBIOBIOB
. . . . . . . . .
...
...
CLB
unde
es
Figu e 4. Tes o a CLB
Tes ec o shi ing h ough he Use Tes Regis e is
e y as , in iew o is educed leng h. Shi ing he
esponse es ec o depends on he leng h o he BST
egis e (de ice size). Since his use egis e is pa o he
CLB a ay, he CLBs whe e i is implemen ed a e also
es ed h ough he same p ocess. This means ha all he
ha dwa e esou ces used o implemen he es p ocedu e
a e sel - es ed.
As he esul o ou analysis o he Vi ex CLB es
model s uc u e, we concluded ha ou es phases a e
enough o exe cise all possible con igu a ions in he CLB.
As we did no know he implemen a ion s uc u e o he
CLBs mul iplexe s and lip- lops, we conside ed a hyb id
aul model [6]. Table 1 summa ises ou expe imen al
esul s.
Table 1. Expe imen al es esul s
Tes session
1s es phase 18 es applica ions
2nd es phase 3 es applica ions
3 d es phase 2 es applica ions
4 h es phase 16 es applica ions
This p ocedu e accoun s o 100% aul co e age
unde he conside ed aul model.
5. Conclusion
The solu ion p oposed in his pape enables he
implemen a ion o a concu en es me hod ha euses he
s anda d BST in as uc u e and he no el pa ial dynamic
econ igu a ion ea u es o ecen FPGA de ices, in o de
o imp o e he eliabili y o econ igu able ha dwa e
sys ems, wi h minimal es o e head and in a way ha is
comple ely anspa en o he sys em ope a ion.
Ou cu en wo k ocuses on he ex ension o he
p oposed me hodology o o he FPGA esou ces and on
he de elopmen o compu a ional ools o in oduce a
highe deg ee o au oma ion in he whole p ocess.
6. Re e ences
[1] Lach, J., Mangione-Smi h, W. H., Po konjak, M., “Low
O e head Faul -Tole an FPGA Sys ems”, IEEE T ans. on VLSI
Sys ems, Vol. 6, Nº 2, pp. 212-221, June 1998.
[2] Shnidman, N. R., Mangione-Smi h, H., Po konjak, M., “On-
Line Faul De ec ion o Bus-Based Field P og ammable Ga e
A ays”, IEEE T ans. on VLSI Sys ems, Vol. 6, Nº 4, pp. 656-
666, Decembe 1998.
[3] IEEE S anda d Tes Access Po and Bounda y Scan
A chi ec u e (IEEE S d 1149.1), IEEE S anda ds Boa d,
Oc obe 1993.
[4] Ab amo ici, M., S oud, M., Wijesu iya, S., Hamil on, C.,
Ve ma, V., “On-Line Tes ing and Diagnosis o FPGAs wi h
Ro ing STARs”, P oc. o he 5 h IEEE In e na ional On-Line
Tes ing Wo kshop, pp. 2-7, July 1999.
[5] Ge ico a, M. G., Al es, G. R., Fe ei a, J. M., “Dynamically
Ro a e And F ee o Tes : The Pa h o FPGA Concu en Tes ”,
2nd IEEE La in-Ame ican Tes Wo kshop Diges o Pape s,
pp. 180-185, Feb. 2001.
[6] Huang, W. K., Meye , F. J., Chen, X., Lomba di, F.,
“Tes ing Con igu able LUT-Based FPGA's”, IEEE T ans. on
VLSI Sys ems, Vol. 6, Nº 2, pp. 276-283, June 1998.