An Au oma ed Ve i ica ion P ocess Based on Scan Techniques
Gus a o R. Al es
DEE / ISEP
Rua S. Tome
4200 Po o – Po ugal
[email p o ec ed]
Ma celo S. Lubaszewski Ma g i Reni K ug
PPGC / UFRGS
A . Ben o Gonçal es, 9500
CEP 91501-970 Po o Aleg e – B asil
[email protected] gs.b ma g i @in .u gs.b
José M. Ma ins Fe ei a
DEEC / FEUP
Rua dos B agas
4000 Po o – Po ugal
jm @ e.up.p
Abs ac
Ma ching he esul s achie ed du ing ci cui simula ion wi h
hose ex ac ed om ci cui unc ioning is a common
e i ica ion p ocess. A la ge numbe o cu en e i ica ion
echniques use he inpu / ou pu ec o s p oduced du ing
unc ional simula ion as he es ec o s applied / compa ed
agains he ci cui esponses. Techniques ha a e mo e
comple e include ex ac ing he alues o in e nal sequen ial
nodes and compa ing hese using in e nal scans. This pape
desc ibes a solu ion o e i ying digi al designs
implemen ed in cu en ly comme cial a ailable CPLDs. All
in e nal lip- lops a e included in a scan-chain accessible
h ough he BST in as uc u e (using a use -de ined
op ional ins uc ion), while he BS cells a e used o apply he
inpu es ec o s and cap u e he ci cui esponses. These
BS cells can ei he belong o he de ice-unde - es o o
o he de ices, he i s con olled h ough he op ional
INTEST ins uc ion and he second con olled h ough he
manda o y EXTEST ins uc ion. To speed up he
e i ica ion p ocess, he es p og am is au oma ically
gene a ed om in o ma ion ha encompasses he design &
de elopmen phase.
1. In oduc ion
Compa ing he esul s ob ained om he simula ion phase
wi h hose ex ac ed om eal ci cui beha iou is a
adi ional me hod o ci cui e i ica ion, some imes
e e ed as unc ional es . While his me hod can be
ex ended o compa ing he alues o in e nal lip- lops
(FFs) [1, 2], he need o expensi e es equipmen
p e en s such an app oach o small esea ch g oups wi h
limi ed budge s. The p esence o a Bounda y Scan Tes
(BST) in as uc u e in cu en comme cial a ailable
Complex P og ammable Logic De ices (CPLDs) is a
possible solu ion o implemen ing a simila app oach
using wo op ional ins uc ions desc ibed in he s anda d
[3] and a chip-le el con olle p e iously de eloped o
debugging & es ing boa d-le el applica ions [4, 5, 6, 7].
The INTEST ins uc ion allows he applica ion o a es
ec o o inpu pins and he cap u e o a esponse ec o s
in ou pu pins, while a simple use -de ined op ional
ins uc ion called ‘INTSCAN’ allows cap u ing he alues
p esen in in e nal sequen ial nodes. The es con olle
named PROcesso o DEbug Pu poses (PRODEP) is
esponsible o con olling all es ope a ions, namely o
shi ing in / ou he es ec o s h ough he CPLD Tes
Access Po (TAP). The es p og am execu ed by
PRODEP is au oma ically gene a ed om in o ma ion
ha encompasses he design & de elopmen phase. Key
poin s o ou solu ion include: a low-cos app oach
dispensing he use o complex es equipmen , e-use o
simula ion esul s, e-use o a boa d-le el BS con olle ,
and use o in-house so wa e ela i ely simple o de elop
( he au oma ic es p og am gene a ion ool). Addi ional
con ibu ions include he iden i ica ion o laws in he
op ional INTEST ins uc ion (de ined in he IEEE 1149.1
s anda d), and in he BSDL ile, in wha e e s o access
o in e nal scan chains, h ough he BST in as uc u e.
This pape is o ganised as ollows: a e his in oduc ion,
sec ion 2 desc ibes he es p og am gene a ion p ocess,
namely he da a low, and he inpu / ou pu in o ma ion.
Some de ails o he in e nal da a s uc u e a e p o ided o
highligh ha mos o his p ocess is ac ually de o ed o
o de ing in o ma ion ex ac ed om exis ing iles. The
conside a ions on he INTEST ins uc ion and on he
BSDL ile a e included in his sec ion. Sec ion 3 desc ibes
how PRODEP is connec ed o he ci cui unde
e i ica ion and how he es p og am is execu ed. Sec ion
4 is de o ed o he e o 1 de ec ion / loca ion / diagnosis
p ocess. Finally, sec ion 5 concludes his pape .
2. Tes p og am gene a ion
The da a low in he es p og am gene a ion p ocess is
illus a ed in igu e 1 ha also se es as a basis o he
ollowing desc ip ion. Mos o he inpu in o ma ion
equi ed by he au oma ic es p og am gene a ion
(ATPG) ool is p o ided om ea lie s ages o he design
& de elopmen p ocess. The ool equi es i e inpu s:
1 An e o is unde s ood he e as a misma ch be ween a cap u ed
alue and an expec ed alue in ei he a pin o an in e nal FF.
• a ile con aining he simula ion esul s (bo h he inpu
s imulus and he ci cui alues o bo h he ou pu pins
and he in e nal FFs);
• he de ice’s BSDL ile (p o ided by he CPLD
manu ac u e o which may be au oma ically
gene a ed using comme cially a ailable so wa e);
• a ile desc ibing he in e nal scan chain o de ing;
• a ile con aining he use op ions;
• he s uc u al es ec o s (op ional).
The i s ile, p o ided by he simula ion ool, con ains a
comple e desc ip ion o all he simula ion channels used,
i.e. he inpu / ou pu / bi-di ec ional pins and he in e nal
lip- lops (which may be all o jus a ac ion o he o al
numbe o lip- lops exis ing in he ci cui ). In e p e ing
his ile is some imes a majo p oblem, as cu en ly he e
isn’ a widely used public o de ac o s anda d o he
o ma o he simula ion esul s ile. The one gene a ed by
he MaxPlusII de elopmen sys em2 comes in a abula
o m, in ASCII, whe e columns co espond o ci cui
signals (inpu s / ou pu s / in e nal nodes) and ows
co espond o ime momen s. The cell co esponding o a
ow ( ime) – column (signal) in e sec ion con ains he
signal alue o a pa icula ci cui loca ion in a pa icula
momen . Simula ion iles in his o ma (wi h mino
a ia ions) a e qui e common o ind, and in ac , hey
ep esen a kind o iles ha a e easie o p ocess in o de
o ex ac he needed in o ma ion. In ou case, we
de eloped a simple C p og am ha pe o ms his
ope a ion, p o iding he in o ma ion needed o he ATPG
ool in a p e-de ined o ma , la e p esen ed in his pape .
The BSDL ile maps he de ice’s inpu / ou pu / bi-
di ec ional pins o he co esponding BS cells. Ou
app oach includes wo op ions: he ec o s may ei he be
applied / cap u ed h ough he BS cells o de ice, using
he op ional INTEST ins uc ion, o h ough he BS cells
o o he de ices, using he EXTEST ins uc ion. The i s
op ion has some d awbacks:
• i elies on a op ional ins uc ion ha some imes is
no suppo ed by comme cial a ailable CPLDs;
• he s anda d de ines se e al ways in which single-
s ep ope a ion may be achie ed. This p esen s some
p oblems o he ATPG ool, namely because he e
isn’ a well-documen ed o m o indica ing which
op ion is ac ually implemen ed in a ce ain de ice.
• INTEST places he BS cells associa ed wi h he
de ice inpu pins in he con ol mode and hose
associa ed wi h he de ice ou pu pins in he cap u e
mode. While his is wha is in ended, when he
op ional ins uc ion used o accessing he in e nal
scan chain is loaded in he ins uc ion egis e , he BS
cells will be placed in he anspa en mode, hus
dis up ing he pe manen applica ion o a s able inpu
es ec o . I no p ope ly conside ed, his swi ch
may cause po en ial haza ds o he ci cui -unde - es .
2 De elopmen sys em used o A e a’s CPLDs [8].
Figu e 1: Da a low o he ATPG p ocess
The second op ion equi es addi ional componen s solely
used o p o iding he necessa y BS cells ac ing as es
channels. The BSDL ile con ains also he opcodes o he
SAMPLE/PRELOAD, INTEST and ‘INTSCAN’
ins uc ions. Cu en ly he e is a se ious omission in he
con en s o his ile, namely he s anda d does no de ine a
way o p esen ing he o de ing o an in e nal scan chain
accessible h ough he BST in as uc u e. A di e en ile
gene a ed by ano he in-house ool p o ides his
in o ma ion. The use con igu a ion ile con ains
addi ional in o ma ion o he way he es p og am will
be execu ed, namely some op ions closely associa ed wi h
he esou ces a ailable in ou boa d-le el BS con olle .
The las ile is supposed o be p o ided in Se ial Vec o
Fo ma (SVF), o enable a s uc u al es o he ci cui
implemen ed in he CPLD. The SVF p og am is ac ually
ansla ed o ou o ma and embedded in he inal es
p og am. The possibili y o un a s uc u al es plus a
unc ional es hus expands he diagnosis capabili ies.
The ATPG ool p ocesses he inpu in o ma ion and
p oduces wo ou pu iles co esponding o he p og ams
o be execu ed by each one o he wo con olle s ha a e
embedded in PRODEP. One con olle (CLT) is able o
con ol wo BS chains and he o he (CLF) is able o
con ol one sys em clock and se e al gene al-pu pose
inpu / ou pu pins The ope a ions o bo h con olle s a e
synch onised a machine le el ( h ough a common inpu
clock) and a p og am le el ( h ough dedica ed
ins uc ions). Figu es 2 and 3 p o ide an idea on how he
in e nal da a s uc u e is i s o med, a e eading he
se e al inpu iles, while igu e 4 p o ides an exce p o
he es ec o s o be applied / compa ed h ough shi
ope a ions. These ec o s a e ex ac ed om he ile wi h
he simula ion esul s, whe e he indi idual alues (bi s)
a e placed in he igh o de using he in o ma ion
p o ided by he in e nal da a s uc u e. No ice ha he
simula ion channels and he BS cells (o he in e nal FFs)
do no necessa ily sha e he same o de .
Nodes
________________ ________________
id: clock1 id: s obe
ype: inpu ype: ou pu
bounda y_cell: 37, BC_4 bounda y_cell: 22, BC_1
________________ ________________
id: sel_d3 id: shu down
ype: inpu ype: ou pu
bounda y_cell: 36, BC_4 bounda y_cell: 21, BC_1
... ...
Figu e 2: Ex ac o he in e nal da a s uc u e a e eading he BSDL ile
Nodes
________________ ________________ ________________
id: clock1 id: s obe id:co e coun 1 cn _bi s1
ype: inpu ype: ou pu ype: bu ied
bounda y_cell: 37, BC_4 bounda y_cell: 22, BC_1 in e nal_cell: 24
ex e nal_cell: 28 ex e nal_cell: 9
________________ ________________ ________________
id: sel_d3 id: shu down id:co e coun 1 cn _bi s2
ype: inpu ype: ou pu ype: bu ied
bounda y_cell: 36, BC_4 bounda y_cell: 21, BC_1 in e nal_cell: 25
ex e nal_cell: 26 ex e nal_cell: 8
... ... ...
Figu e 3: Exce p o he in e nal da a s uc u e a e eading he ile desc ibing in e nal scan chain and he ile
con aining he use op ions
BS egis e .
ec o o be shi ed in:
10010000101000011000000001111110111111
expec ed ec o :
00000000000000011000000001111110111111
mask:
00000000000000011111111111111111111111
in e nal scan egis e .
expec ed ec o :
00000000000000000000000000
mask:
11111111000000000000011110
Figu e 4: Ope ands o he shi ins uc ions a e eading
he ows o he ile con aining he simula ion
esul s and combining he in o ma ion p o ided
by he in e nal da a s uc u e
The s epwise applica ion / cap u ing o each es ec o is
now desc ibed in he ollowing sec ion.
3. The es p og am execu ion
Two iles o m he es p og am, each one co esponding
o he ins uc ions and ope ands in e p e ed by each one
o he wo con olle s embedded in PRODEP. The
in e nal s uc u e o his de ice was al eady desc ibed in
p e ious pape s [4, 5], he e o e we will concen a e on
he es p og am execu ion. The basic p ocedu e in ou
e i ica ion p ocess consis s o :
• apply one inpu ec o used du ing simula ion;
• cause he de ice o ad ance one s ep in i s ope a ion;
• cap u e / shi / compa e he alues p esen a he
ou pu pins, and shi / compa e he alues p esen a
he in e nal FFs.
The i s ac ion consis s o mo ing he de ice’s TAP
con olle o he Shi -DR s a e, shi in he es ec o and
hen mo ing o Upda e-DR. This ac ion is simila i using
he INTEST ins uc ion plus he de ice BS cells, o he
EXTEST ins uc ion plus he BS cells o o he de ices
used as ex e nal es channels.
The second ac ion may be pe o med in se e al ways,
acco ding o he in o ma ion p o ided in he use op ions
ile. This in o ma ion is closely ela ed o he se e al
examples p o ided in he IEEE 1149.1 s anda d [3], on
how a s ep-by-s ep ope a ion may be implemen ed o
in e nal es ope a ions ( igge ed by he INTEST
ins uc ion). As one o he con olle s embedded in
PRODEP is able o con ol one sys em clock, he use is
u he able o choose be ween an ex e nal o in e nal
clocks sou ce ( his las co esponding o he one
con olled h ough he BST in as uc u e). Figu e 5a) and
5b) illus a e hese wo op ions, espec i ely.
The hi d and las ac ion includes wo dis inc pa s. The
i s co esponds o mo ing he de ice’s TAP con olle o
he Cap u e-DR s a e (whe e he esponse o he es
ec o is cap u ed), mo ing u he o Shi -DR, and hen
shi ou he cap u ed ec o . The second pa co esponds
o loading he op ional ‘INTSCAN’ ins uc ion (mo e
TAP con olle o Shi -IR, shi in he ins uc ion code,
and hen mo e o Upda e-IR, whe e he new ins uc ion
comes e ec i e) and hen pe o ming a ci cula shi , i.e.
he alues shi ed ou o he in e nal scan chain a e also
shi ed in, so ha he scan chain con en s emain he
same. Meanwhile, he shi ed alues a e also compa ed
( h ough a mask) agains he expec ed ones, inside
PRODEP. This way, PRODEP is esponsible o he e o
de ec ion phase.
Figu e 5: Possible ways o p o iding he clock signal o
s ep-by-s ep ope a ion
4. The de ec ion/loca ion/diagnosis p ocess
Any misma ch be ween a cap u ed alue and an expec ed
alue (when he compa ison mask is ac i e) cause
PRODEP o acknowledge e o in a dedica ed ou pu pin.
The es p og am may hen be hal ed h ough condi ional
ins uc ions ha es he in e nal e o lag, o con inued
up o he end. E o loca ion is pe o med by ano he in-
house ool ha ex ac s he ec o s cap u ed by PRODEP
( alues shi ed in o PRODEP a e s o ed in an ex e nal
memo y) and compa es he las wi h he co esponding
expec ed one ( he exac o de is p o ided by he ATPG
ool ha numbe s all expec ed ec o s). The nex s ep
consis s o iden i ying he o ending bi , i.e. which alue
di e s in he cap u ed ec o , in ela ion o he expec ed
one, when he compa ison mask is ac i e. A e he bi
o de is iden i ied, he ool combines he in o ma ion
p o ided by he in e nal da a s uc u e o loca e he
o ending pin o lip- lop. Diagnosis hen ollows wi h an
addi ional simula ion session. By looking in o he ime
slo whe e he e o is de ec ed, namely o he alue o he
o ending pin o lip- lop, he use is able o iden i y
possible e o sou ces. I mo e in o ma ion is needed he
use may un a mo e speci ic simula ion session wi h
co ne cases su ounding he exac e o si ua ion, and
hen gene a e ano he es p og am (using he ATPG ool).
The new alues ex ac ed om he ci cui beha iou may
hen help he use o ind a solu ion o he ac ual e o .
This las p ocess can be epea ed se e al imes un il he
use is ce ain ha he exac e o condi ion has been
unequi ocally iden i ied and ha he en isaged solu ion is
co ec , namely by compa ing he alues ob ained in
simula ion wi h hose ex ac ed om ci cui unc ioning.
5. Conclusions
This pape desc ibes a low-cos ci cui e i ica ion
me hodology. The key poin s a e: e-usabili y o iles ha
encompass he design & de elopmen phase, e-usabili y
o he BST in as uc u e o debug pu poses (besides he
adi ional p oduc ion es ), use o easy- o-de elop in-
house applica ions. This las poin includes wha is
conside ed he ATPG ool. Al hough his ool gene a es
he es p og am execu ed by ou es con olle , i di e s
om adi ional ATPG ools in he ac ha i does no
ollow a pa icula algo i hm o aul model, bu a he
combines in o ma ion p o ided by al eady exis ing inpu
iles. As he simula ion esul s ile p o ides he bulk o
he inpu in o ma ion, i is a guable ha he ecen STIL
[9] (S anda d Tes In e ace Language, o IEEE 1450
s anda d) may be a be e way o es ablish he connec ion
be ween ci cui simula ion and ci cui e i ica ion.
Howe e , he au ho ’s opinion is ha his o ma is be e
sui able o la ge, expensi e es equipmen , no o he low-
cos BST con olle used by us, o possibly used by o he
esea ch g oups wi h limi ed budge s.
6. Re e ences
[1] K. Holdb ook, S. Joshid, S. Mi a, J. Pe olino, R. Ramon
and M. Wong, “mic oSPARCTM: A Case-S udy o Scan
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Con e ence, pp. 70-75, IEEE Compu e Socie y P ess, 1994.
[2] Hong Hao and Rick A a, “S uc e ed Design- o -Debug -
he Supe SPARCTM II Me hodology and Implemen a ion,”
in p oceedings o he In e na ional Tes Con e ence (ITC),
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[3] IEEE S anda d Tes Access Po and Bounda y-Scan
A chi ec u e, Oc . 1993, IEEE S d. 1149.1 (Includes IEEE
S d. 1149.1a), ISBN 1-55937-350-4.
[4] J. M. Fe ei a, M. G. Ge ico a, J. L. Ramalho and Gus a o
R. Al es, "BIST o 1149.1-Compa ible Boa ds: A Low-
Cos and Maximum-Flexibili y Solu ion," in p oceedings o
he In e na ional Tes Con e ence (ITC), pp. 536-543, IEEE
Compu e Socie y P ess, 1993.
[5] Gus a o R. Al es, Telmo Ama al and José M. M. Fe ei a,
“Boa d-le el P o o ype Valida ion: A Buil -in Con olle
and Ex ended BST A chi ec u e,” in p oceedings o he
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IEEE Ci cui s and Sys ems Socie y P ess, 1999.
[6] Gus a o R. Al es and José M. M. Fe ei a, “F om Design-
o -Tes o Design- o -debug-and-Tes : Analysis o
Requi emen s and Limi a ions o 1149.1,” in p oceedings
o he VLSI Tes Symposium (VTS), IEEE Compu e Socie y
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[7] Gus a o R. Al es, “Design o Debug and Tes based on he
P114.4 and 1149.1 a chi ec u es”, PhD Thesis, FEUP, Ap .
1999.
[8] Al e a Co po a ion Web si e, h p://www.al e a.com, 1999.
[9] IEEE S d. 1450-1999, IEEE S anda d Tes In e ace
Language (STIL) o Digi al Tes Vec o Da a, IEEE
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h p://s anda ds.ieee.o g/ca alog/olis/ es ech.h ml, 1999