A Fixed-Frequency Quasi-Sliding Control Algorithm: Application to Power Inverters Design by Means of FPGA Implementation

344 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003 A Fixed-Frequency Quasi-Sliding Control Algorithm: Application to Power Inverters Design by Means of FPGA Implementation Rafael R. Ramos, Student Member, IEEE, Domingo Biel, Member, IEEE, Enric Fossas, and Francesc Guinjoan, Member, IEEE Abstract—In this paper a fixed-frequency quasi-sliding control algorithm based on switching surface zero averaged dynamics (ZAD) is reported. This algorithm is applied to the design of a Buck-based inverter, and implemented in a laboratory prototype by means of a field programmable gate array (FPGA), taking into account processing speed versus computational complexity trade-off. Three control laws, namely sliding control (SC), fixed-frequency quasi-sliding ZAD and PWM-based control have been experimentally tested to highlight the features of the proposed algorithm. According to the experimental results presented in the paper, the ZAD algorithm fulfills the requirement of fixed switching frequency and exhibits similar robustness properties in the presence of perturbations to those of sliding control mode. IndexTerms—Fixed-frequency,FPGA,powerconverters,quasisliding control. I. INTRODUCTION POWER conditioning systems are often designed to supply anacloadfromadcsource.Theuninterruptiblepowersupplies (UPS), photovoltaic systems (PV) connected to the utility grid and ac power sources constitute the most classical applications. The design of such systems must achieve a behavior as close as possible to ideal ac voltage or current sources, in the sense of fast transient response to load variations, steady-state accuracy and low total harmonic distortion (THD). Severalcontrolschemeshavebeensuggestedfordctoacconversion, depending on how the signal error is processed. For instance, in order to preserve the benefits of a fixed-frequency design, many tracking control techniques based on high-frequency pulse width modulation (PWM) have been proposed for Buck-based inverters [1]–[5]. In all of these cases, the control design is based on a power stage model, leading to output waveforms sensitive to power stage parameter variations, such as output load. Considering this sensitivity, several advanced linear control algorithms, for example multiple-loop dead-beat and adaptive controllers, have been suggested to improve the Manuscript received January 30, 2002; revised October 7, 2002. This work was supported by the Ministerio de Ciencia y Tecnología, Spain, under Grant DPI2000-1509-CO3-02,03. Recommended by Associate Editor S. B. Leeb. R. R. Ramos and D. Biel are with the UPC-EUPVG, Vilanova i la Geltrú 08800, Spain (e-mail: [email protected]; [email protected]). E. Fossas is with UPC-ETSEIB, Institut d’Organització i Control de Sistemes Industrials, Barcelona 08028, Spain (e-mail: [email protected]). F. Guinjoan is with UPC-Mòdul C4, Barcelona 08034, Spain (e-mail: guin- [email protected]). Digital Object Identifier 10.1109/TPEL.2002.807164 robustness and the dynamic response of inverter design. Moreover, the corresponding inverter implementation includes a digital programmable platform in the control loop because of the computational complexity involved in such control algorithms. In this sense, several implementations based on microprocessors, DSP and FPGA can be found in the literature [6]–[12], in agreement with switching frequency versus control loop processing time trade-off. Sliding-mode control techniques have also been proposed as an alternative to PWM control strategies in dc–dc switching regulators since they make these systems highly robust to perturbations, namely variations of the input voltage and/or in the load [13]–[17]. For this reason, tracking control schemes based on these techniques have also been applied to the design of high-efficiency Buck-based inverters. In this case, the converter output is forced to track an external sinusoidal reference by means of an appropriate sliding-mode control action [18]–[21]. However, because of the sliding mode control principles, the resulting designs operate at a variable switching frequency, this leading to an undesirable chattering phenomenon and hindering the design of the inverter filter elements. In order to partially overcome these drawbacks, analog implementations of sliding mode control have traditionally been carried out by means of a hysteresis comparator [22]–[24], which provides a variable bounded switching frequency. In addition, and regarding hysteresis comparator based implementations, several authors have suggested alternative designs for combining the robustness properties of sliding mode control with a fixed-switching frequency operation mode. One approach is based on fixing the switching frequency by means of a variable width hysteresis comparator [25]–[27], this leading to a cumbersome analog implementation where hysteresis width depends on the converter parameters. As an alternative, the addition of a fixed-frequency external signal to the switching surface has also been presented in [28]–[30]. Hence, in these works the switching instants do not only depend on the switching surface behavior. At the same time, the increasing performances of digital platforms such as DSP or FPGA allow specific discrete-time sliding controllers as in [31]–[33]. This approach, known as quasi-sliding control, also seeks fixed switching frequency operation by obtaining control algorithms which force a switching surface null value at the end of the desired switching period. Several applications of such algorithms to the inverter design can be found in the works of [34] and [35]. 0885-8993/03$17.00 © 2003 IEEE Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. RAMOS et al.: FIXED-FREQUENCY QUASI-SLIDING CONTROL ALGORITHM 345 Fig. 1. ZAD principle. Alternatively, a fixed-frequency quasi-sliding control algorithm based on switching surface zero averaged dynamics (ZAD) is reported in this paper. This algorithm is applied to the design of a Buck-based inverter, and implemented in a laboratory prototype by means of a field programmable gate array, taking into account the processing speed and computational complexity trade-off. The paper is organized as follows: the ZAD control algorithm is introduced in section two; the main characteristics of a sliding mode controlled power inverter are presented in section three for the subsequent application of the ZAD control algorithm; section four is devoted to the description of the FPGA implementation of the proposed algorithm; for comparative purposes, simulation and experimental results of three control laws, namely sliding control (SC), fixed-frequency quasi-sliding ZAD and PWM-based control, are presented in section five to highlight the features of the proposed algorithm. Finally, the conclusions of this work are pointed out in section six. II. ZERO AVERAGE DYNAMICS CONTROL ALGORITHM This section contains a summary of the ZAD algorithm [36] and deals with a quasi-sliding mode strategy based on the achievement of switching surface zero average dynamics in each cycle in steady-state. Starting from a general, SISO, autonomous, nonlinear system defined by (1) where and and are vector fields defined on ,it is assumed that the system is governed by a switching surface and a sliding control law if if (2) which will be modified into a pulse width modulation as if if (3) where is the switching period and is the duty cycle in the -period. The ZAD control algorithm imposes the control variable to force a switching surface zero average dynamics in steady-state, that is (4) Referring to Fig. 1, where and stand for the instants at the beginning and the end of the period, the control law is obtained under the hypothesis of linear approximation for the switching surface. As a consequence, the switching surface derivatives defined as and are considered constant during the period, and given by (5) The ZAD control algorithm is deduced according to two differentcasesthat canbedistinguishedfrom theswitchingsurface behavior, namely the following. A) If and (condition verified during transient state), the dashed area will always be greater than the dotted one. Since in this case eq. (4) cannot be fulfilled for the period, the control action at , that is , holds throughout the period, forcing the value of to decrease. Thus, no switching action occurs and . B) If and (condition verified in steady-state), the dotted area will always be greater than the dashed one. In this case, condition (4) can be fulfilled during the period if the control action at , , is switched to after a time interval , where (6) A similar reasoning can be applied to . All the cases and the corresponding control actions are summarized in Table I [36]. From these results, it can be concluded that the duty cycle corresponding to the ZAD control algorithm can be determined provided that , and as well as the switching period fixed by the user, are known. III. SLIDING MODE CONTROLLED BUCK INVERTER The previous control algorithm has been applied to the design of a Buck-based high-frequency inverter. This work is focused on the sliding control loop design of a full-bridge Buck Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. 346 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003 TABLE I ZAD CONTROL ALGORITHM inverter, as that depicted in Fig. 2, where the Buck stage behavior can be represented by means of the following piecewise state equations: (7) Thecontrolsignal drivesthepowerswitchstatesandtakesdiscrete values, namely , this resulting in an LC filter input voltage of or . The desired ac regulated output voltage is achieved by designing a sliding control loop based on the following switching surface proposed by Carpita et al. [23] (8) and the control law if if (9) where is the reference signal. As the authors have shown, this design leads to the desired steady sliding motion, that is . Starting from this previous work, the following section is devoted to the implementation of the quasi-sliding ZAD algorithm applied to the switching surface given by (8) for a Buck-based inverter design. IV. FPGA-BASED ZAD CONTROL LOOP IMPLEMENTATION Control loop implementation assumes the design of a Buckbased inverter operating at a fixed switching frequency ranging from 20 to 40 kHz. In addition, the parameters of the Buck power stage are designed to fulfill the linear behavior approximation of the switching surface given in (8) for the desired switching period. As has been previously shown in Table I, the control algorithm must take into account several cases, some of which involve nonlinear arithmetic. Because of the algorithm complexity, a digital implementation appears to be the best solution. Fig. 2. DC/AC Buck power stage. Fig. 3. ZAD quasi-sliding control block diagram. Fig. 4. Analog signal conditioner circuit. Fig. 5. Functional block diagram of the designed FPGA. Several digital platforms can be considered, such as general-purpose microprocessors, digital signal processors (DSP) Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. RAMOS et al.: FIXED-FREQUENCY QUASI-SLIDING CONTROL ALGORITHM 347 and high-density programmable logic devices like field programmable gate arrays (FPGA) or complex programmable logic devices (CPLD). The final selection should take into account several features such as processing speed, device capability, design environment and device cost. As for fixed-frequency PWM waveforms, the main processing speed requirements to preserve the expected closed-loop dynamics are that the digital processor supplies the proper control action at the beginning of the period and that the computing time does not exceed in any case the time interval during which the control value holds before switching. If these two requirements are fulfilled, the control implementation can be considered as cycle-by-cycle control. In the case of the dc/ac power converters considered here, the switching frequency ranges from 20 to 40 kHz, which means that obtaining a minimum duty cycle of 10% will require a control law computing time less than 10% of the switching period, thus ranging from 2.5 sto5 s for the present application. This computing-time requirement rules out the use of general-purpose microprocessors or DSP, which are based on software design. Alternatively, because of its high-speed processing capability and its embedded hardware design, an FPGA has been finally selected for the present case. Fig. 3 shows a block diagram of the XC4010E FPGA-based implementation of the ZAD quasi-sliding control algorithm. This block diagram includes an analog signal conditioner, an analog-to-digital converter (ADC) and an FPGA programmable logic device with its corresponding external clock and EEPROM memory to store the FPGA configuration. Some aspects of the design of these blocks are described in the following paragraphs. A. Analog Signal Conditioner The signal conditioner is in charge of supplying the value of theswitchingsurface givenby(8)totheADC,andisdesigned by means of conventional OpAmp’s-based circuitry, as shown in Fig. 4. The Buck output voltage is sensed by means of an AD215BY wideband isolation amplifier, whereas the capacitor current is acquired with an LA25-NP current sensor. B. AD Converter The switching surface value is sampled and digitized by the ADC at a fixed rate for the subsequent FPGA processing. As far as ADC selection is concerned, the following related parameters must be taken into account. 1) Maximum allowable sampling frequency: the maximum sampling frequency is lower bounded by the effective sampling frequency used in the design, and upper bounded by the ADC cost. 2) Analog-to-digital time conversion. The ADC time conversion is added to the FPGA computing time, thus increasing the overall control-loop processing time. This parameter must be chosen in order to preserve the cycle-by-cycle control concept. 3) Number of bits of the digital conversion. This parameter affects both the desired output voltage waveform and the FPGA computing time, since the higher the number Fig. 6. Schematic algorithm procedure. TABLE II EXPRESSIONS FOR THE PARAMETER D TABLE III SWITCHING SURFACE DERIVATIVES IN TERMS OF S , S , S AND D of bits, the smaller the quantization error affecting the output voltage waveform, but the longer the control algorithm computing time becomes. This trade-off can be solved from several simulations by including the effects of a quantizer of bits and by numerically evaluating the dependenceofanerrorindexsuchas Total HarmonicDistortion (THD) through the number of bits. Simulations show a good-enough closed-loop output voltage response for an 8-b quantizer. Inaccordancewiththeaforementionedtrade-offs,aMAX118 A/D (eight channels, 8 b of resolution, 1 Msps of maximum sampling frequency and 660 ns of conversion time) has been adopted for the present design. C. FPGA Design Thefunctionalblock diagram ofthedesignedFPGAis shown in Fig. 5, where three different blocks can be distinguished, namely. Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. 348 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003 Fig. 7. Arithmetic block diagram. Fig. 8. Digital PWM block diagram. 1) Thearithmeticblock,whichcomputestheZADalgorithm from the digitized samples of the switching surface and supplies the corresponding duty cycle digital value, according to the expressions of Table I. 2) The digital PWM block, which is in charge of generating thePWMoutput waveformfrom thedutycyclevalue, and of fixing the desired switching frequency. 3) The sequential control block, which generates all the FPGA and ADC control signals. Let us illustrate the main steps of the computational procedure embedded in the FPGA, by obtained the duty cycle determination of the period from the values sampled and computed during the period. The whole computational procedure is based on a switching surface synchronous sampling at twice the desired switching Fig. 9. Dead-time generator: (a) block diagram and (b) time diagram. Fig. 10. Board of the ZAD control loop implementation. frequency. Then, as can be seen in Fig. 6, during the period the following samples are known: (10) Itshould bepointedoutthatthevaluesof and are obtained by sampling 826 ns prior to the end of the period to avoid the switching noise. Assuming that the duty cycle of the period, , is known, the first step is the computation of the parameter , defined as (11) which corresponds to the denominator of the control laws given in Table I. This parameter can be easily calculated from , , Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. RAMOS et al.: FIXED-FREQUENCY QUASI-SLIDING CONTROL ALGORITHM 349 Fig. 11. ZAD simulation results. (a) Steady-state output voltage, v [10 V/div], 180 shifted reference, V ( t ) [10 V/div], and voltage error, e ( t ) [1 V/div]. (b) Steady-state output voltage, v [10 V/div], and capacitor current, i [0.5 A/div]. (c) Steady-state output voltage, v [10 V/div], and switching surface value, S [1 V/div]. (d) Output voltage, v [10 V/div], and load current, i [1 A/div], transient response for a load step change from open circuit to 20  . and . That is, if and (as depicted in Fig. 6), the following relations hold: (12) hence (13) Similarly, the expressions of the parameter depending on the sign of and the value of can be easily derived. These expressions, normalized with respect to the switching period , are summarized in Table II. It can be noticed that these expressions may be applied provided that the two derivatives of (11) are defined during the period, this implying that the control value switches during the period. However, in transient state the ZAD algorithm holds the control action and the switching surface may remain positive (or negative) throughout the period. In this case, one of the two derivatives of (13) is not defined. Nevertheless, the parameter can be deduced from (5) and (11) as (14) or equivalently, by replacing (7) and (8) in (14) (15) The FPGA implementation algorithm can identify this fact and then assign the value given by (15), which may be previously introduced and stored in the FPGA by means of the digital input shown in Fig. 3. Once the value of is known, the next step is the computation of the switching surface derivatives, and . As shown in Table III these derivatives may also be easily computed from the values of , , and . The value of is computed by assuming that the switching surface derivatives vary slowly with respect to the switching period (this assumption is reasonable due to Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. 350 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003 the output voltage low ripple), which enables the following approximation: (16) and for instance, in the case of the second row of Table I, the duty cycle is finally computed as (17) which can be rewritten in terms of , , and , according to Tables II and III, as for (18) Regarding the FPGA algorithm implementation, the Arithmetic block is in charge of both identifying the different cases of Tables I–III and of computing the corresponding expressions, such as eq. (18). These tasks are carried out on an XC4010E-3-PC84 FPGA from Xilinx by means of the proper connection of registers,adders,multipliersandadigitalsquarerootcircuitextractor [37]–[40], as shown in Fig. 7. In addition, although a processing time is needed to evaluate the whole algorithm (see Fig. 6), according to Table I, the control value at can be easily known by considering the sign of the switching surface at the beginning of the period (i.e., the sign of . The proposed FPGA implementation provides this control value and holds it during the processing time. The digital PWM block, implemented as shown in Fig. 8, is composed of an 8-b comparator and an 8-b step-down counter. The outputs of the Arithmetic block and the counter are compared to carry out the voltage to time conversion. An additional T-flip-flop is included to achieve the desired fixed-frequency synchronism. A dead-time block of three clock signal periods, shown in Fig. 9, is also included to prevent an input powerstage short-circuit. Finally, the “sequential control” block generates 24 control signals in order to manage the operation of both the inner blocks of the FPGA and the external A/D converter. The XC4010E-1-PC84 FPGA includes 10000 logic gates and 800 flip-flops embedded in 400 configurable logic block (CLB) and 61 input/output block (IOB). The current design has consumed 245 CLB’s (61% of the available CLB resources), 30 IOB’s (49% of the available IOB resources) and 84 flip-flops (10% of the available FF resources). The duty cycle computation at the beginning of each switching period consumes approximately between 10 and 16 clock periods, which leads to a total processing time ranging from 1.6 s to 2.7 s for a clock frequency of 6 MHz. As a consequence, for a switching period of 42.5 s (23 kHz), a minimum duty cycle of 6.3% may be achieved in the worst case, this allowing a cycle-by-cycle control design. V. SIMULATION AND EXPERIMENTAL RESULTS This section is devoted to the verifying of the proper operation of the ZAD algorithm by means of simulation and experimental results, and to experimental comparing the features of the proposed control algorithm with its sliding counterpart. A full-bridge Buck inverter has been built for this purpose with the following parameters. 1) Buck converter: V, F, mH, . 2) Switching surface:. 3) User-defined parameters: switching frequency = 23 kHz, desired output voltage (reference signal) of . The ZAD control loop Board including the FPGA, the analog conditioner circuitry and the ADC converter are shown in Fig. 10. A. ZAD Simulation Results A MATLAB-SIMULINK simulation of the ZAD-controlled inverter,includinganaccuratemodeloftheFPGA,hasbeencarried out prior to the experimental verification. The steady-state behavior of the output voltage, the voltage error, the capacitor current and the switching surface are shown in Fig. 11(a)–(c), respectively. In addition, Fig. 11(d) shows the output voltage and the load current for a load step change from open circuit to . As can be seen, a fast recovery (less than the twentieth of the output voltage period) of the steady-state is obtained. B. ZAD Experimental Results The same simulation conditions have been experimentally testedinthelaboratory.Thecorrespondingsteady-stateandload step change experimental results are shown from Fig. 12(a) to (d). As can be observed, they are in close agreement with those obtained in the simulations despite a steady-state error of 3%. Fig. 12(e) shows both the output voltage and the output current when the inverter is loaded with a full-wave rectifier; the THD measured in this case is approximately 0.3%, which can be considered a good inverter performance. Finally, the switching control signal spectrum, which evidences the fixed-frequency operation, is presented in Fig. 12(f). C. ZAD Versus Sliding Control In order to explore the differences between the fixed-frequency quasi-sliding ZAD control and its sliding counterpart, Fig. 13(a)–(d) shows the experimental steady-state and load transient responses under the same laboratory conditions using the same switching surface and the sliding control law given in (9). In this case, the steady-state error is slightly lower (2% instead of 3%), and the steady-state recovery slightly faster than that corresponding to the ZAD algorithm. Fig. 13(e) shows the switching control signal spectrum, evidencing the expected variable-frequency operation of the sliding-mode control. Other comparisons of the ZAD controlled inverter are reasonable, for example with PWM-based inverters due to their Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. RAMOS et al.: FIXED-FREQUENCY QUASI-SLIDING CONTROL ALGORITHM 351 Fig. 12. ZAD experimental results. (a) Steady-state output voltage, v [10 V/div], 180 shifted reference, V ( t ) [10 V/div], and voltage error, e ( t ) [1 V/div]. (b) Steady-state output voltage, v [10 V/div], and capacitor current, i [0.5 A/div]. (c) Steady-state output voltage, v [10 V/div], and switching surface value, S [1 V/div]. (d) Output voltage, v [10 V/div], and load current, i [1 A/div], transient response for a load step change from open circuit to 20  . (e) Steady-state output voltage, v [10 V/div], and output current, i [2 A/div], for a full-wave rectifier load. (f) Switching control signal spectrum [10 dB/div]. Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply. 352 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 1, JANUARY 2003 Fig. 13. Sliding control experimental results. (a) Steady-state output voltage, v [10 V/div], 180 shifted reference, V ( t ) [10 V/div], and voltage error, e(t) [1 V/div]. (b) Steady-state output voltage, v [10 V/div], and capacitor current, i [0.5 A/div]. (c) Steady-state output voltage, v [10 V/div], and switching surface value, S [5V/div]. (d)Output voltage, v [10V/div], and load current, i [1A/div],transientresponsefora load step changefromopencircuitto20  .(e) Switching control signal spectrum [10 dB/div]. Authorized licensed use limited to: UNIVERSITAT POLIT?CNICA DE CATALUNYA. Downloaded on October 23, 2009 at 06:18 from IEEE Xplore. Restrictions apply.