Interleaving Modulation Schemes in Asymmetrical Dual Three-Phase Machines for the DC-Link Stress Reduction

Citation: DeMarcos, A.; Robles, E.; Ugalde, U.; Martinez de Alegria, I.; Andreu, J. Interleaving Modulation Schemes in Asymmetrical Dual Three-Phase Machines for the DC-Link Stress Reduction. Machines 2023,11, 267. https://doi.org/ 10.3390/machines11020267 Academic Editor: Krzysztof Pienkowski Received: 13 January 2023 Revised: 1 February 2023 Accepted: 7 February 2023 Published: 10 February 2023 Copyright: © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). machines Article Interleaving Modulation Schemes in Asymmetrical Dual Three-Phase Machines for the DC-Link Stress Reduction Ander DeMarcos * , Endika Robles , Unai Ugalde , Inigo Martinez de Alegria and Jon Andreu Department of Electronic Technology, Faculty of Engineering in Bilbao, University of the Basque Country (UPV/EHU), Plaza Ingeniero Torres Quevedo 1, 48013 Bilbao, Spain *Correspondence: ander[email protected]; Tel.: +34-946-01-3915 Abstract: The DC-Link capacitor plays a crucial role as far as power density and reliability are concerned: it occupies approximately 40% of the inverter, and causes approximately 30% of its failures. Asymmetrical dual three-phase (ADTP) multiphase arrangements are gaining relevance in the automotive sector for powertrain applications. This work focuses on reducing the impact that the widely used double zero sequence injection (DZSI) family of PWM techniques have on such a bulky and failure-prone component in an ADTP arrangement by means of interleaving techniques. By using the double Fourier integral formalism, the input current spectra and the overall performance of these PWM techniques have been derived, in terms of current rms value and voltage ripple in the DC-Link capacitor. Simulations have shown that choosing an adequate interleaving scheme and angle considerably relieves both current and voltage stresses on the DC-Link capacitor compared to noninterleaved operation. Reductions of 84% current rms and 86% voltage ripple have been achieved at static operating points. Finally, by averaging the rms current over WLTP standard driving cycle, reductions up to 26% have been obtained under more realistic conditions. All this would enhance the reliability and reduce the size of the onboard capacitors in future electric vehicles. Keywords: multiphase; interleaving; asymmetrical dual three-phase; double zero-sequence injection (DZSI) PWM; DC-Link capacitor; DC-Link current spectrum 1. Introduction The electric vehicle (EV) powertrain is experimenting a huge change. WBG semiconductors, motors without dependence on rare earth materials and new converter architectures are being introduced. Automotive manufacturers and international programs such as Horizon Europe, USCAR, DOE, and UN ESCAP are focusing on improving specific power (kW/kg), power density (kW/ ` ), efficiency (%), and cost ($/kW) [ 1 ]. In this context, multiphase propulsion systems provide several advantages at an affordable cost compared with classic three-phase electric motor-driven systems. Such benefits include power splitting between phases (lower currents and power losses for the same rated output power), reduction of the torque ripple (enhanced efficiency), torque density improvement using harmonic current injection (in concentrated winding machines), lower DC-Link current ripples (smaller DC-Link capacitor), and intrinsic fault-tolerant operation [2–5]. In order to benefit from the abovementioned advantages of multiphase systems, the recent scientific literature shows that the dual three-phase topology (Figure 1) is probably the most widespread multiphase solution [ 6 – 10 ]. Although odd phase number multiphase star-connected arrangements offer a better relationship between the degrees of freedom and the phase number and semiconductor device number, they have lower fault tolerance regarding short circuit and power supply faults (when dual three-phase arrangements are supplied independently) and their modulation scheme is more complex [ 11 ]. Therefore, multiple three-phase winding machines are preferred. Theoretically, any number of threephase winding sets can constitute this kind of electric machine; the most common is to Machines 2023,11, 267. https://doi.org/10.3390/machines11020267 https://www.mdpi.com/journal/machines Machines 2023,11, 267 2 of 31 find dual three-phase arrangements with two isolated neutral points known as “dual three-phase” [ 12 ]. These configurations are the most interesting because (i) they represent a good tradeoff between performance and complexity; (ii) easy migration from three-phase technologies is possible because multiple generic and modular three-phase inverters can feed the two three-phase winding sets independently [ 13 ]; and (iii) they have very good performance in terms of fault tolerance (open and short circuit faults as well as on the DC power supply) [ 6 , 7 , 14 , 15 ]. Generally, 0 ◦ , 30 ◦ , and 60 ◦ are the preferred angle displacements between the two sets. However, the 30 ◦ type, which is commonly called asymmetrical six-phase or asymmetrical dual three-phase (ADTP) machine (Figure 1), provides higher torque density and lower torque ripple than the others [ 16 ] because it eliminates the sixth torque harmonic pulsation through the synchronization of the two winding sets [17,18]. ibat iinv icap sa1 sb1 sc1 sa1 sb1 sc1 ia1 ib1 ic1 n1 VDC a1b1c1 sa2 sb2 sc2 sa2 sb2 sc2 ia2 ib2 ic2 n2 a2b2c2 iinv1 VSI1 ADTP VSI2 iinv2 iinv1a iinv2a iinv1b iinv1c iinv2b iinv2c 30º a1 a2 b1 n1 b2 c1c2 CDC n2 Figure 1. Asymmetric dual three-phase electric machine with two parallel three-phase VSIs. Thus, ADTP-specific voltage-source inverters (VSIs) have been developed, which show great potential in safety-critical applications, and when high power density is needed, such as in electric vehicle (EV) drivetrains [ 19 ]. These VSIs (Figure 1) can be controlled by using either appropriate space vector (SV) [ 20 – 24 ] or carrier-based (CB) [ 25 – 30 ] PWM techniques. There is a wide variety of SV-PWM techniques for the ADTP topology; some of them utilize two large adjacent active vectors to synthesize the reference voltage vector [ 20 ], and others use four large active vectors [ 20 , 21 ], three large active vectors plus one medium active vector [22], or two large and two medium active vectors [23]. In contrast, CB-PWM strategies are usually treated as a dual three-phase structure (VSI 1 and VSI 2 , Figure 1), instead of a six-phase system. This implies an advantage over the SV-based approach because conventional CB-PWM techniques can be exploited. Figure 2shows how these three-phase CB-PWM techniques are implemented, where v∗=Mcos(θ1) is the modulating signal, v0s is the injected zero-sequence component, v∗∗ =v∗+v0s is the modified modulating signal, θ1 is the modulating signal’s angular position and the modulation index ( M ) is defined as M=ˆ V1/(0.5·VDC) [ 31 ], where ˆ V1 is the peak phase-neutral voltage and VDC is the DC-Link voltage (Figure 1). Machines 2023,11, 267 3 of 31 ++ ++ ++ + va** sa sc sb vb** vc** v0s vcr va* vb* vc*1 0 1 0 1 0 − + − + − (a) CB-PWM block diagram. 0 1 θ1 [rad] 2π 0π π 2 3π 2 v** v0s v* −1 (b) MINMAX-PWM. 0 1 −1 θ1 [rad] 2π 0π π 2 3π 2 v** v0s v* (c) THI-PWM. 0 1 θ1 [rad] 2π 0π π 2 3π 2 v** v0s v* −1 (d) D-PWMMIN. 0 1 θ1 [rad] 2π 0π π 2 3π 2 v** v0s v* −1 (e) D-PWMMAX. θ1 [rad] 0 1 2π 0π π 2 3π 2 v** v0s v* −1 (f) D-PWM0. 0 1 θ1 [rad] 2π 0π π 2 3π 2 v** v0s v* −1 (g) D-PWM1. θ1 [rad] 0 1 2π 0π π 2 3π 2 v** v0s v* −1 (h) D-PWM2. θ1 [rad] 0 1 2π 0π π 2 3π 2 v** v0s v* −1 (i) D-PWM3. Figure 2. CB-PWM block diagram as well as their voltage references and zero sequence signals. CB-PWM techniques applied in a “split” six-phase inverter are commonly known as double zero-sequence injection (DZSI) PWM techniques because this implies injecting one zero-sequence component ( v0s ) into each three-phase structure [ 25 ]. They can be classified into continuous and discontinuous modulation techniques [ 31 ]. Sinusoidal PWM (SPWM, as the zero sequence signal which is injected in SPWM is 0, sometimes it is not considered Machines 2023,11, 267 4 of 31 as DZSI-PWM technique), third harmonic injection PWM (THI-PWM) and min-max PWM method (MINMAX-PWM, sometimes also called symmetrical SV-PWM) are known as continuous modulations (C-PWM), in which all the inverter branches switch continuously. D-PWMMIN, D-PWMMAX, D-PWM0, D-PWM1, D-PWM2, and D-PWM3 are known as discontinuous PWM (D-PWM) techniques, in which one branch does not switch over a whole switching period (while the modulating signal is clamped to ± 1, Figure 2). Thus, the switching power losses in the semiconductors of the VSI are reduced for discontinuous PWM techniques because only two out of the three branches are actually switching and the average equivalent switching frequency is reduced to 2/3fsw . Finally, all these carrier-based PWM techniques allow a maximum modulation index Mmax = 1.15 working in the linear region except for SPWM technique in which Mmax =1. At hardware level, the DC-Link capacitor ( CDC , Figure 1) is a crucial element of the VSI. This capacitor is responsible for reducing the low-frequency voltage ripple at the input of the converter, in both steady and transient states, as well as storing the necessary energy to allow an instantaneous power balance between the converter input and output. It must provide a low impedance path for high-frequency currents in order to decouple and reduce the current ripple from the battery. More importantly, in traction applications, the DC-Link capacitor is a bulky and expensive component because it amounts to up to 40% of the total volume of the VSI [ 32 – 35 ]. In addition, DC-Link capacitors are also considered to be one of the most critical elements in power electronics because they cause 30% of the total failures in power electronic inverters [ 36 – 38 ]. For this reason, the reliability of these reactive components has been discussed deeply during the last several years [39–42]. The selection of the DC-Link capacitor (technology, capacitance, size, weight, cost, etc.) is highly dependent on the DC voltage rating of the application where they are integrated [ 40 ]. To date, light EV batteries ranged from 250 to 450 V [ 43 ], whereas for heavy vehicles the rated voltage is about 800 V. In this context, a trend change is taking place in which electric mobility manufacturers are committed to offering more solutions for these 800-V systems, because this permits the utilization of lighter wiring [ 44 ] and also produces smaller on-state power losses, higher efficiency and power density motors, and faster charge of the battery pack [ 45 ]. At higher DC voltages, the capacitance of CDC decreases for the same size or encapsulation [ 46 ], and its lifetime is significantly reduced. For example, AVX automotive film capacitors of the FHC1 series has a lifetime of an order of magnitude of 10,000 h at 400 V, whereas at 900 V the lifetime drops to approximately 1000 h [46]. In addition to the DC voltage rating, there are other important specifications to select an appropriate DC-Link capacitor: voltage ripple, which is inversely proportional to the capacitance and the size of the DC-Link capacitor [ 47 , 48 ], and current ripple [ 32 , 34 , 49 ]. Any voltage ripple on the DC-Link produces an additional current ripple on the phase currents, which worsens torque ripple in the electric machine. In this context, there is often a specification for the maximum allowable voltage ripple on the DC-Link (typically ranging from 5–10%). The current ripple is conditioned by the maximum hot-spot temperature of the DCLink capacitor. This internal temperature depends on the power losses due to the equivalent series resistance (ESR) and is inversely proportional to the lifetime of the component. Thus, manufacturers typically specify the maximum rms ripple current rating at an ambient temperature and a specific frequency. Because the DC-Link capacitor is a critical component, significant efforts are being made to enhance its performance. Some works propose to minimize the DC-Link capacitor’s current stress by the synchronization of parallel-interleaved single-phase inverters [ 50 , 51 ] and three-phase inverters [ 52 – 59 ]. In ADTP machines, constant interleaving angles can be used to reduce the DC-Link capacitor current for the MINMAX-PWM and some discontinuous PWM techniques [ 49 , 60 – 62 ]. Ref. [ 63 ] proposes a dynamic interleaving method to reduce the DC-Link current ripple, which is only applicable to discontinuous PWM techniques. Machines 2023,11, 267 5 of 31 However, it is not common to find research works that analyse in-depth the effect of the interleaving angle on the input harmonic cancellation and the rms current minimization of the ADTP arrangement. Furthermore, the few existing contributions usually focus on one or two specific PWM techniques, which makes it hard to compare and quantify the performance of the various DZSI-PWM techniques. As a result, identifying the best interleaving angle for each DZSI-PWM technique applied in an ADTP arrangement is also missing in the scientific literature. This paper focuses on reducing the current and voltage stress in the DC-Link capacitor by using a multiphase VSI and DZSI-PWM techniques suitable for ADTP arrangement. Different aspects are discussed throughout the paper. In Section 2, DC-Link current spectra are analysed by using the double Fourier integral method for DZSI-PWM techniques in ADTP converters, which are directly related to the main voltage and current stress variables (rms current and peak-to-peak voltage ripple) for the DC-Link capacitor. The figure-ofmerit considered in the scientific literature is the output current quality, which is directly related to the total harmonic distortion (THD) or the flux harmonic distortion factor (HDF). However, this ignores how the modulation technique affects the converter input. Thus, Section 3mathematically analyses and simulates the effect of the DZSI-PWM techniques on the input current spectrum and how it affects the DC-Link capacitor in an ADTP arrangement. Due to the need to reduce the rms value of the DC-Link capacitor current, Section 4expresses different interleaving schemes and how the relationship between the input current harmonic spectrum and the constant interleaving can be exploited in order to cancel certain dominant harmonics. Next, in order to display the importance of using this type of interleaving techniques, Section 5shows both the rms current and the peak-to-peak voltage of the DC-Link capacitor applying the optimal interleaving scheme for each DZSIPWM technique. Finally, Section 6draws the corresponding conclusions, emphasizing that the performance of the DC-Link capacitor can be significantly improved by applying a suitable interleaving scheme. 2. DC-Link Capacitor Current and Voltage Stress in Asymmetrical Dual Three-Phase Inverters Voltage ripple and DC-Link capacitor current ( icap , Figure 1) rms value play a crucial role in the selection of an appropriate DC-Link capacitor. The current in the ADTP inverter determines the capacitor current. Figure 3shows the detailed flow chart followed in this work in order to obtain the harmonic spectrum of the DC-Link capacitor for the described ADTP system. Here, two parallel procedures have been implemented: (i) in Matlab executing the corresponding code for the mathematical equations synthesized in this section; and (ii) in Matlab–Simulink by using a higher-level block environment. The current harmonic spectra obtained from both procedures have been compared to each other in order to check the result matching. In the next lines, the harmonic spectrum of the ADTP inverter is studied in detail. 2.1. Current Spectrum Theoretical Basics for an ADTP Inverter 2.1.1. Input Current of One Branch of VSI1(iinv1a) The double Fourier integral formulation characterizes a double periodic function in the frequency domain [ 64 ]. Such is the case of a generic analog PWM waveform g[x(t),y(t)] , where x(t)= 2 πfswt and y(t)= 2 πf1t=θ1 are two time variables, with fsw the carrier frequency and f1<fsw the fundamental frequency. Thus, according to that formulation, Machines 2023,11, 267 6 of 31 g(x,y)=A00 2 DC offset + ∞ ∑ n=1hA0ncos ny +B0nsin nyi Fundamental, and Baseband Harmonics + ∞ ∑ m=1hAm0cos mx +Bm0sin mxi Carrier Harmonics (1) + ∞ ∑ n=−∞ but n6=0 ∞ ∑ m=1hAmn cos(mx +ny)+Bmn sin(mx +ny)i Sideband Harmonics , where Amn =1 2π2 π Z −π π Z −π g(x,y)cos(mx +ny)dx dy, (2) Bmn =1 2π2 π Z −π π Z −π g(x,y)sin(mx +ny)dx dy, (3) or, in complex form, Cmn =Amn +jBmn =1 2π2 π Z −π π Z −π g(x,y)ej(mx+ny)dx dy. (4) Thus, |Cmn|=pA2 mn +B2 mn represents the spectral magnitude of each harmonic, which arises at frequency values equalling fh=m fsw +n f1 , where m is the carrier index variable and nis the baseband index variable. Figures 2and 4show how the voltage patterns of a PWM-driven inverter are synthesized as a function of the reference and carrier voltages, i.e., v∗∗ and vcr , respectively. As is usual [ 65 , 66 ], let us assume that fsw f1 ; therefore, the phase currents are sinusoidal, with amplitude ˆ Iout and phase lag φwithout any high-frequency ripple current, so ia1=ˆ Iout cos(2πf1t−φ)=ˆ Iout cos(y−φ); (5) then, because iinv1a results from the sampling of ia1 by following the same voltage PWM pattern, Equations (1)–(4) can be applied with g(x,y) = (0 when v∗∗ ≤vcr, ˆ Iout cos(y−φ)when v∗∗ >vcr.(6) As Figure 4shows, the limits of the inner integral for the rising and falling portions of g(x , y) equal xr=−π 2[1+v∗∗(y)] and xf=π 2[1+v∗∗(y)] . Therefore, from (1) – (4) the harmonic coefficients of iinv1aresult [65,66] in Cinv1a mn =ˆ Iout 2π2 2π Z 0    [1+v∗∗(y)]π 2 Z −[1+v∗∗(y)]π 2 cos(y−φ)·ej(mx+ny)dx  dy. (7) Thus, Equation (7) quantifies the spectrum of the current iinv1a , emphasizing its dependance on the PWM technique and modulation index M through the limits of the inner integral v∗∗(y)as well as on the phase lag φ. Machines 2023,11, 267 7 of 31 DZSI-PWM technique selection Cmn calculation (6) inv1a inv1 Cmn calculation (9) icap,rms calculation (12)-(14) inv Cmn calculation: - without (11) - with (31) M value selection fh value selection M range completed? Yes No fh range completed? Yes No Matlab script Simulink model CDC harmonic analysis CDC stress reduction DZSI-PWM technique selection Run simulation End End θ1 [rad] 0 1 -1 2π 0π π 23π 2 v** v0s v* 0 -0.5 -1 0.5 2Tsw Tsw 2 3Tsw 0 2 Tsw fh fh range M range 0.07 -0.07 -0.14 0.14 2Tsw Tsw 2 3Tsw 0 0 2 Tsw Δvcap,pp m=1 m=2 m=3 m=4 0.1 0.2 0.3 0.4 0 n=-3 n=3 n=0 peak=0.765 n=0 Modulating signal construction ( ) v** Cmn calculation (6) inv1a Cmn calculation (6) inv1 Cmn calculation (6) inv a1b1c1 a2b2c2 inv1 inv fh=n f1+m fsw () m and n determination 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 10.9 ζc= rad π 2 ζ=0 rad ζd ζopt m=1 m=2 m=3 m=4 0.1 0.2 0.3 0.4 0 n=-3 n=3 n=0 peak=0.765 n=0 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 10.9 ζc= rad π 2 ζ=0 rad ζd ζopt m=1 n=-3 Signal measurement (iinv, iinv1, icap, vcap...) Plot iinv FFT 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 10.9 ζd=ζc ζopt ζ=0 rad Plot ΔVcap,max Plot icap,rms Repeat simulation until M range completed m0.1 0.5 1 0 0.5 1 1234567M Amplitude [p.u] Cmn Initialization fh range, M range, f1, fsw, Io, ... Cmn inv icap,rms inv Check result matching Check result matching icap,rms Δvcap,max Δvcap iinv FFT icap Figure 3. CDC harmonic analysis and rms calculation flow chart. 2.1.2. Input Current of VSI1(iinv1) The Fourier coefficients for the consecutive branches ‘1b’ and ‘1c’ ( Ciinv1b mn and Ciinv1c mn ) of the VSI 1 (Figure 1) can be obtained by taking (7) and replacing ny with n(y+2π 3) and n(y+4π 3) , respectively (the current pulses of this branches are phase shifted 2π/3 rad 4π/3rad concerning the branch ‘1a’). Likewise, it can be phase shifted Ciinv1a mn as Ciinv1b mn =Ciinv1a mn ·ejn 2π 3, (8) Ciinv1c mn =Ciinv1a mn ·ejn 4π 3. (9) However, because iinv1=iinv1a+iinv1b+iinv1c(Figure 1), Ciinv1 mn =Ciinv1a mn ·h1+ejn 2π 3+ejn 4π 3i=Ciinv1a mn ·1+2cosn2π 3, (10) where, it can be inferred that Ciinv1 mn = 0 for all values of n except for 0 and multiples of 3. This means that at the output phase currents of each three-phase VSI within the ADTP, where the harmonics multiples of 3 times the fundamental cancel each other out, at the Machines 2023,11, 267 8 of 31 input, the opposite happens. Thus, there only exist high-frequency carrier and sideband triplens harmonics at the converter input because the PWM methods eliminate all the low-order baseband harmonics. +1 -1 -π+π 0 0xrxf x=ωswt x=ωswt 0 +1 -1 0 v**(y) g(x,y) Tsw vcr vcr -π 2π +2 V Block diagram v** vcr v** Figure 4. CB-PWM and integration limits of (7). 2.1.3. Input Current of ADTP (iinv) The ADTP is composed of two three-phase stator windings displaced spatially by 30 electrical degrees ( π/6 rad). Usually, each three-phase subsystem has its own isolated neutral point (n 1 and n 2 , Figure 1). Thus, following a similar analysis to (10), the Fourier coefficients for the input current harmonics of the second three-phase stator winding ( Ciinv2 mn ) result in Ciinv2 mn =Ciinv1a mn ·1+2cosn2π 3·ejn π 6, (11) where ejn π 6 corresponds to the 30 ◦ displacement of the second stator winding with respect to the first one. From (10)–(11), the Fourier coefficients of the input current of the ADTP result in Ciinv mn =Ciinv1a mn ·1+2cosn2π 3·h1+ej(nπ 6)i. (12) The difference among the input current harmonics of a three-phase system (10) and an asymmetrical dual three-phase VSI (12) is the h1+ej(nπ 6)i term, which equals 0 for n= 6 (2k+1)∀k∈Z . This leads to the cancellation of some of the existing high-frequency carrier and sideband triplens harmonics at the input of each of the ADTP converter. 2.2. Definition of RMS Current and Voltage Ripple in DC-Link Capacitor The worst scenario for the DC-Link capacitor is when the whole input current ripple of the ADTP comes from the DC-Link capacitor ( icap =iinv,AC ) and the battery only supplies the average current of the inverter ( Ibat =Iinv,avg ) [ 53 , 67 – 70 ]. Thus, the rms value of the DC-Link current (Figure 1) can be expressed as Icap,rms =qI2 inv,rms −I2 inv,avg , (13) where the rms value of the input current is Iinv,rms =v u u u t ∞ ∑ n=0 Ciinv 0n √2  2 + ∞ ∑ m=1 ∞ ∑ n=−∞ Ciinv mn  √2  2 , (14) Machines 2023,11, 267 9 of 31 and the average value of the input current of the ADTP is Iinv,avg =6 4Mˆ Iout cos φ. (15) Assuming that at the dominant current harmonic’s frequency the capacitor has a predominantly capacitive reactance, the RL impedance can be neglected, so the DC-Link voltage variation can be expressed as ∆vcap(t) = 1 C t Z 0 icap dt =1 C t Z 0 (iinv −Iinv,avg)dt. (16) Considering this, Figure 5a shows the current through the DC-Link capacitor and Figure 5b its voltage ripple according to (16). Applying a normalization factor ∆vbase =ˆ Iout·Tsw/C to the voltage ripple of (16), the peak-to-peak value of the voltage ripple in every switching period (Tsw) can be obtained by ∆vcap,ppTsw =max∆vcap(t)Tsw −min∆vcap(t)Tsw , (17) which makes it possible to determine the maximum value of the switching voltage ripple over T1 (or θ1= 2 πrad ). Because the input current to the ADTP is repeated every 2π/6rad (Figure 5c), it is sufficient to perform the analysis during this interval, so ∆vcap,max =max∆vcap,pp2π=max∆vcap,pp2π/6 . (18) 0 −0.5 −1 0.5 Tsw 4 3Tsw 0 icap 4 Tsw 2 Tsw time [s] (a) Current waveform over two Tsw. 0 Tsw 4 3Tsw 4 Tsw 2 Tsw time [s] 0.07 −0.07 −0.14 0.14 0 Δvcap Δvcap,pp (b) Voltage waveform over two Tsw. 0.2 0.1 0 0.3 Δvcap,pp Δvcap,max time [s] 0T1 6 5T1 3 2T1 6 T1 2 T1 3 T1 (c) Voltage waveform over a T1. Figure 5. Normalized current and voltage in the DC-Link capacitor with SPWM technique, M= 0.9 and cos φ= 1. Machines 2023,11, 267 16 of 31 lar current pulses depends on the amplitude ˆ Iout and the square root of the duty cycle ( Iinv1,rms =√D·ˆ Iout , Figure 11). When an interleaving angle ζ= 0 rad is applied between two inverters, the current pulses of both VSIs are totally overlapped, and the resulting pulses are doubled in amplitude, which leads to a double rms current value of the interleaved inverter current ( Iinv,rms = 2 ·√D·ˆ Iout ). As the interleaving angle is increased, the overlap is reduced, and in turn, the rms value of the resulting waveform is reduced. When the interleaving angle between the pulses is large enough for them not to overlap ( ζ≥D ), the rms current is minimized ( Iinv,rms =√2·√D·ˆ Iout ). This way, a reduction of the rms value is achieved with respect to the previous cases without interleaving (Figure 11). In order to analyse the concept of interleaving in depth, three different schemes will be introduced: constant interleaving, dynamic interleaving, and optimal interleaving. vcr2 iinv1 D iinv2 iinv Iout Iout 2Iout Iinv,rms=2· D·Iout Iinv,rms vcr1 v** x Tsw (a) No interleaving (ζ=0◦). iinv2 vcr1 iinv1 iinv Iinv,rms D ζ Iout Iout 2Iout Iout vcr2 x v** Iinv,rms= 2·ζ+4·(D-ζ)·Iout (b) Overlapping (ζ<D). iinv1 iinv2 iinv Iout Iout Iout Iinv,rms D ζ Iinv,rms= 2· D·Iout x vcr1 vcr2 v** (c) No overlapping (ζ≥D). Figure 11. Interleaving concept on rectangular current pulses. 4.1. Constant Interleaving: ζc The concept of interleaving can be applied to the Fourier double series of the input current of the VSI 2 by adding an additional phase shift with respect to the input current of the VSI 1 (Figure 1). As Figure 11 shows, because x(t) is the variable related to the carrier wave angle, the Fourier coefficients for branch ‘a’ of the consecutive inverter ‘2’ ( Ciinv2a mn ) can be calculated by taking (7) and replacing mx with m(x+ζc) . This can be also represented as Ciinv2a mn =Ciinv1a mn ·ejmζc, (30) where ejmζc corresponds to the shifting caused by the interleaving of the second carrier signal (vcr2, in Figure 11). The introduction of this new parameter affects Ciinv2 mn of (11) and Ciinv mn of (12), leading to Ciinv2 mn =Ciinv1a mn ·1+2cosn2π 3·ejn π 6·ejmζc, (31) Ciinv mn =Ciinv1a mn ·1+2cosn2π 3·h1+ej(nπ 6+mζc)i. (32) In (32), it can be observed that making the second term in brackets h1+ej(nπ 6+mζc)i equal to 0, an interleaving angle ζc that cancels some specific input current harmonics ( Ciinv mn , (12)) is obtained: ζc=(2k+1)·π−nπ 6 m∀k∈Z+. (33) Machines 2023,11, 267 17 of 31 In this sense, and because the dominant harmonic is the most important component when it comes to computing the rms value of the whole current spectrum through the capacitor, the interleaving angle ( ζc ) should eliminate this dominant harmonic. Table 2 summarizes the most significant constant interleaving angles and the harmonic orders cancelled. This table also points out when the most relevant input current harmonics are removed: letting ζc=π/2 rad erases the (2,0) and (1,3) harmonics, whereas letting ζc=πrad erases the (1,0) harmonic. As a collateral effect, sometimes other harmonics can slightly increase their amplitude. Therefore, the angle which eliminates the dominant input current harmonic and the one which minimizes Icap,rms can be different. For example, Figure 12 shows the input current spectrum for the ADTP with SPWM technique, M= 0.9, cos φ = 1 and two interleaving angles ( ζc= 0 rad and ζc=π/2 rad). For this case, it can be observed that the dominant harmonic (2,0) has been cancelled out, but (1, − 3) and (2, ± 6) have increased their amplitude. Therefore, the selection of the interleaving angle has to be made carefully. m=1 n=3 n=0 n=6 n=-6 n=-3 m=2 0.2 0.4 0.6 0.8 0 π 2 =0 rad ζc= rad ζc Figure 12. Input current spectrum for the ADTP with SPWM technique, M= 0.9, cos φ = 1 and two interleaving angles. In view of this, numerical calculations have been carried out in Matlab following the procedure explained in Section 2for each DZSI-PWM technique, by sweeping the modulation index M and the interleaving angle ζc . All these calculations show that the ζc=π/2 rad constant angle minimizes Icap,rms regardless of the value of M for all the analysed DZSI-PWM techniques except for D-PWMMIN and D-PWMMAX, in which ζc=π rad is the best choice for any value of M . However, from the numerical analysis carried out, it has been seen that the constant angle applied for the entire period of the fundamental of D-PWMMIN and D-PWMMAX ζc=π is the best option only for M⩽ 0.75; and for M> 0.75 the interleaving angle which minimizes the Icap,rms is only constant for each fundamental period but not for rest of the linear range. This is explained better in Section 4.3. This analysis coincides with the above performed input harmonic spectra of Figure 10, as well as with the removal of the dominant harmonics observed in Table 2. Table 2. Eliminated (m,n) harmonics depending on ζcaccording to (33). k=0k=1k=2 ζc=π/2rad (2,0) (6,0) (10,0) (1,3) (5,3) (9,3) (3,−3) (7,−3) (11,−3) ζc=πrad (1,0) (3,0) (5,0) (2,6) (4,6) (6,6) (2,−6) (4,−6) (6,−6) Finally, as an example of this analysis, Figure 13 shows the case of the SPWM technique. Here, note that for M= 0.35 (Figure 13a), Icap,rms is at minimum when ζc lies between 1.08 and 2.06 rad even though the current spectra is not the same (Figure 13c–e. Performing the same analysis in the whole linear region of M , for 0 ⩽M< 0.5, there is not a single ζc which minimizes Icap,rms but a range of values (Figure 13b); however, for 0.5 ⩽M⩽ 1 Machines 2023,11, 267 18 of 31 there is just one ζc value ( π/2 rad) that is considered the best choice ζc in the entire range of Mfor the SPWM technique. interleaving angle ζ [rad] 0.4 0.8 0.6 1 0 Icap,rms π 4 π 2 π 4 3ππ 4 5π 4 7 π 2 32π 1.08 2.06 ( a ) Normalized Icap,rms as a function of the interleaving angle ζfor M=0.35. modulation index [p.u.] π 10.90.8 0.70.60.50.40.30.20.1 ζ π 4 3 π 2 π 4 0 1.08 2.06 ζc ( b ) Constant interleaving angle ζc for the whole linear range. m=1 m=2 m=3 m=4 0.2 0.4 0.6 0 ( c ) Input current spectrum of the ADTP with ζ=1.08 rad and M=0.35. m=1 m=2 m=3 m=4 0.2 0.4 0.6 0 ( d ) Input current spectrum of the ADTP with ζ=π/2rad and M=0.35. m=1 m=2 m=3 m=4 0.2 0.4 0.6 0 ( e ) Input current spectrum of the ADTP with ζ=2.06 rad and M=0.35. Figure 13. Input current under constant interleaving angle applying the SPWM technique. 4.2. Dynamic Interleaving Scheme for Discontinuous PWM Techniques: ζd Unlike the constant interleaving scheme discussed above, a dynamic interleaving algorithm ζd applicable only for discontinuous PWM has been recently proposed in [ 63 ] to reduce the DC-Link current ripple of the ADTP. In this case, the interleaving angle of the proposed method is not constant. In some subintervals of the fundamental period cycle, ζ is set to πrad whereas the rest of the time it is 0 rad. In any discontinuous PWM technique, the peak-to-peak value of the input current of the VSI without any interleaving rises significantly when any two nearby phases ( Figure 14a ) in the phasor diagram are clamped to ± 1. As an example, Figure 14 shows the operation basics of ζd for D-PWM1 and D-PWMMIN. Figure 14b,c show the input current of the VSI without interleaving ( ζ= 0 rad) for these discontinuous PWM techniques and Figure 14d,e their respective voltage references of the ADTP. In the case of D-PWMMIN, two nearby phases in the phasor diagram are continuously clamped to ± 1 (Figure 14e). This leads to a continuous activation of the dynamic interleaving algorithm (Figure 14g, ζd in blue). This means that for this specific PWM technique, the dynamic interleaving scheme is exactly the same as applying a constant angle of ζc=π rad. The effect of applying this angle can be visualized in Figure 14f,g for D-PWM1 and D-PWMMIN, respectively. The peak-to-peak values of the input currents are reduced significantly comparing to the ζ= 0 rad scenario of Figure 14b,c. The techniques D-PWM0, D-PWM2 and D-PWM3 follow the same pattern as D-PWM1, whereas D-PWMMAX behaves as D-PWMMIN in terms of full-time clamping. Therefore, for both D-PWMMIN and D-PWMMAX, applying the dynamic interleaving scheme would be exactly like applying the scheme ζc=πrad explained in the previous subsection. Machines 2023,11, 267 19 of 31 a1 a2 b1 n1 b2 c1c2 n2 ( a ) ADTP phasor diagram. 0 1.5 0.5 2 iinv 1 θ1 [rad] 2π 0π π 2 3π 2 high peak-to-peak current ( b ) Input current of the VSI without interleaving (ζ=0 rad) for D-PWM1. 0 1.5 0.5 2 iinv 1 θ1 [rad] 2π 0π π 2 3π 2 high peak-to-peak current ( c ) Input current of the VSI without interleaving (ζ=0 rad) for D-PWMMIN. θ1 [rad] 0 1 v** 2π 0π π 2 3π 2 b1 b2 0 1 v** −1 2π 0π π 2 3π 2 two nearby phases clamped a2 a1 0 1 v** 2π 0π π 2 3π 2 c1 c2 −1 −1 ( d ) Voltage references of the VSI of the ADTP for D-PWM1. θ1 [rad] 0 1 v** A1B2 C1 C2 2π 0π π 2 3π 2 A2 B1 a1 a2 c2 −1 0 1 v** A1B2 C1 C2 2π 0π π 2 3π 2 A2 B1b2c2 c1 −1 0 1 v** A1B2 C1 C2 2π 0π π 2 3π 2 A2 B1 −1 b1 b2 a2 ( e ) Voltage references of the VSI of the ADTP for D-PWMMIN. 0 1.5 0.5 2 iinv 1 θ1 [rad] 2π 0π π 2 3π 2 peak-to-peak current reduction ζd 0 π ( f ) Input current of the VSI and the instantaneous interleaving angle applying ζd for D-PWM1. 0 1.5 0.5 2 iinv 1ζd 0 π θ1 [rad] 2π 0π π 2 3π 2 peak-to-peak reduction ( g ) Input current of the VSI and the instantaneous interleaving angle applying ζd for D-PWMMIN. Figure 14. Dynamic interleaving method proposed in [63] for D-PWM1 and D-PWMMIN. As a counterpart, this dynamic interleaving scheme ( ζd ) has some disadvantages compared to the constant interleaving ( ζc ); i.e., more computational resources are needed Machines 2023,11, 267 20 of 31 in order to detect the voltage reference clampings between two nearby phases in the phasor diagram; in addition, it is only applicable for discontinuous PWM techniques. 4.3. Optimal Interleaving Scheme for any DZSI-PWM: ζopt The optimal interleaving scheme ( ζopt ) can be defined as the one which minimizes Icap,rms over the entire linear region, 0 ⩽M⩽ 1. In the case of continuous techniques, ζopt =ζc because a dynamic interleaving scheme cannot be used. Therefore, the optimal interleaving angle can be considered ζc=π/2rad. In the case of the D-PWMMIN and D-PWMMAX techniques, it is a bit more complex. First, it is worth remembering that as the dynamic interleaving is applied continuously, it is the same as applying a constant interleaving of ζc=π rad. In addition, following the numerical analysis described in Section 4.1 and as Figure 15 shows, ζ=π rad minimizes Icap,rms for 0 ⩽M⩽ 1. However, for higher modulation indexes, the interleaving angle becomes smaller. This happens because in this range of M , although the (1,0) harmonic is not completely cancelled, the harmonics that have great influence on the rms value of the current, such as (1,0) and (2,0), are considerably attenuated. modulation index [p.u.] π 10.90.8 0.70.60.50.40.30.20.1 ζ π 4 3 π 2 π 4 0 ζopt(M) D-PWMMIN & D-PWMMAX ζd=ζc=π rad Figure 15. Constant and optimal interleaving angles for the whole linear range for D-PWMMIN and D-PWMMAX. Finally, for the rest of discontinuous techniques (D-PWM0, D-PWM1, D-PWM2 and D-PWM3), the optimal interleaving scheme consists of comparing both interleaving algorithms and selecting the one which gives the smallest Icap,rms for each modulation index. Therefore, the implementation of this optimal interleaving scheme is performed following the indications in Figure 16. The next section will show the results obtained for all the interleaving schemes. DZSI-PWMs Modulation index (M) 0-0.30 0.30-0.80 0.80-0.85 0.85-0.95 0.95-1 Continuous SPWM THI-PWM MINMAX-PWM Discontinuous D-PWMMIN D-PWMMAX D-PWM0 D-PWM1 D-PWM2 D-PWM3 π or d π/2 as a function of M (Figure 15) or π/2 π/2 π/2 π/2 d d d d d Figure 16. Optimal interleaving scheme as a function of the selected DZSI-PWM technique and M for cos φ=1. 5. Influence of Interleaving for DZSI-PWM Techniques on the Current Ripple and Voltage in the DC-Link Capacitor The influence of DZSI-PWM techniques on Icap,rms and ∆vpp,max has been identified through the interleaving schemes described in Section 4as a function of M and for cos φ= 1 by using the methodology described in Figure 3. In contrast to three-phase VSIs, where the rms current through the DC-Link capacitor is independent of the chosen PWM technique [ 67 ], in the ADTP with double zero sequence injection technique it is strongly dependent on it. This happens due to the 30 ◦ shifting between the two three-phase inverters forming the ADTP. The rms value of the input Machines 2023,11, 267 21 of 31 current of either the first inverter or the second inverter do not depend on the modulation technique but their sum does: Iinv,rms 6=Iinv1,rms +Iinv2,rms. (34) In general terms, in EV applications, the DC-Link capacitor is selected mainly considering the ripple current through the capacitor. As there are no low-frequency harmonic components as in single-phase converters, the voltage ripple is lower for a multiphase application with the same power rating. For this reason, the optimal interleaving angle must be selected based on the current profile and not on the basis of the voltage ripple. However, in any case, it is also interesting to analyse whether this optimal interleaving scheme which minimizes Icap,rms also reduces ∆vpp,max . The Icap,rms results shown in the following section were obtained by using the double Fourier integral analysis of Section 2and the results that correspond to ∆vpp,max were obtained by a numerical analysis in Matlab–Simulink. Finally, in Section 5.3 Icap,rms is simulated for EV dynamic conditions applying the WLTP driving cycle. 5.1. RMS Value of the Current Through DC-Link Capacitor at Static Operating Points Figure 17 shows the rms current curves for the different DZSI-PWM techniques. Here, it can be observed that without using interleaving algorithm (in blue) D-PWM1, DPWM0, D-PWM2, and D-PWM3 present the lowest Icap,rms (in that order) and continuous techniques, as well as D-PWMMIN and D-PWMMAX have the highest values of Icap,rms . Although the differences between these two main PWM groups are bigger for central values of M (0.4 <M< 0.7), when M gets close to 1 ( M> 0.9), all analysed PWM techniques tend to equalise. These continuous PWM techniques, as well as D-PWMMIN and D-PWMMAX, present a maximum value at M≈0.6. When the proposed optimal interleaving scheme is applied (Figure 17, in black), continuous modulations with ζopt =π/2 rad reduce Icap,rms of up to 62% for SPWM, 84% for MINMAX-PWM and 80% for THI-PWM. For discontinuous modulations, reductions up to 80% for D-PWMMIN and D-PWMMAX and 78% for D-PWM0, D-PWM1, D-PWM2 and D-PWM3 are obtained. D-PWM1 and MINMAX-PWM provides the lowest values of Icap,rms (in that order). 5.2. Voltage Ripple in the DC-Link Capacitor at Static Operating Points Even though the main idea of the interleaving approach is to reduce the rms value of the current through the DC-Link capacitor, Figure 18 shows that it also reduces the DC-Link voltage ripple (∆vcap,max) for all DZSI-PWMs. Unlike the rms value of the current through the DC-Link capacitor, when no interleaving (ζ=0 rad) is applied, continuous PWM techniques (MINMAX-PWM, THI-PWM and SPWM, in that order) present the lowest ∆vpp,max , and discontinuous techniques present the highest values of ∆vcap,max (Figure 18). Specifically, MINMAX-PWM provides the smallest and D-PWM0 provides the highest voltage ripple among these noninterleaved DZSI-PWM techniques. When the proposed optimal interleaving scheme ( ζ=ζopt ) is applied, the following maximum reductions of ∆vpp,max are obtained: up to 64% for SPWM, 86% for MINMAXPWM, 85% for THI-PWM, 90% for D-PWMMIN and D-PWMMAX, 88% for D-PWM0, 90% for D-PWM1, 90% for D-PWM2, and 91% for D-PWM3. The DZSI-PWM technique which presents the smallest ∆vpp,max once the optimal interleaving scheme is applied is MINMAX-PWM. Machines 2023,11, 267 22 of 31 Icap,rms 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 M 10.9 rad π 2 ζc= ζopt= ζ=0 rad 62 % (a) SPWM. Icap,rms 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 M 10.9 ζ=0 rad rad π 2 ζc= ζopt= 84 % (b) MINMAX-PWM. Icap,rms M 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 10.9 ζ=0 rad rad π 2 ζc= ζopt= 80 % (c) THI-PWM. Icap,rms 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 M 10.9 ζ=0 rad ζopt rad π ζc= ζd= 80 % (d) D-PWMMIN and D-PWMMAX. Icap,rms 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 M 10.9 ζc= rad π 2 ζ=0 rad ζd ζopt 78 % (e) D-PWM0. Icap,rms 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 M 10.9 ζc= rad π 2 ζ=0 rad ζd ζopt= 78 % (f) D-PWM1. Icap,rms 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 M 10.9 ζc= rad π 2 ζ=0 rad ζd ζopt 78 % (g) D-PWM2. Icap,rms 0 0.1 0.25 0.5 0.75 0.2 0.3 0.4 0.5 0.6 0.80.7 1 M 10.9 ζc= rad π 2 ζ=0 rad ζd ζopt 78 % (h) D-PWM3. Figure 17. Normalized DC-Link rms current for DZSI-PWM techniques as a function of M. As has been seen in this section, the combination of the optimal interleaving scheme and DZSI-PWM techniques is a good alternative in order to reduce the stress variables on the DC-Link capacitors of the ADTP power converters for electric vehicles. However, it is enough to apply a constant interleaving scheme ( ζc ) in order to reduce the current stress on the DC-Link capacitor considerably. 5.3. RMS Value of the Current through DC-Link Capacitor during Standardized Driving Cycles Figure 19 shows the block diagram of the ADTP platform and the simulation model used to obtain the results during EV dynamic conditions. The vehicle battery has been modelled as a 400 V DC source according to the typical values of electric vehicles [ 43 ]. The selected DC-Link capacitance has been 600 µ F. The motor that has been modelled is the one indicated in Table 1(Section 3.1). A maximum motor current of 25 A has been set and the base mechanical speed of the motor has been changed to 2400 rpm. Lastly, the control algorithm used is explained in detail in [ 79 ] and the switching frequency of the power devices has been set to 25 kHz. Matlab–Simulink has been used to execute the simulation models, and they have been embedded on an OPAL-RT OP4510 high-performance, real-time platform, which has accelerated the simulation time considerably. The simulation step has been set to 1 µ s. In addition, in order to visualize in a more didactic way and compare of the results with Machines 2023,11, 267 23 of 31 and without interleaving, the results have been postprocessed with a moving average of 2000 samples. 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζopt=ζc= rad π 2 ζ=0 rad 64 % (a) SPWM. ζ= rad π 2 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζ=0 rad 86 % ζopt=ζc= rad π 2 (b) MINMAX-PWM. 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζ=0 rad ζopt=ζc= rad π 2 (c) THI-PWM. 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζd=ζc ζopt ζ=0 rad (d) D-PWMMIN and D-PWMMAX. 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζd ζc= rad π 2 ζ=0 rad ζopt (e) D-PWM0. 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζc= rad π 2 ζ=0 rad ζopt=ζd (f) D-PWM1. 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζc= rad π 2 ζ=0 rad ζopt ζd (g) D-PWM2. 0 0.1 0.2 0.4 0.6 0.2 0.3 0.4 0.5 0.6 0.80.7 M 10.9 ζ=0 rad ζ= rad π 2 ζopt ζd (h) D-PWM3. Figure 18. Normalized maximum switching voltage ripple within one period of the fundamental. ibat iinv icap sa1 sb1 sc1 sa1 sb1 sc1 ia1 ib1 ic1 n1 a1b1c1 sa2 sb2 sc2 sa2 sb2 sc2 ia2 ib2 ic2 n2 a2b2c2 iinv1 VSI1 VSI2 iinv2 iinva1 iinva2 iinvb1 iinvc1 iinvb2 iinvc2 CDC GUI OP4510 RTlab platform Communications bus Laptop Power converter (ADTP) IPMSM model (VDQ) Results v G1-G12 wmech θ,ω Duty cycles Console vehicular model Field Oriented Control (FOC) Vbat Tem * Vbat Battery icap data Control data Modulation 0.5 0.25 0.75 speed 1 0 time [s] 200 180014001000600 WLTP driving cycle 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms 0 -0.5 0.5 torque 1 -1 time [s] 200 180014001000600 i 6 t t Figure 19. RTlab OP4510 simulation platform diagram for electric vehicle ADTP propulsion systems. Machines 2023,11, 267 24 of 31 Figure 20 shows the results of Icap,rms in the whole WLTP driving cycle, with and without constant interleaving angle for each DZSI-PWM technique ( ζc=π/2 rad for the techniques SPWM, MINMAX-PWM, THI-PWM, D-PWM0, D-PWM1, D-PWM2, DPWM3; and ζc=π rad for D-PWMIN and D-PWMMAX). Here, it can be observed that all the analysed PWM techniques reduce Icap,rms when the interleaving scheme is applied. Likewise, Table 3shows the mean value of the rms current throughout the entire WLTP driving cycle. These results confirm that an adequate constant interleaving scheme reduces the current stress on the DC-Link capacitor considerably. These simulations show that reductions up to 26% can be achieved. The largest reductions are provided by continuous PWM techniques, and the lowest values of Icap,rms are found for discontinuous PWM techniques. However, these D-PWMs are not so often used in EV application because they worsen the quality of the output voltage waveform. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π 2 ζc= (a) SPWM. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π 2 ζc= (b) MINMAX-PWM. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π 2 ζc= (c) THI-PWM. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π ζc= (d) D-PWMMIN and D-PWMMAX. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π 2 ζc= (e) D-PWM0. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π 2 ζc= (f) D-PWM1. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π 2 ζc= (g) D-PWM2. 2 1 3 4 0 time [s] 200 180014001000600 Icap,rms ζ=0 rad rad π 2 ζc= (h) D-PWM3. Figure 20. DC-Link RMS current for DZSI-PWM techniques in WLTP driving cycle with (in red) and without (in blue) constant interleaving schemes. Machines 2023,11, 267 25 of 31 Table 3. DC-Link rms current ( Icap,rms ) for noninterleaved DZSI-PWM techniques and using the correspondent constant interleaving angle ζcfor the WLTP driving cycle. Noninterleaved (A) Interleaved (A) Reduction (%) SPWM 1.06 0.82 22.94 MINMAX-PWM 1.13 0.82 27.48 THI-PWM 1.13 0.82 27.25 D-PWMMIN 0.82 0.64 21.23 D-PWMMAX 0.83 0.64 22.67 D-PWM0 0.78 0.65 16.01 D-PWM1 0.71 0.59 16.27 D-PWM2 0.72 0.61 16.01 D-PWM3 0.79 0.67 15.37 6. Conclusions The ADTP has turned out to be one of the most successful multiphase arrangement in the short term for electric traction applications due to its intrinsic advantages, such as enhanced efficiency and fault-tolerant operation. In power converters in general, and therefore also in ADTP architecture, the DC-Link capacitor is a critical element that represents a considerable fraction of the volume and source of failures because it is responsible for up to a 40% of the total volume and 30% of the total failures in power electronic inverters. This work focuses on the DC-Link stress reduction in order to benefit this capacitors by means of the following figures of merit: rms value of the ripple current through the DC-Link capacitor ( Icap,rms ) and the maximum peak-to-peak voltage ripple ( ∆vcap,max ). For that purpose, the input current spectra of the ADTP arrangement have been analysed by using the double Fourier integral method for the DZSI-PWM techniques. Although each branch of the multiphase VSI presents certain input current harmonics, the interaction between the different branches inherent to the ADTP architecture cancels them out and changes the amplitude of some of these harmonics. All these input current harmonics depend mainly on the selected DZSI-PWM technique, as well as on M and cos φ . For electric vehicle applications, the main vehicle standard driving cycles NEDC and WLTP using a PMSM demonstrate that the value of the power factor is cos φ> 0.97. Thus, the current spectra for these DZSI-PWM techniques have been obtained as a function of M and for cos φ= 1. Here, it has been observed that continuous PWM techniques (SPWM, MINMAX-PWM, and THI-PWM) have a predominant carrier wave harmonics at 2 fsw ; D-PWM0, D-PWM1, D-PWM2, and D-PWM3 have a wide sideband harmonic range around fsw , even though their carrier wave harmonics at 2 fsw cannot be neglected; finally, D-PWMMIN and D-PWMMAX have their predominant current harmonics at fsw and 2fsw. Due to lack of in-depth research in the scientific literature about the interleaving schemes for this kind of ADTP arrangements, this work has analytically derived the relationship between the input current harmonic spectrum and the constant interleaving angle ( ζc ), as well as how this can be exploited in order to cancel certain dominant harmonics inherent to these DZSI-PWM techniques. As a result, the rms value of the ripple current through the DC-Link capacitor ( Icap,rms ) and the maximum peak-to-peak voltage ripple ( ∆vcap,max ) has been reduced. This confirms that the elimination of the dominant input current harmonics is directly related to the minimization of Icap,rms. It has been concluded that for all continuous PWM techniques the optimal interleaving angle is ζc=π/2 rad because it eliminates the dominant carrier harmonic at 2 fsw . For discontinuous PWMs, a combination between the dynamic (only applicable for discontinuous PWM techniques) and the constant interleaving schemes is generally preferred. During the subinterval in which the constant interleaving scheme is applied, for D-PWM0, D-PWM1, D-PWM2, and D-PWM3 ζc=π/2 rad is preferred because their 2 fsw carrier wave harmonic and fsw + 3 f1 sideband harmonic are cancelled out. However, for D-PWMMIN