Development of a CubeSat payload for in-orbit computing and LoRa communications

UNIVERSITAT POLITÈCNICA DE VALÈNCIA School of Telecommunications Engineering Development of a CubeSat payload for in-orbit computing and LoRa-based communications Master's Thesis Master's Degree in Telecommunication Engineering AUTHOR: Pino Mena, Juan del Tutor: Boria Esbert, Vicente Enrique Cotutor: Martínez Pérez, Jorge Daniel ACADEMIC YEAR: 2024/2025 Master’s Degree in Telecommunications Engineering Master’s Thesis “Development of a CubeSat payload for in-orbit computing and LoRa-based communications” Academic course: 2024/2025 Author: Juan Del Pino Mena Supervisors: Vicente Enrique Boria Esbert Department of Communications Jorge Daniel Martínez Pérez Department of Electronic Engineering Cite this work: @phdthesis{cite-key, author = "Juan Del Pino Mena and Vicente Enrique Boria Esbert and Jorge Daniel Martínez Pérez", title = "Development of a CubeSat payload for in-orbit computing and LoRa-based communications", school = "Universitat Politècnica de València", year = "2025", month = "9", address = "Camí de Vera, s/n, 46022 València, Valencia, Spain", type = "Master's Thesis" } Juan Del Pino Mena, Vicente Enrique Boria Esbert and Jorge Daniel Martínez Pérez This work is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0) license. 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Juan Del Pino Mena ð§# Juan Del Pino Mena was born in 2000 in Arriate, Málaga, Spain. He completed the Bachelor’s degree in Telecommunications Engineering at the University of Granada (UGR) in 2022. He was affiliated with the GranaSat group and participated as technical staff for Esero CanSat Spain 2022. His bachelor’s thesis was awarded first prize as the best telecommunications bachelor’s thesis in Andalucía in 2022 and as the best in the electronic systems category in Spain in 2023. He studied a double Masters in Telecommunications Engineering and Electronic Systems Engineering at the Polytechnic University of Valencia (UPV). Since 2022, he has held the position of Payload Engineer at Pluton UPV, a student team developing a CubeSat for which the payload developed in both theses is intended; and since 2024, he is the head of Pluton UPV’s Hardware Department. Starting 2024, he is also a researcher at the Microwave Applications Group (GAM/MAG) of the Institute of Telecommunications and Multimedia Applications (iTEAM-UPV). Vicente Enrique Boria Esbert ð# Vicente E. Boria Esbert was born in Valencia, Spain, in 1970. He received the Degree in Telecommunications and PhD in Telecommunications from the Universitat Politécnica de València (UPV) in 1993 and 1997, respectively. In 1993, he joined the Communications Department, where he has been a Full Professor since 2003. In 1995 and 1996 he was a trainee in the European Space Research and Technology Centre (ESTEC-ESA). He has authored or coauthored ten chapters in technical textbooks, 180 articles in international journals, and over 200 papers in international conference proceedings. His current research interests include the analysis and automated design of passive components, left-handed and periodic structures, and the simulation and measurement of power effects in passive waveguide systems. Dr. Boria Esbert is a member of the IEEE Microwave Theory and Techniques Society (IEEE MTT-S), the IEEE Antennas and Propagation Society (IEEE AP-S), the European Microwave Association (EuMA) and the Technical Committees of the IEEE-MTT International Microwave Symposium and the European Microwave Conference. He acts as a regular reviewer of the most relevant IEEE and IET technical journals in his areas of interest. He was an Associate Editor of IEEE Microwave and Wireless Components Letters and Electronics Letters (IET). He also serves as a Subject Editor (Microwaves) for Electronics Letters (IET) and as an Editorial Board Member for International Journal of RF and Microwave Computer-Aided Engineering. Jorge Daniel Martínez Pérez # Jorge Daniel Martínez was born in Murcia, Spain, in 1979. He received the Telecommunication Engineering degree and the PhD in Electrical Engineering from the Universitat Politècnica de València (UPV) in 2002 and 2008, respectively. In 2002, he joined the Department of Electronic Engineering. In 2007, he was a visiting researcher at XLIM CNRS-Université de Limoges, France, working on the design and fabrication of RF MEMS components at MINACOM group. He was appointed as an Assistant Professor in UPV in 2009 and was promoted to an Associate Professor in 2012. He is currently the Deputy Director of the Department of Electronic Engineering and a Member of the I3M Research Institute at UPV, where he is the Head of the Laboratory for High Frequency Circuits (LCAF). His current research interests are focused on reconfigurable microwave components, passive devices in planar and SIW technologies, and multi-layer fabrication for microwave and millimeter-wave. He has authored or co-authored more than 80 publications in journals and international conferences and he serves as an Associate Editor for IEEE Microwave and Wireless Components Letters, and reviewer for the IEEE Transactions on Microwave Theory and Techniques and IEEE Microwave and Wireless Components Letters. Development of a CubeSat payload for in-orbit computing and LoRa-based communications Keywords: AI, Artificial Intelligence, Compute Module, CubeSat, EDP, Engineering Design Process, Embedded System, Estigia, Gateway, IoT, Internet of Things, LEO, Low-Earth Orbit, Link Budget, LoRa, Nano-Satellite, PCB, Printed Circuit Board, Payload, Pluton UPV, RF, Radio-Frequency, Simulation, Space Communications Abstract: This Master’s Thesis deals with the development of an embedded system designed to perform computing and communications tasks in a CubeSat type nano-satellite flying in low earth orbit (LEO). The project entails the development of the hardware for the payload of Estigia, Pluton UPV’s first CubeSat mission. Pluton UPV is a team of students interested in the development of nano-satellites under the Generación Espontánea programme of the Universitat Politècnica de València (UPV). The purpose of the Estigia mission is to enable users on Earth to communicate directly with a chatbot running on the satellite by only using their smartphones and low-cost LoRa-based mini-ground stations. To achieve this, the CubeSat payload developed in this Master’s Thesis incorporates a Compute Module (CM) to provide the processing power needed for the onboard Artificial Intelligence (AI) running the chatbot, as well as a LoRa gateway. LoRa is a Low-Power Wide-Area Network (LPWAN) technology oriented towards the Internet of Things (IoT), characterised by its long-range, low-power and low-cost communication capabilities. This Master’s Thesis in Telecommunications Engineering represents a continuation of the author’s previous Master’s Thesis in Electronic Systems Engineering. In light of the results and lessons learned from the preceding thesis, this new development iteration re-evaluates the original design with the aim of streamlining it and adapting it to changes in requirements and mission objectives. This thesis therefore reviews the system’s operational conditions and evaluates several hardware designs prior to their incorporation into the payload’s final design. The working methodology employed is based on the Engineering Design Process (EDP). The project uses several CAD and EDA tools in order to simulate and implement the electronics, taking manufacturing and testing considerations into account. The final objective of this Master’s Thesis is to demonstrate the application of multidisciplinary knowledge, the capacity for analysis and synthesis inherent to engineering, as well as the documentation of the entire process. This Master’s Thesis has also benefited from the collaboration of the Microwave Applications Group (MAG), a member of the Institute of Telecommunications and Multimedia Applications (iTEAM-UPV). v Desarrollo de una carga útil CubeSat para computación en órbita y comunicaciones basadas en LoRa Palabras clave: IA, Inteligencia Artificial, Módulo de computación, CubeSat, EDP, Proceso de Diseño de Ingeniería, Sistema Embebido, Estigia, Pasarela, IoT, Internet de las Cosas, LEO, Órbita Terrestre Baja, Balance de Enlace, LoRa, Nano-satélite, PCB, Placa de Circuito Impreso, Carga útil, Pluton UPV, RF, Radiofrecuencia, Simulación, Comunicaciones Espaciales Resumen: El presente Trabajo de Fin de Máster (TFM) aborda el desarrollo de un sistema embebido destinado a la realización de tareas de computación y comunicaciones en un nanosatélite tipo CubeSat que vuela en órbita baja terrestre (LEO). El proyecto se centra en el desarrollo del hardware de la carga útil de Estigia, la primera misión CubeSat de Pluton UPV. Pluton UPV es un equipo de estudiantes pertenecientes al programa Generación Espontánea de la Universitat Politècnica de València (UPV) interesados en el desarrollo de nano-satélites. El objetivo de la misión Estigia es permitir a los usuarios en la Tierra comunicarse directamente con un chatbot ejecutado en el propio satélite, utilizando para ello únicamente smartphones y mini-estaciones terrestres de bajo coste basadas en LoRa. Para cumplir este fin, la carga útil del CubeSat desarrollada en este TFM incorpora un módulo de computación que proporciona la potencia de procesamiento necesaria para la Inteligencia Artificial (IA) a bordo del satélite que ejecuta el chatbot, así como una pasarela LoRa. LoRa es una tecnología Low-Power Wide-Area Network (LPWAN) orientada al Internet de las Cosas (IoT), caracterizada por su capacidad de comunicación de largo alcance, bajo consumo y bajo coste. Este TFM en Ingeniería de Telecomunicaciones (MUIT) representa la continuación de un TFM anterior del mismo autor en Ingeniería de Sistemas Electrónicos (MUISE). Teniendo en cuenta los resultados precedentes, esta nueva iteración reevalúa el diseño anterior con el objetivo de simplificarlo y adaptarlo a los cambios en los requisitos y objetivos de la misión. Para ello, este trabajo revisa las condiciones de operación y evalúa varios diseños de hardware antes de incorporarlos al diseño final de la carga útil. La metodología de trabajo empleada se basa en el Proceso de Diseño de Ingeniería (EDP). Durante el proyecto se hace uso de herramientas CAD y EDA para simular e implementar la electrónica, sin perder de vista consideraciones de fabricación y testeo. El objetivo final del presente Trabajo de Fin de Máster es demostrar la aplicación de conocimientos multidisciplinares, la capacidad de análisis y síntesis inherentes a la ingeniería, así como la documentación de todo el proceso. Este Trabajo de Fin de Máster ha contado a su vez con la colaboración del Grupo de Aplicaciones de Microondas (GAM), miembro del Instituto de Telecomunicaciones y Aplicaciones Multimedia (iTEAM-UPV). vii Y así como todo cambia Que yo cambie no es extraño “Todo cambia”, Julio Numhauser, 1982 Cantada por Mercedes Sosa en “¿Será posible el Sur?”, 1984 xv Contents About the authors iii Abstract v Executive overview xi Acknowledgements xiii Dedication xv Table of contents xix List of figures xxii List of tables xxiii Glossary xxv 1 Introduction 1 1.1 Motivation ....................................... 2 1.1.1 Pluton UPV and the Estigia mission ..................... 2 1.1.2 Academic return ............................... 3 1.1.3 Collaborators, sponsors, market and customers .............. 3 1.2 State of the Art ..................................... 4 1.2.1 CubeSats .................................... 4 1.2.1.1 The CubeSat electronics ..................... 6 1.2.2 Internet of Things, LPWAN and LoRa in satellite systems ........ 7 1.2.3 Edge computing and Artificial Intelligence in CubeSats .......... 8 1.3 Scope and methodology ................................ 8 1.3.1 Engineering Design Process ......................... 9 1.4 Objectives ....................................... 10 1.5 Project tasks timeline ................................. 10 1.6 Report structure .................................... 12 2 Starting point, changes and updates 13 2.1 The first design iteration ............................... 13 2.2 Firmware compatibility and the two payloads ................... 14 2.3 Design methodology and improvements ...................... 15 2.4 Updated radio link budget simulations ....................... 16 2.4.1 Change in the frequency band ........................ 16 2.4.2 Orbit ...................................... 18 2.4.3 Sources of absolute frequency error ..................... 19 2.4.4 Dynamic frequency error: the Doppler rate ................ 19 2.4.4.1 Study for the SX126x/7x nodes and the SX1301 gateway IC . . 20 2.4.4.2 Study for the LR11xx nodes and the SX1302 gateway IC . . . . 21 2.4.4.3 Results and discussion ...................... 21 2.4.5 Power budget ................................. 23 2.4.5.1 Sensitivity ............................. 23 2.4.5.2 Attenuation ............................ 23 xvii 2.4.5.3 Transmission power ........................ 24 2.4.5.4 Power budget results ....................... 25 2.4.6 Signal-to-noise ratio budget ......................... 25 2.5 Discussion ....................................... 26 3 Evaluation boards 29 3.1 Design overview .................................... 29 3.2 Fabrication ....................................... 33 3.2.1 Panelisation .................................. 33 3.2.2 Soldering ................................... 34 3.2.3 Bring-up .................................... 38 3.3 Tests .......................................... 39 3.3.1 Calibration and de-embedding ........................ 39 3.3.2 RF tests definition and results ........................ 41 3.3.2.1 Characterisation of the de-embedding kit ............ 41 3.3.2.2 Test RF.1: SX1250 LNA input impedance ............ 42 3.3.2.3 Test RF.2: SX1261 LNA input impedance ............ 43 3.3.2.4 Test RF.3: SX1250 PA output impedance ............ 43 3.3.3 Power tests definition ............................ 44 3.3.3.1 Test PWR.1: Evaluation of the TPS62912 DC/DC converter . . 44 3.3.3.2 Test PWR.2: Evaluation of the INA232 power monitor . . . . . 44 3.3.3.3 Test PWR.3: Evaluation of the TPS259474 eFuse ........ 44 3.4 Discussion ....................................... 45 3.4.1 Optimum PA load impedance and 1 dB load pull .............. 45 3.4.2 Optimum LNA source impedance and 1 dB noise source pull ....... 45 4 Specification 47 4.1 Requirements ..................................... 47 4.2 Hardware architecture ................................ 49 4.2.1 Digital ..................................... 49 4.2.2 Radio ...................................... 50 4.2.3 Power system ................................. 52 4.2.4 Mechanical considerations .......................... 53 4.3 Component selection ................................. 54 4.3.1 Compute module ............................... 54 4.3.2 CAN-SPI converter and CAN transceivers ................. 55 4.3.3 Power amplifier ................................ 55 4.3.4 Low Noise amplifier ............................. 55 4.3.5 RF power splitter ............................... 55 5 Design 57 5.1 Schematics ....................................... 57 5.1.1 Best practices ................................. 57 5.1.2 General outline ................................ 58 5.1.3 Radio schematics ............................... 59 5.1.3.1 RF front-end ............................ 59 5.1.3.2 LoRa transceivers ......................... 69 5.1.3.3 LoRa baseband processor ..................... 75 5.1.4 Digital schematics .............................. 75 5.1.4.1 Compute Module ......................... 75 5.1.4.2 CAN bus .............................. 79 5.1.4.3 Interfaces .............................. 79 xviii 5.1.5 Power schematics ............................... 81 5.1.5.1 Power source ORing ....................... 82 5.1.5.2 Electronic fuses and current sense ................ 82 5.1.5.3 Voltage regulators ......................... 82 5.2 Printed circuit board ................................. 85 5.2.1 Design rules .................................. 85 5.2.2 Materials, stackup and layer assignment .................. 85 5.2.3 Trace width, controlled impedance and via sizes .............. 86 5.2.4 Best practices ................................. 87 5.2.5 Walkthrough of the printed circuit board .................. 89 5.2.5.1 Layout ............................... 89 5.2.5.2 Radio ................................ 89 5.2.5.3 Digital ............................... 90 5.2.5.4 Power ............................... 90 6 Conclusion and future lines 95 6.1 Achieved milestones .................................. 95 6.2 Personal assessment .................................. 96 6.3 Lessons learned, improvements and future lines .................. 96 Bibliography 99 A Sustainable Development Goals 109 B Project costs 111 C Circuit schematics 113 C.1 Evaluation Board EB-SX1250 ............................. 114 C.2 Evaluation Board EB-SX1261 ............................. 115 C.3 Evaluation Board EB-POWER ............................ 116 C.4 TOSM de-embedding kit for the input port of the EB-SX12xx ........... 120 C.5 Through de-embedding kit for the output port of the EB-SX1250 ......... 121 C.6 CubeSat payload .................................... 122 D Printed Circuit Boards 141 D.1 Panel of evaluation boards and de-embedding kits ................. 142 D.2 Payload ......................................... 146 E Interfaces, connections and pin allocation 153 F CubeSat antenna measurements and tuning 157 G Receiver RF budget spreadsheets 159 xix xx List of Figures 1.1 Organizations that have contributed to this thesis. ................. 1 1.2 Conceptual diagram of the Estigia mission. ..................... 2 1.3 Standard sizes of CubeSats. .............................. 5 1.4 Nano-satellite launches by year. ........................... 5 1.5 Example CSKB board and stack. ........................... 7 1.6 The Engineering Design Process. ........................... 10 1.7 Gantt chart of the complete timeline of the project. ................ 11 2.1 Render of the modules, carrier and EGSE, from the first iteration. ........ 13 2.2 Block diagram of the subsystems and of the first iteration of the payload. . . . . 14 2.3 Simplified drawing of the orbit geometry. ...................... 18 2.4 Elevation of the ground station and slant range for several orbit heights. . . . . 18 2.5 Latency and Doppler shift for several orbit heights. ................ 19 2.6 LoRa PHY frame structure and spectrogram of a LoRa frame. ........... 20 2.7 Doppler rate for LoRa packets when varying the packet size, SF and orbit height. 22 2.8 Doppler rate for packets and symbols varying the packet size, SF and orbit height. 22 2.9 Evaluation of the power flux density. ........................ 24 2.10 Received signal power in uplink and downlink. ................... 25 2.11 Signal-to-Noise Ratio in uplink and downlink. ................... 26 2.12 Details of some commercial LoRa gateway modules. ................ 27 3.1 Renders of the EB-SX1250 and EB-SX1261 evaluation boards. ........... 30 3.2 PCB prints of the EB-SX1250 evaluation board. ................... 30 3.3 PCB prints of the EB-SX1261 evaluation board. ................... 30 3.4 Renders of the de-embedding kit. .......................... 31 3.5 PCB prints of the TOSM de-embedding kit. ..................... 31 3.6 PCB prints of the RF output thru kit. ......................... 31 3.7 Render of the EB-POWER evaluation board. .................... 32 3.8 PCB prints of the EB-POWER evaluation board. .................. 32 3.9 Render of the PCB panel for the evaluation boards. ................ 33 3.10 Stencil alignment for solder paste deposition. .................... 34 3.11 Pick & Place machine and reflow oven for assembly of the SMD components. . . 35 3.12 Chip placement process. ............................... 35 3.13 Inspection of solder paste deposition and solder problems. ............ 36 3.14 Inspection of solder joints with a microscope. ................... 36 3.15 Soldered boards. .................................... 37 3.16 Probing of some signals from the SX1250 evaluation board. ............ 38 3.17 Reference plane after calibration and after de-embedding. ............. 39 3.18 Photos taken during the measurements. ....................... 40 3.19 S-parameters of the RF input de-embedding kit. .................. 41 3.20 S-parameters of the RF output de-embedding kit. .................. 42 3.21 Test results for the SX1250’s LNA source impedance. ............... 42 3.22 Test results for the SX1261’s LNA source impedance. ............... 43 3.23 Test results for the SX1250’s PA output impedance (not de-embedded). ..... 44 3.24 Setup for the measurement of the 1 dB load/source pull. .............. 46 3.25 Gain and constant output power contours. ..................... 46 4.1 High-level block diagram of the digital part. .................... 50 xxi 4.2 High-level block diagram of the LoRa radio. .................... 51 4.3 High-level block diagram of the power system. ................... 52 4.4 Renders of the SatNOGS COMMS board. ...................... 53 4.5 The Raspberry Pi Compute Module 5. ........................ 54 5.1 Low-level, hierarchical block diagram of the complete payload. .......... 58 5.2 Simulated circuit and frequency response of the antenna filter. .......... 59 5.3 Low-level, hierarchical block diagram of the radio part. .............. 60 5.4 Schematic of the RF front-end and filter for the antenna and PA. ......... 61 5.5 Analysis of the impedance of the two candidate PAs. ............... 62 5.6 Simulated circuit and frequency response of the transmit path. .......... 63 5.7 Schematic of the radio transmit path: power amplifier and filters. ........ 64 5.8 Comparison of the S-parameters of the transmit path. ............... 65 5.9 Simulation of the noise figure in the receiving path. ................ 66 5.10 Simulated circuit and frequency response of the receive path. ........... 67 5.11 Schematic of the radio receive path: low-noise amplifier, filters and power splitter. 68 5.12 Estimation of the output impedance of the SX1250. ................ 69 5.13 Circuit and simulation of the RFO matching network. ............... 70 5.14 Simulated circuits of the three-element and four-element baluns. ......... 71 5.15 Return loss and phase balance of the baluns. .................... 72 5.16 Transmission coefficient and magnitude balance of the baluns. .......... 73 5.17 Schematics of a SX1250 modem and the transceivers’ TCXO. ........... 74 5.18 Schematic of the LoRa baseband processor. ..................... 76 5.19 Low-level, hierarchical block diagram of the digital part. ............. 77 5.20 Schematic of the relevant parts of the Raspberry Pi Compute Module 5. . . . . . 78 5.21 Schematic of the temperature sensors. ........................ 78 5.22 Schematic of the CAN A transceiver and CAN to SPI converter. ......... 79 5.23 Schematic of the two USB type-C connectors and SD-card reader. ........ 80 5.24 Low-level block diagram of the power supply’s eFuse and regulators. ...... 81 5.25 Organisation and dependency of the different power rails available in the payload. 81 5.26 Schematic of the ideal diodes for power source ORing. ............... 82 5.27 Schematic of the eFuse for the RF power supply and the current-sense ADC. . . 83 5.28 Schematic of the RF voltage regulators. ....................... 84 5.29 6-layer, controlled impedance PCB stackup. ..................... 85 5.30 Structure of a microstrip and a stripline. ....................... 87 5.31 Impedance of capacitors and their combined impedance. ............. 88 5.32 PCB prints: front layer and internal layer 1. ..................... 91 5.33 PCB prints: internal layers 2 and 3. ......................... 92 5.34 PCB prints: internal layer 4 and bottom layer. ................... 93 5.35 Renders of the payload. ................................ 94 B.1 Chart illustrating the costs of the project. ...................... 111 E.1 Schematic and pinout of the OBC PL1 connector and the CSKB headers. . . . . . 153 E.2 CubeSat Kit Bus (CSKB) pin allocation for the Estigia CubeSat. .......... 154 E.3 Diagram of the subsystems and their interconnections for the Estigia CubeSat. . 155 F.1 Antenna measurement setup. ............................. 157 F.2 Return loss measurements during the antenna tuning process. .......... 158 G.1 RF budget of the gateway reference design and the payload with ideal components.160 G.2 RF budget of the payload with realistic components. ................ 161 xxii List of Tables 1.1 Principal top-level objectives of this project. .................... 10 2.1 Link budget simulation parameters. ......................... 16 2.2 Requirements for non-specific short-range devices. ................ 17 2.3 List of contributions to absolute frequency error. .................. 19 2.4 Time-on-air and maximum allowed Doppler rate for different spreading factors. 21 2.5 Summary of worst-case external attenuation in the power budget. ........ 24 4.1 Payload requirements. ................................. 47 4.1 Payload requirements. ................................. 48 4.1 Payload requirements. ................................. 49 4.2 Estimation of power consumption of the digital system. .............. 52 4.3 Estimation of power consumption of the radio system. .............. 52 5.1 Trace widths in each net class. ............................ 86 5.2 Via sizes and ratings. ................................. 86 A.1 Relationship of this project with the SDGs of the 2030 Agenda. .......... 110 B.1 Breakdown of the project costs. ........................... 111 F.1 Return loss measurements during the antenna tuning process. .......... 157 xxiii 4 Chapter 1. Introduction 1.2 State of the Art In the past century, space missions were primarily funded by the public sector and pursued scientific, societal and geopolitical objectives. They were predominantly driven by government or public entities such as NASA, ESA, Roscosmos and JAXA. Traditional space missions have typically relied on highly sophisticated, bespoke technologies that have been rigorously tested and designed to adhere to the highest quality standards and comply with numerous regulations. While technical performance generally took precedence over economic efficiency, the substantial capital expenditure associated with these missions favoured conservative, risk-averse development methodologies and rigid systems engineering processes. Aside from broader spillover benefits to other industries, there were limited direct economic returns [12], [13]. The 2000s and 2010s were marked by a shift towards privatisation and the emergence of innovative business models within the space sector, the so-called “new space”. This phenomenon encompasses a broad spectrum of participants, including government institutions, large system integrators, start-ups, and academia. Alongside publicly-funded projects, private entities are carrying out for-profit space ventures, normally using a combination of public and private capital. Some large private-sector initiatives have focused primarily on satellite constellations, such as Kuiper, Starlink, Iridium and OneWeb. The activities of new space players span diverse domains, such as space exploration, geolocation, communications, remote sensing, Earth observation, meteorology, in-orbit services, Internet of Things (IoT), education, and military applications [12]–[16]. A defining feature of new space actors is their pursuit of economically viable access to space. This is supported by advances in miniaturised technology, novel development processes, and less rigid risk management methodologies. Among the many shifts in development are new satellite platforms such as micro-satellites and nano-satellites, with CubeSats being the undisputed leader [13], [17]–[19]. 1.2.1 CubeSats A CubeSat is a standardised satellite that adheres to the CubeSat Design Specification (CDS) [20]. This standard defines satellites based on cubic units, each measuring 10 cm on a side. This dimension strikes a balance between volume and surface area for solar cells [21]. Many satellite types of different sizes and weights are derived from this fundamental volume unit (see Figure 1.3). The standard also includes the design of the P-POD deployer: a specialised container engineered to safely carry and deploy CubeSats as secondary payloads inside a launch vehicle [18]. CubeSats were originally conceived in 1999 by Professor Jordi Puig-Suari of California Polytechnic State University and Professor Bob Twiggs of Stanford University’s Space Systems Development Laboratory as an educational tool to encourage satellite development in academic institutions. Their innovative, risk-tolerant approach has since been recognised by numerous entities and gained widespread adoption, particularly for scientific and commercial missions. The compactness, modularity and reduced cost of CubeSats facilitate rapid development programmes [18], [22]. As of April 2025, 2956 CubeSats have been launched and hundreds are announced annually [23] (see Figure 1.4). 4 Development of a CubeSat payload for computing and LoRa communications 1.2. State of the Art 5 (a) (b) Figure 1.3 – Standard sizes of CubeSats. Units in mm. Extracted from [24] (modified). Nanosatellite launches by types 211 274 22 910 14 19 12 25 88 142 129 86 297 244 188 162 329 334 390 280 316 nanosats.eu 2025/04/30 1998 2000 2002 2003 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 0 50 100 150 200 250 300 350 400 Nanosatellites Picosats (0.1-1 kg) Other nanosats (1-10 kg) Other CubeSats 16U CubeSat 12U CubeSat 6U CubeSat 3U CubeSat 2U CubeSat 1U CubeSat 0.25U CubeSat Announced launch year Nanosats 2024 prediction Figure 1.4 – Nano-satellite launches by year as of April 2025 [19]. Juan Del Pino Mena 5 6 Chapter 1. Introduction Due to their inherent development cycles, which can span from mere months to a few years, CubeSat missions tolerate a high degree of risk [25]. The idea is that a series of flights will collectively achieve the programme’s overall objectives [18]. In order to ensure that any failures are tolerable, it is necessary to keep costs low. Consequently, CubeSats make extensive use of commercial off-the-shelf components (COTS). 1.2.1.1 The CubeSat electronics The CubeSat Design Specification (CDS) intentionally avoids defining the electronics, which allows missions to implement bespoke solutions tailored to their needs. However, this has resulted in a lack of standardization among COTS component vendors, making per-mission customization necessary and often leading to vendor-locked ecosystems. The CubeSat Kit Bus (CSKB), a stacked PCB platform developed by Pumpkin Inc., is now the most widely adopted electrical interface in CubeSats [16], [26]. The CubeSat Kit Bus itself is built upon the PC/104-based electrical interface, a standard originally designed for industrial embedded systems and avionics [27]. Although the CSKB defines the form factor and mechanical interface, it does not standardise the electrical pinouts, protocols or signals. This situation has prompted numerous proposals for standardised, miniaturised CSKB alternatives, with limited success [28]–[31]. On the other hand, the community has made efforts to standardize the CSKB through initiatives like LibreSpace [32] and LibreCube [33], and by defining CubeSatspecific protocols such as SpaceCAN [34]. Nevertheless, due to the persistent lack of out-of-the-box interoperability between vendors, it remains common practice for missions to define their own custom interconnects and/or pinouts. Nevertheless, most CubeSats are equipped with the same set of subsystems: •The On-Board Computer (OBC) manages and coordinates the rest of the satellite. It executes ground station commands, ensures correct data and telemetry processing, storage and transmission, and performs housekeeping tasks [35]. •The Telemetry, Tracking and teleCommand subsystem (TT&C) is the main communication system and is usually a low-data-rate, narrowband radio system. This radio is typically restricted to the CubeSat operator’s ground station (GS), with limited or no access for third-party users [36]. •The Attitude Determination and Control System (ADCS) determines and controls the orientation (attitude) and rotation of the spacecraft. It points the satellite as required for thermal control, power generation, or for the operation of onboard instruments such as cameras and antennas. Gyroscopes, magnetometers, sun sensors and/or star trackers are usually used for orientation sensing. On the other hand, common actuators include magnetorquers and inertial wheels [37]. •The Electrical Power System (EPS) generates, stores, regulates and distributes power. The technologies most commonly used are photovoltaic panels and LiIon/Li-Po batteries. Voltage and current outputs depend on the mission [38]. •The payload is responsible for carrying out the satellite’s mission, rather than ensuring the CubeSat’s overall functionality. This subsystem can encompass all kinds of sensors, scientific instruments, expermients, communication systems, etc. 6 Development of a CubeSat payload for computing and LoRa communications 1.2. State of the Art 7 Figure 1.5 – Example CSKB board and stack. From [26] (modified). 1.2.2 Internet of Things, LPWAN and LoRa in satellite systems The Internet of Things (IoT) is widely used on Earth in various metering and monitoring domains, smart homes and smart cities. To accommodate the growing demands of IoT, Low Power Wide Area Networks (LPWAN) have emerged. LPWANs are engineered for low-cost, low-power networks, facilitating the transmission of small data packets at low bit rates over narrowband channels and over broad coverage areas [39], [40]. LoRa, a widely recognised LPWAN technology developed by Semtech Corp. and managed by the LoRa Alliance, has attracted significant attention from academia and industry thanks to its exceptional performance in environments with a low signal-to-noise ratio (SNR) [40]. LoRa itself is a proprietary layer 1 wireless protocol and modulation technique based on Chirp Spread Spectrum CSS [41]. LoRaWAN is built on top of LoRa and provides the medium access control (MAC), link, and network protocol layers [42]. In recent years, new space actors have recognised the substantial business opportunities inherent in satellite Internet of Things (IoT) and machine-to-machine (M2M) communications, largely attributable to advancements in the CubeSat ecosystem [43], [44]. Satellite IoT/M2M would enable global connectivity, which would be particularly useful in remote regions lacking infrastructure. The effectiveness of these technologies in the space environment depends on the deployment of robust wireless protocols. Consequently, LPWAN technologies such as LoRa are strong candidates [43], [45]. Satellite IoT/M2M services are usually provided by Mobile Satellite Service (MSS) operators like Inmarsat, Orbcomm, EchoStar Mobile, Iridium, Globalstar, Thuraya, and Omnispace. These services typically use frequencies below 3 GHz across both Geostationary Orbit (GSO) and Non-Geostationary Orbit (NGSO) [46]. Low Earth orbit (LEO) is an attractive platform for satellite IoT/M2M due to its ability to provide direct connectivity with simpler hardware and shorter delays compared to GSO [43]. However, the orbital characteristics of LEO inherently result in limited visibility windows and brief pass durations [47]. This challenge is being addressed through the deployment of large constellations. Nevertheless, concerns have been raised about the environmental impact of this approach, particularly with regard to astronomy and astrophotography, as well as the risks it poses to the space sector itself [48], [49]. Juan Del Pino Mena 7 8 Chapter 1. Introduction Several companies, including Eutelsat, Lacuna Space, Fossa Systems, Plan-S, Wyld Networks and Hello Space Systems have already deployed LoRa satellites in LEO [50]. Furthermore, TinyGS [51] –a global network of amateur, LoRa ground stations which decode beacons and telemetry from LoRa satellites– has attracted considerable interest. 1.2.3 Edge computing and Artificial Intelligence in CubeSats In satellite systems, edge computing involves processing data directly on the satellite itself, rather than transmitting all of the raw data to Earth for analysis. Preliminary data processing, filtering and compression on board enables the transmission of meaningful information alone, thereby reducing data volume and transmission time [52], [53]. This paradigm shift offers significant advantages for various space missions, particularly for LEO CubeSats [54], which face limitations in downlink bandwidth and short communication windows with ground stations due to their orbital characteristics [55]. Artificial Intelligence (AI), especially convolutional neural networks (CNNs), provide new capabilities for addressing complex problems such as image processing tasks in Earth observation missions. ESA’s Φ-Sat-1 (launched in 2020) and Φ-Sat-2 (2024) are pioneering examples that demonstrate the direct extraction of image features on board a CubeSat. These satellites ran a deep CNN accelerated by a COTS Intel Movidius Myriad II Vision Processing Unit (VPU) for cloud detection on acquired images in the visible and infrared spectrums, allowing the detection and discard of cloudy images and thus reducing downlink data volume [52]. Moreover, the KP Labs Intuition-1 CubeSat (2023) marks the inaugural in-orbit demonstration of an integrated neural network (NN) on a COTS Zynq UltraScale+ multiprocessor system-on-chip (MPSoC), equipped with FPGAbased hardware accelerators for AI inference [54], [56], [57]. CubeSat avionics are increasingly incorporating machine learning algorithms into critical systems such as Fault Detection, Isolation and Recovery (FDIR), to provide advance warning of potential failures by analysing telemetry [54], [58]. Conversely, edge AI could enable more autonomous operations and reduce reliance on ground control, which is essential for low-latency responses, and is particularly important for deep space missions, which experience significant communication delays [52], [54], [57]. 1.3 Scope and methodology Upon the conclusion of the first master’s thesis, a multitude of issues were identified. The modular, redundant approach adopted in the initial phase was deemed too complex given that this is the team’s first experience of satellite development, and that there are constraints in terms of funding, facilities, human resources, and know-how. Furthermore, changes to the mission objectives and constraints have motivated significant alterations to the payload, rendering the initial design obsolete. The technical details are explained in Chapter 2:Starting point, changes and updates (page 13). Instead of manufacturing and debugging the initial, flawed design, it is proposed that time, money and effort should be directed towards a safer, more methodical approach, leveraging existing designs and documentation from prior experience. In this second iteration of the project, the proposed strategy is to design, manufacture and test several chips individually on small evaluation boards (EBs). This strategy provides insight into 8 Development of a CubeSat payload for computing and LoRa communications 1.3. Scope and methodology 9 the operation of the assessed chips (e.g. specifications, configuration and programming), eliminates design uncertainties, facilitates the early identification of issues, enables the comparison of design alternatives, and ensures that the evaluated components function correctly prior to integration into a fully-fledged PCB. This approach aids both the design process of the payload and later debugging tasks. The design and testing of the evaluation boards are explained in Chapter 3:Evaluation boards (page 29). Additionally, the development of the payload’s Electrical Ground Support Equipment (EGSE) is outside the scope of this thesis and will not be pursued further. 1.3.1 Engineering Design Process The work of an engineer largely involves design. Designing involves finding solutions to unsolved problems or offering new solutions to existing ones. Creating an effective design requires creativity and the ability to make informed trade-offs. Design is the culmination of a process involving planning and effort, often achieved by breaking the challenge down into smaller, more manageable components [59]. The Engineering Design Process (EDP) represents a series of steps that engineers can follow in order to solve a problem, and is compatible with existing aerospace development methodologies [25], [60]–[62]. The development stages are shown in Figure 1.6. •Identify and define the problem. Addressed in Chapter 1 and Chapter 2. •Conduct background research to gain a comprehensive understanding of the context and state of the art, and to identify potential missteps. This step is developed in Chapter 1,Chapter 2 and Chapter 3. •Requirements engineering is the process of defining a system’s functions, behaviour and constraints. This topic is covered in Chapter 2 and Chapter 4. •Brainstorming and assessing of the feasibility of potential solutions, evaluating them in terms of their advantages and disadvantages and discarding any non-compliant. This process is discussed in Chapter 2,Chapter 4 and Chapter 5. •Specify the architectural design of the device and the technological solutions that will be employed. This point appears in Chapter 3,Chapter 4 and Chapter 5. •Development involves implementing the selected solution. This process is described in Chapter 3 and Chapter 5. •Test, verify and validate to ensure that it meets the required specifications and provides an adequate solution to the problem, while identifying any design issues. This process is started in Chapter 3 and is planned to continue in the near future. •Feedback and redesign. Feedback and redesign provide valuable information for design iterations until a fully compliant solution is achieved. This process began in the first master’s thesis, is discussed in this document in Chapter 2, and is implemented in Chapter 3,Chapter 4 and Chapter 5. •Communication of results. Results are communicated via documentation of each development step. Both master’s theses record the EDP and its results. Juan Del Pino Mena 9 10 Chapter 1. Introduction Figure 1.6 – The Engineering Design Process. 1.4 Objectives Table 1.1 presents the project’s key objectives, which highlight the thesis’s anticipated academic and professional outcomes. Obj ID Description O-1 To design an edge computing and LoRa communications payload for a CubeSat. O-2 To become familiar with the CubeSat standard at the hardware level. O-3 To become proficient in complex, mixed-signal printed circuit board designs. O-4 To gain experience with RF regulations such as ITU/RR and CEPT-ECC. O-5 To put into practice the knowledge acquired during the double Master’s degree in Telecommunications Engineering and Electronic Systems Engineering. O-6 To prove the student’s capabilities of carrying out an engineering project, and to document the entire development process. O-7 To successfully complete the master’s thesis in Telecommunications Engineering. Table 1.1 – Principal top-level objectives of this project. 1.5 Project tasks timeline Figure 1.7 illustrates the duration of each task in this Master’s thesis. The initial phase was dedicated to foundational groundwork and redefining requirements, alongside radio link simulations for feasibility analysis, and designing the testing to be carried out on the evaluation boards, in order to establish a development baseline. The project then transitioned to the development of the evaluation boards, encompassing circuit design, PCB development and fabrication, followed by checks and testing. Payload development started as the design of the evaluation boards was finishing. Meanwhile, the radio link simulations were updated and revised for this document. 10 Development of a CubeSat payload for computing and LoRa communications 1.5. Project tasks timeline 11 Christmas and exams period Summer Summarised panning of the Master's Degree in Eectronic Systems MUISE) master's thesis, 12 ECTS August 2023 2024 JuySeptember W1 W2 W3 W4 October W1 W2 W3 W4 November W1 W2 W3 W4 December W1 W2 W3 W4 January W1 W2 W3 W4 February W1 W2 W3 W4 March W1 W2 W3 W4 Apri W1 W2 W3 W4 May W1 W2 W3 W4 June W1 W2 W3 W4 W1 W2 W3 W4W4W1 W2 W3 September W4W1 W2 W3 Summer August W4W1 W2 W3 Xmas Panning of the Master's Degree in Teecommunications Engineering MUIT) master's thesis, 30 ECTS 2024 December W2 W3 W4 January W1 W2 W3 W4 February W1 W2 W3 W4 March W1 W2 W3 W4 Apri W1 W2 W3 W4 May W1 W2 W3 W4 Juy W4 June W1 W2 W3 W4 W1 W2 W3 2025 Summer August W4W1 W2 W3 September W4W1 W2 W3 DANA October November W1 W2 W3 W4 W1 W2 W3 W4 W1 Feasibiity report Circuits - groundwork Circuit design and documentation Design review Defense prep. TFM proposa writing Writing the master's thesis report Requirements defined Feasibiity anaysis and research Systems definition Radio Link simuations and documentation MUISE master's thesis defense Simuations report MUISE master's thesis submission Iteration 1 design finished Writing the master's thesis report Defense preparation MUIT master's thesis submission TFM proposa writing PCB deveopment and documentation Groundwork: research, feasibiity anaysis, requirements, system re-definition. Evauation Boards: Circuit design, PCB deveopment, and PCB paneing. EB test design EBs sent for fabrication Radio ink simuations Radio ink simu. Payoad: Circuit design and documentation Payoad: PCB deveopment and documentation Iteration 2 design finished EB fab. and check ESAFYSDB sat proposa deadine EBs received EB test exec. MUIT master's thesis defense Figure 1.7 – Gantt chart of the complete timeline of the project. Juan Del Pino Mena 11 12 Chapter 1. Introduction 1.6 Report structure The chapters form the main body of the document: 1. Chapter 1:Introduction.The initial chapter establishes a foundation for the subject matter, and delineates the project’s objectives and motivations. 2. Chapter 2:Starting point, changes and updates.This chapter summarises the project’s development status prior to this Master’s thesis, providing insight into the changes to the mission that have prompted modifications to the payload, defining system constraints. It also presents an updated study of the Earth-satellite communications link. 3. Chapter 3:Evaluation boards.This chapter provides a comprehensive overview of the rationale behind, the design of, the fabrication of, and the testing of the evaluation boards used to evaluate and experiment with specific components that will be incorporated into the final payload PCB. 4. Chapter 4:Specification.This chapter outlines the requirements on which the subsequent design will be based. It will propose a hardware architecture and select the most relevant components. 5. Chapter 5:Design.This chapter provides a comprehensive overview of the circuit and PCB design, taking into account manufacturing considerations. 6. Chapter 6:Conclusion and future lines.This chapter concludes the thesis by reviewing the milestones achieved and the issues that arose during development. It also establishes future work and suggests improvements. The appendices provide supplementary material: A. Appendix A:Sustainable Development Goals.This appendix demonstrates the alignment of this project with the Sustainable Development Goals. B. Appendix B:Project costs.A detailed account of the project budget. C. Appendix C:Circuit schematics.The complete schematics of all the boards. D. Appendix D:Printed Circuit Boards.Includes prints of PCBs. E. Appendix G:Receiver RF budget spreadsheets.Provides additional parameters of the receiving stage of the payload. Owing to the responsibilities associated with the position at Pluton UPV, the following aspects of the CubeSat have been developed as by-products of this master’s thesis: F. Appendix E:Interfaces, connections and pin allocation.This appendix includes the electrical interface definition of each subsystem, the interconnection between them, as well as their CubeSat Kit Bus pin allocation. G. Appendix F:CubeSat antenna measurements and tuning.Attaches the satellite’s antenna measurements and tuning process. 12 Development of a CubeSat payload for computing and LoRa communications Chapter 2 Starting point, changes and updates This section provides insight into the precedents and the changes to the mission objectives that have, in turn, prompted modifications to the payload architecture. 2.1 The first design iteration The first master’s thesis in Electronic Engineering [1] focused on designing the first hardware iteration of the LoRa payload for the Estigia mission. This payload comprised two mixed-signal, multi-layer printed circuit boards. An Electrical Ground Support Equipment (EGSE) was also designed as a test and development platform (Figure 2.1). The thesis covered the project’s motivation, methodology, requirements analysis and initial design. The requirements were defined based on the mission’s objectives and operational constraints. To assess the feasibility of the communications system, exhaustive simulations of the Earth-satellite radio link were carried out. The process was meticulously documented, forming the basis for this second master’s thesis. The second phase was intended to address the manufacturing and assembly of the hardware, as well as the programming, debugging, testing, verification, validation and gathering of feedback for further design iterations. However, the design was finally not manufactured due to the abundance of issues identified during its development, which indicated a low probability of the system functioning as intended. Figure 2.1 – Render of the payload’s first iteration, including modules (daughterboards, red), carrier (motherboard, blue) and EGSE (test board, green) boards. Extracted from the first master’s thesis [1]. 13 20 Chapter 2. Starting point, changes and updates 2.4.4.1 Study for the SX126x/7x nodes and the SX1301 gateway IC The SX126x/7x and SX1301 chips tolerate a maximum packet frequency drift of [87]: Δ𝑓d,pkt,max = 𝐿·𝐵 3·2SF (2.1) where 𝐿=16 if the Low Data Rate Optimization (LDRO) flag is enabled, and 𝐿=1 otherwise. To assess if the limit is exceeded, the overall change in frequency from the start to the end of a packet is calculated [45]: Δ𝑓d,pkt(𝑡)=𝑓d(𝑡+𝑇pkt)−𝑓d(𝑡)(2.2) where 𝑓d(𝑡)is the Doppler frequency shift and𝑇ptk is the duration of a LoRa PHY frame transmission, called Time-on-Air (ToA) in the LoRa jargon. Figure 2.6 illustrates and explains the structure of a LoRa frame. The ToA is the sum of the duration of the preamble, start frame delimiter (SFD) and data symbols [89]: 𝑇pkt =𝑇pre +𝑇SFD +𝑇data 𝑇pkt =𝑛pre +2+2.25 +𝑛data·𝑇s (2.3) where the symbol period is 𝑇𝑠=2SF/𝐵and the number of data symbols is [90], [91]: 𝑛data =8+max ceil 8·𝑛payl −4·SF +8+16 +20 ·𝑏H 4(SF −2·𝑏LDRO)·(𝑛CR +4),0(2.4) where the 𝑛payl is the payload length, 𝑛CR =[1,4]is the coding-added redundancy bits, 𝑏H={0,1}indicates wether the header is present or not, and 𝑏LDRO ={0,1}indicates if Low Data Rate Optimization (LDRO) is active (mandatory for 𝑆𝐹 ≥11). (a) The LoRa PHY frame structure comprises a header, a payload and an optional 2-byte CRC. The header begins with the preamble and start frame delimiter (SFD) for receiver synchronization. The next 8-bit field specifies the payload’s length, a CRC bit indicates the presence of the payload CRC, a 3-bit field stores the coding rate (CR), and ends with an 8-bit header CRC. The payload size ranges from 0 to 255 bytes, although is usually reduced to comply with the channel utilisation regulations [81] (Table 2.2), or to mitigate the frequency drift. Based on [42], [75], [90]. (b) Spectrogram of a LoRa frame with the main parts of the frame identified. Simulated with [92], [93]. Figure 2.6 – LoRa PHY frame structure and spectrogram of a LoRa frame. 20 Development of a CubeSat payload for computing and LoRa communications 2.4. Updated radio link budget simulations 21 2.4.4.2 Study for the LR11xx nodes and the SX1302 gateway IC The newer LR11xx series of nodes and the SX1302 gateway chips tolerate maximum frequency drift for each symbol rather than for the entire LoRa packet [87]: Δ𝑓d,sym,max = 𝐵 10 ·2SF (2.5) The change in frequency during a symbol is defined similarly as before: Δ𝑓d,pkt(𝑡)=𝑓d(𝑡+𝑇s)−𝑓d(𝑡)(2.6) where 𝑓d(𝑡)is the Doppler frequency shift and 𝑇s=2SF/𝐵is the symbol period. A symbol period is much shorter than a frame, making these transceivers more resistant to the Doppler rate and easier to analyse, as there are fewer variables involved. 2.4.4.3 Results and discussion Table 2.4 gathers the time-on-air and maximum allowed Doppler rate for both symbols and complete frames, for different spreading factors. SF values below 10 are not evaluated since they are highly unlikely to reach the satellite (see section 2.4.5:Power budget). Higher SFs cause the transceiver to have poorer immunity to frequency drifts. Figure 2.7 shows the Doppler rate during packet transmission for the highest and lowest orbit altitudes, with varying payload sizes and spreading factors. On the other hand, Figure 2.8 depicts the Doppler rate during the transmission of both LoRa packets and individual symbols, at various orbit heights while varying the spreading factor. Increasing the frequency from 438 MHz to 870 MHz has caused a significant increase in Doppler rate compared with previous analyses [1]. In both figures it can be seen that as ToA increases (due to larger payloads and/or SFs), the total frequency drift also increases. Moreover, a lower orbit results in a higher orbit velocity and thus greater Doppler. For all the reasons given above, the Doppler rate limits are almost always exceeded, forcing the use of lower SFs and/or very short payloads, while favouring high orbits. This has significant drawbacks in terms of the power balance, since lower SFs result in poorer receiver sensitivity and high orbits suffer greater propagation losses (section 2.4.5). Even so, the results for chips with symbol-based immunity to Doppler (LR11xx and SX1302) are considerably better than those packet-based (SX126x/7x). Regardless of whether the 862 −870 MHz band is ultimately used, the results presented in this document and the previous one [1] suggest that the LoRa ground stations should use the LR11xx transceivers in lieu of the SX12xx to avoid Doppler effect issues. BW SF LDRO Bitrate Symbol period ToA Limit packet Doppler rate Limit symbol Doppler rate 125 kHz 10 On 976 bps 8.2 ms 2.79 s 651 Hz 12 Hz 11 On 537 bps 16.4 ms 5.00 s 325 Hz 6 Hz 12 On 292 bps 32.8 ms 9.02 s 168 Hz 3 Hz Table 2.4 – Time-on-air and maximum allowed Doppler rate for different spreading factors. The packet has 8 preamble symbols, explicit header, coding rate 4/5, and a payload of 255 bytes. Juan Del Pino Mena 21 22 Chapter 2. Starting point, changes and updates Figure 2.7 – Analysis of the Doppler rate for LoRa packets when varying the packet payload size, SF and orbit height. Longer ToAs are much more susceptible to the Doppler rate. Figure 2.8 – Analysis of the Doppler rate for LoRa packets and symbols when varying the packet payload size, SF and orbit height. The left column plots the Doppler rate for a 255-byte payload frame, while the right column plots the Doppler rate for a single symbol. 22 Development of a CubeSat payload for computing and LoRa communications 2.4. Updated radio link budget simulations 23 2.4.5 Power budget A power budget is an accounting of all the gains and losses encountered in the transmission of a signal. The power budget for Earth-space communication systems has been considerably studied, including the cases of NB-IoT and LoRa [43], [86], [94]–[96]. Relevant parameters for the power budget, including transmission power, receiver sensitivity, and insertion losses, are summarised in Table 2.1. 2.4.5.1 Sensitivity The sensitivity of a receiver depends on [97], [98]: 𝑆=10 ·log10(𝑘𝑇 ) + 10 ·log10(𝐵) + NF +SNR𝑂(2.7) where 10 ·log10(𝑘𝑇)is the thermal noise density (−174 dBm/Hz at 𝑇=298 K), 𝐵is the bandwidth, NF is the system noise figure and SNR𝑂is the required output SNR. The sensitivity criterion for LoRa is defined as the minimum signal power required to achieve a packet reception rate (PRR) of at least 90 % with a 32-byte payload [40]. Under these conditions, the sensitivity of typical LoRa transceivers is specified as −137 dBm with a required SNR of −20 dB, using SF 12 and 𝐵=125 kHz [74], [75]. Solving for NF in Equation 2.7 yields a noise figure of 6 dB for a typical LoRa transceiver. This figure, and therefore the sensitivity, can be vastly improved by including a lownoise, high-gain LNA early in the receiver chain, as shown by the Friis formula [98]: NFsys =10 ·log 𝐹sys=10 ·log 𝐹1+𝐹2−1 𝐺1 +𝐹3−1 𝐺1𝐺2 +...+𝐹𝑛−1 𝐺1𝐺2. . .𝐺𝑛−1(2.8) For this reason, a high-performance LNA has been incorporated into the CubeSat’s payload, which, as will be seen in Chapter 5:Design (page 57), improves the overall NF of the reception chain to a maximum of 3 dB. Solving again for 𝑆in Equation 2.7 with the new noise figure yields a sensitivity of −140 dBm in the satellite. 2.4.5.2 Attenuation Table 2.5 lists sources of external attenuation. The most significant contributor is Free-Space Path Loss (FSPL), the order of 150 dB. The 870 MHz carrier suffers a 6 dB increase in FSPL compared to 438 MHz [1]. The simulation employs the ITU-R P.618 model [99] to estimate the expected atmospheric losses near Valencia, setting exceedances set to the model’s worst-case values. An exceedance occurs when atmospheric conditions cause losses to pass a given threshold. Atmospheric losses are small for sub-GHz bands, amounting to 0.770 dB (see Table 2.5). Radio waves undergo Faraday polarisation rotation under the influence of the ionosphere. Using circularly polarised antennas at both ends of the link avoids rotational losses [55]. The chosen 3 dB loss represents the loss of one of the polarisation components, since, at the time of writing, the ground antenna is circularly polarised, whereas the satellite’s antenna is linear. The total losses ranges from 154.4 dB to 157.3 dB at 𝛿=15◦elevation. Juan Del Pino Mena 23 24 Chapter 2. Starting point, changes and updates Attenuation type Worst-case value (dB) Gaseous attenuation 0.18 Cloud and fog attenuation 0.01 Rain attenuation 0.02 Tropospheric scintillation attenuation 0.56 Polarization loss 3.00 Free-Space Path Loss 𝑓=870 MHz ℎ=450 km,𝛿=15◦,𝑆=1295 km 153.50 ℎ=400 km,𝛿=15◦,𝑆=1175 km 152.70 ℎ=350 km,𝛿=15◦,𝑆=1055 km 151.70 ℎ=300 km,𝛿=15◦,𝑆=925 km 150.60 Table 2.5 – Summary of worst-case external attenuation in the power budget. Expected atmospheric losses near Valencia with exceedances set to the model’s worst-case values. 2.4.5.3 Transmission power As can be seen in Table 2.2, the short-range devices (SRD) band is subject to strict transmission power limitations on Earth, reducing the effective radiated power (ERP) from 30 dBm (as considered in the simulations of the first master’s thesis) down to 27 or 14 dBm, depending on the subband. In addition, commercial LoRa modems can output a maximum of 22 or 14 dBm, depending on the model [74], [75]. On the other hand, the power flux density (PFD) on Earth’s surface must not exceed −142 dB(W/m2·4 kHz)to protect terrestrial services [50]. The PFD is calculated as: PFD =EIRP +10 ·log10 (4 kHz/𝐵)−𝐿𝑇(2.9) where EIRP is the CubeSat’s effective isotropic radiated power, and 𝐿𝑇is the total loss. The left-hand plot of Figure 2.9 shows that the PFD limits are exceeded if the satellite emits the maximum power for which it is designed (33 dBm). Therefore, the transmit power must be limited according to the orbit height, as shown in the right-hand plot of Figure 2.9. This will affect the outcome of the power balance and signal-to-noise ratio. Figure 2.9 – PFD for the satellite’s maximum output power, and after limiting it accordingly. 24 Development of a CubeSat payload for computing and LoRa communications 2.4. Updated radio link budget simulations 25 2.4.5.4 Power budget results Once all the contributors have been identified, the power balance is performed. Compliance is achieved when the received signal strength exceeds the sensitivity threshold. As this is a conservative balance, no margin has been established, as it would be too restrictive. As it can be seen in Figure 2.10, although communications are assured in the downlink, the uplink’s limited transmission power greatly restricts communication time, a limitation that cannot be fully compensated for by the satellite’s improved sensitivity. Figure 2.10 – Received signal power in uplink and downlink. 2.4.6 Signal-to-noise ratio budget The signal-to-noise ratio (SNR) quantifies the power of a desired signal relative to the level of background noise. The SNR in the studied wireless channel is defined as [100]: SNR =EIRP +G/T −𝐿𝑇−10 ·log10(𝑘·𝐵)(2.10) where the EIRP is the effective isotropic radiated power, 𝐿𝑇is the total loss and G/T is the antenna-gain-to-noise-temperature ratio [100]: G/T =𝐺rx −NF −10 ·log10 𝑇0+(𝑇𝐴−𝑇0)·10NF/10(2.11) where 𝐺rx is the receive antenna gain, and 𝑇0is the ambient temperature and 𝑇𝐴is the antenna temperature. Relevant parameters for the SNR budget are listed in Table 2.1. As with sensitivity, the criterion is defined as the minimum signal-to-noise ratio required to achieve a packet reception rate (PRR) of at least 90 % with a 32-byte payload [40]. The threshold depends on the selected SF and bandwidth. For reference, the limit is −20 dB with SF 12 and 𝐵=125 kHz [74], [75]. As it can be seen in Figure 2.11, the results are analogous to those of the sensitivity. The signal-to-noise ratio complies with margin in the downlink, even with the PFD transmission power limits in place. However, the limited transmission power of the mini-ground stations has a detrimental effect the SNR in the uplink, thereby restricting communication time, specially using higher spreading factors. Juan Del Pino Mena 25 26 Chapter 2. Starting point, changes and updates Figure 2.11 – Signal-to-Noise Ratio (SNR) in uplink and downlink. 2.5 Discussion As explained in section 2.4.1 (page 16), the change from the 435 −438 MHz band to 862 −870 MHz was motivated by the need to avoid collisions between the two onboard radio systems. This change also has clear advantages in terms of hardware design: as this band is widely used on Earth, RF designs are easier to implement thanks to the availability of miniaturised, high-performance RF components. And, unlike the 435 MHz one, there are also gateway reference designs from Semtech operating in this band. However, in terms of link balance, the change is highly detrimental: both the power balance and the SNR have worsened due to the increased 6 dB of FSPL, and the Doppler effect exhibits a concerning increase in absolute drift and rate. Furthermore, constraints on power emission on Earth make it challenging to comply with the uplink power budget. A concerning dichotomy also exists: at the apogee, when the link conditions are more favourable in terms of power balance and SNR, the Doppler rate makes communication unfeasible in many cases. Furthermore, the Doppler effect is weaker in higher orbits because the relative speed between observers is reduced, but the power balance is worse. What measures can be taken to address this issue? Firstly, as stated in section 2.4.4.3 (page 21), as a partial solution is to use the LR11xx transceivers in the mini-ground stations due to their enhanced Doppler immunity. It is also proposed to employ high minimum elevation angles, of around 30−40◦. While this would greatly restrict visibility time, improved link conditions would allow lower spreading factors to be used, significantly increasing the data rate. This would reduce transmission times considerably and thus greatly mitigate packet loss due to Doppler. Similarly, using more but shorter frames would reduce the packet loss probability, albeit at the expense of increased overhead. Furthermore, low elevations should be avoided since, apart from the greater communication distance, they tend to be affected by shadowing, fading, multipath, interferences and noise [101], whose effects were not studied in this work. What’s more, many of the most promising mini-ground stations’ antenna designs explored in [7] have a gain greater than zero between 40◦and 140◦. 26 Development of a CubeSat payload for computing and LoRa communications 2.5. Discussion 27 Moving on to another topic, another question that may arise is: why a commercial off-the-shelf (COTS) single-board computer (SBC) module was chosen for the processing unit of the payload, yet not a COTS LoRa gateway module as the radio hardware? There are several reasons for this: Firstly, because most gateway designs follow the cost-saving principles of the reference designs [64]–[67]. These include a 1-to-3 power splitter implemented as a Tjunction (see Figure 2.12a), and an all-in-one RF front-end IC that serves as a low-noise amplifier (LNA), power amplifier (PA), and RF switch. The T-junction splitter causes impedance mismatches and reflections, while the RF front-end IC has mediocre specifications [102]. Moreover, avoidable insertion losses in the receiving path cause the cascade noise figure (NF) of the receiver –and therefore its sensitivity– to deteriorate. The reference baluns for the LoRa modems are also not well balanced, neither in magnitude nor phase. These aspects are discussed in section 5.1.3.1:RF front-end (page 59). Secondly, because RF performance could not be improved externally. Since the designs are half-duplex, there is only a single RF input/output port, so it is not feasible to add external amplifiers. To have control over signal quality, it is necessary to engage with the low-level RF design. This master’s thesis proposes a design that adds a standalone LNA and PA, giving it an edge in the link budget. And finally, because gateways on modules typically use a U.FL/IPEX micro-coaxial connector (Figure 2.12b). This connector is designed for consumer electronics, and is not mechanically suitable for space conditions. It is a weak plug, only rated for a few dozen mating cycles. It is also likely to become damaged or disconnected due to the extreme vibrations experienced during launch, or due to thermal cycling. (a) 1-to-3 T-junction RF splitter in a reference design [66]. The impedance of all traces is 50 Ω. (b) U.FL/IPEX micro-coaxial connector for RF I/O in Nebra’s open source gateway module [103]. Figure 2.12 – Details of some commercial LoRa gateway modules. Juan Del Pino Mena 27 28 Chapter 3 Evaluation boards An evaluation board is a printed circuit board (PCB) that provides engineers with a platform on which to assess the performance and suitability of components, compare different solutions and develop and debug software. Evaluation boards typically include the main component for which they are designed, as well as supporting circuitry, such as voltage regulators, clocks, decoupling capacitors, and communication interfaces. 3.1 Design overview The evaluation boards (EBs) are described below. Prints and renders of the PCBs can be found on the following pages. The schematics are not commented on here, since they mostly follow the reference designs and do not require much explanation. The complete schematics can be found in Appendix C:Circuit schematics (page 113); and a description of similar circuits is present in section 5.1:Schematics (page 57). 1. Two LoRa transceivers characterisation boards (Figure 3.1) will be used to determine the input and output impedances of the transceivers, crucial parameters that have not been specified by the manufacturer (see section 5.1.3.1:RF frontend (page 59)). One board contains a Semtech SX1250 modem, which is used in the gateway for transmission and reception as radios A and B. The other board contains an SX1261 modem, which is used for listen-before-talk (LBT) only. Each boards contains a modem and a high-precision 32 MHz TCXO. The RF traces are designed to achieve a 50 Ω impedance and feature tapers to couple with the modems’ pads. The RF traces are spaced as far apart as possible to avoid coupling. The PCBs are compact while still making test points and interfaces accessible. 2. A de-embedding kit for the LoRa EBs (Figure 3.4) composed of an input path through, open, short and match (TOSM) and an output path through kit. The TOSM board replicates the shape and copper distribution of the LoRa EBs and to be as faithful as possible to their electrical properties. The board has two quasi identical faces. The front one has parasitic traces near the RF traces, whereas the bottom face does not. It is important to note that Ansys SIwave simulations with and without parasitic traces revealed no differences for sub-1 GHz frequencies. The RFO through simply replicates the RF output structure of the SX1250, comprising the trace and the PA bias inductor. 3. A power electronics evaluation board (Figure 3.7) combines a Texas Instruments TPS62912 low-noise DC/DC converter, a TPS259474 eFuse and an INA232 power monitor on the same PCB for convenience and cost savings. The designs are similar to the circuits implemented in the first iteration of the payload. The boards contain resistors and jumpers that can be used to adjust the devices’ settings. Each stage has a jumper to connect its output to the input of the next stage, enabling them to be evaluated together. 29 36 Chapter 3. Evaluation boards (a) Too much solder paste (TPS259474x). (b) Insufficient solder paste (TPS62912). (c) Stencil misalignment (SX1250). (d) Solder balling (TPS62912). Figure 3.13 – Inspection of solder paste deposition and solder problems. (a) (INA232). (b) (TPS259474). (c) (TPS62912). (d) (SX1250). Figure 3.14 – Inspection of solder joints with a microscope. 36 Development of a CubeSat payload for computing and LoRa communications 3.2. Fabrication 37 (a) EB-SX1250 and EB-SX1261. (b) De-embedding kit. (c) EB-POWER. Figure 3.15 – Soldered boards. Juan Del Pino Mena 37 38 Chapter 3. Evaluation boards 3.2.3 Bring-up The Arduino MKR WAN 1300 development board is used to configure the EB-SX12xx boards. As the EB-SX12xx’s power consumption is far below the MKR WAN 1300’s 600 mA limit, it can be powered entirely by its internal 3.3 V regulator [110]. It is important to use 3.3 V logic to avoid damaging the SX12xx chips. The SX126x LoRa receiver example from the SX12xx open source LoRa library for Arduino [111] was used as the basis for the test firmware. This firmware is also compatible with the SX1250, as they have identical internal logic. A digital multimeter was used to measure all voltage rails, which were found to be at their nominal voltages. Several signals were probed with a Rohde & Schwarz RTC1002 oscilloscope to check whether the LoRa modem was alive. These signals included the 32 MHz oscillator and the SPI Master Input Slave Output (MISO) data signals (Figure 3.16). Once the manufacturing process has been completed successfully and both LoRa boards have been brought up, the next stage is to initiate the testing procedure. (a) Setup for the board bring-up. (b) The 32 MHz clock (the waveform is distorted due to the probe’s load). (c) Internal DC/DC converter switching at 3 MHz. The IC’s SMPS is working properly. (d) Activity on the SPI clock (Ch.1) and MISO (Ch.2). The chip responds to SPI commands. Figure 3.16 – Probing of some signals from the SX1250 evaluation board. 38 Development of a CubeSat payload for computing and LoRa communications 3.3. Tests 39 3.3 Tests 3.3.1 Calibration and de-embedding Calibration is a pre-measurement setup, performed before connecting the device under test (DUT) to correct the measurement equipment’s systematic errors using known, highly accurate physical standards with well-defined electrical characteristics [112]. In this case, the used calibration kit is the Agilent 85052C Short-Open-Load-Thru (SOLT) [113]. Calibration defines its reference measurement plane to a defined physical location, in the studied case, the end of the cables of the vector network analyser (VNA). However, when the DUT is an integrated circuit, the test fixture itself may contain various transitions and interconnects between the measurement plane established by the calibration and the DUT itself that will alter the measurements. De-embedding of the test fixture is therefore necessary in this case [114]. De-embedding refers to the removal of unwanted effects that a test fixture can have on the measurement of a device under test. Unlike calibration, de-embedding is a postmeasurement process [114]–[116]. No well-known standards are used for de-embedding, either because they cannot exist, or are not practical to implement. Instead, de-embedding uses several dummy structures that help remove unwanted test fixture effects, but does not provide enough information to deduce a complete error box network like those obtained using calibration. De-embedding uses the S-parameters of said dummy structures to subtract their contribution from the total measured response [114]–[116]. In the measurements performed in this work, the widely used open-short deembedding method was used. The accuracy of this procedure depends on the validity of the assumption that the parasitics of the test fixture are a combination of parallel conductances and series impedances, which is generally applicable to the case study. The detailed procedure is described in the scikit-rf documentation [115], [116]. Figure 3.17 – Reference plane after calibration and after de-embedding. Extracted from [114]. Juan Del Pino Mena 39 40 Chapter 3. Evaluation boards (a) Measurement setup. (b) TOSM kit. (c) RFO kit. Figure 3.18 – Photos taken during the measurements. 40 Development of a CubeSat payload for computing and LoRa communications 3.3. Tests 41 3.3.2 RF tests definition and results These tests make use of the following equipment: 1. EB-SX1250 board. 2. Arduino MKR WAN 1300 development kit, to configure the SX1250. 3. Rohde & Schwarz ZNB, 20 GHz, two-port VNA. 4. Agilent 85052C Short-Open-Load-Thru (SOLT) calibration kit. 5. An SMA torque wrench. 6. PC, for programming the Arduino and retrieving measurements from the VNA. The test assumes that the VNA has reached its nominal operating temperature, that calibration has been performed using the 85052C kit, and that all RF connections are tightened using an SMA torque wrench. The test firmware was created using the SX126x receiver example (also compatible with the SX1250) from the SX12xx lora library [111]. 3.3.2.1 Characterisation of the de-embedding kit The four S-parameters of each Through, Open, Short and Match in the TOSM kit were measured, for the de-embedding of S-parameters in the subsequent measurements. 100.0 250.0 400.0 550.0 700.0 850.0 1000.0 50 40 30 20 10 0 Magnitude (dB) Load Calkit, S11 Calkit, S12 Calkit, S21 Calkit, S22 100.0 250.0 400.0 550.0 700.0 850.0 1000.0 50 40 30 20 10 0 Magnitude (dB) Open 100.0 250.0 400.0 550.0 700.0 850.0 1000.0 Frequency (MHz) 50 40 30 20 10 0 Magnitude (dB) Short 100.0 250.0 400.0 550.0 700.0 850.0 1000.0 Frequency (MHz) 50 40 30 20 10 0 Magnitude (dB) Thru Figure 3.19 – S-parameters of the RF input de-embedding kit. Juan Del Pino Mena 41 42 Chapter 3. Evaluation boards 100.0 250.0 400.0 550.0 700.0 850.0 1000.0 Frequency (MHz) 50 40 30 20 10 0 Magnitude (dB) S-parameters of the RFO thru sparam, S11 sparam, S12 sparam, S21 sparam, S22 Figure 3.20 – S-parameters of the RF output de-embedding kit. 3.3.2.2 Test RF.1: SX1250 LNA input impedance This test consists on the measurement of the source impedance of the differential low-noise amplifier (LNA) of the SX1250 LoRa modem. The test procedure is the following: 1. The SX1250 shall be in the receiving state and configured with best sensitivity. 2. Take measurements for all four S-parameters of the input ports of the EB-SX1250. 3. Perform the de-embedding using the Open-Short method [115]. The LNA impedance is the double of the measured single-ended impedance, id est: 𝑍LNA =2· (10.3−𝑗59.9 Ω)=20.6−𝑗119.8 Ω (@ 866 MHz)(3.1) Frequency Impedance M1 436.6 MHz 11.3 -184.6j Ohms M2 865.9 MHz 6.1 -66.3j Ohms M3 436.6 MHz 33.0 -163.3j Ohms M4 865.9 MHz 10.3 -59.8j Ohms M5 436.6 MHz 33.4 -164.0j Ohms M6 865.9 MHz 10.3 -59.9j Ohms M7 436.6 MHz 33.4 -164.0j Ohms M8 865.9 MHz 10.3 -59.9j Ohms 10.0 25.0 50.0 100.0 250.0 10.0j 25.0j 50.0j 100.0j 250.0j -10.0j -25.0j -50.0j -100.0j -250.0j 0.0 M1 M2 M3 M4 M5 M6 M7 M8 SX1250 reflection S-parameters (de-embedded) SX1250 OFF, S11 SX1250 SF12, S11 SX1250 SF11, S11 SX1250 SF10, S11 Figure 3.21 – Test results for the SX1250’s LNA source impedance. 42 Development of a CubeSat payload for computing and LoRa communications 3.3. Tests 43 3.3.2.3 Test RF.2: SX1261 LNA input impedance The measurement is identical to the previous one, but this time it is taken with the EB-SX1261. Although there is no reference impedance for the SX1261, it is assumed to be similar to that of the SX1250 because the two chips are similar. The procedure is as described in the previous section (3.3.2.2). The measured LNA impedance is identical to the previous result. The impedance did not change when the spreading factor was modified in either case. 𝑍LNA =2· (10.6−𝑗59.9 Ω)=21.2−𝑗119.8 Ω (@ 866 MHz)(3.2) Frequency Impedance M1 436.6 MHz 11.8 -185.8j Ohms M2 865.9 MHz 6.3 -66.5j Ohms M3 436.6 MHz 34.9 -166.1j Ohms M4 865.9 MHz 10.6 -60.6j Ohms M5 436.6 MHz 34.4 -163.9j Ohms M6 865.9 MHz 10.6 -59.9j Ohms M7 436.6 MHz 34.5 -163.8j Ohms M8 865.9 MHz 10.7 -59.9j Ohms 10.0 25.0 50.0 100.0 250.0 10.0j 25.0j 50.0j 100.0j 250.0j -10.0j -25.0j -50.0j -100.0j -250.0j 0.0 M1 M2 M3 M4 M5 M6 M7 M8 SX1261 reflection S-parameters (de-embedded) SX1261 OFF, S11 SX1261 SF12, S11 SX1261 SF11, S11 SX1261 SF10, S11 Figure 3.22 – Test results for the SX1261’s LNA source impedance. 3.3.2.4 Test RF.3: SX1250 PA output impedance Measurement of the optimum load impedance of the power amplifier (PA) of the SX1250 modem. The RF output is single-ended. The procedure is as follows: The test procedure is the following: 1. The SX1250 shall be in the transmitting state and its PA biased and set to output a desired RF power. 2. Take measurements of the 𝑆11 parameter of the output port of the EB-SX1250. 3. Perform the de-embedding using the RFO kit. Unfortunately, the measurement method used for this test is inadequate, so de-embedding cannot be performed. The Through kit is not suitable for these kinds of measurements. Instead, an OpenShort should be used [115], [116]. The measured impedance did not change when the output power or the spreading factor was modified. Figure 3.23 shows the results without de-embedding for reference purposes. Juan Del Pino Mena 43 44 Chapter 3. Evaluation boards Frequency Impedance M1 867.7 MHz 1.2 -22.0j Ohms M2 867.7 MHz 4.0 -3.1j Ohms M3 867.7 MHz 4.0 -3.1j Ohms M4 867.7 MHz 4.0 -3.1j Ohms 10.0 25.0 50.0 100.0 250.0 10.0j 25.0j 50.0j 100.0j 250.0j -10.0j -25.0j -50.0j -100.0j -250.0j 0.0 M1 M2 M3 M4 SX1250 RFO S-param, NOT de-embedded SX1250 RFO (OFF), S11 SX1250 RFO (0 dBm), S11 SX1250 RFO (10 dBm), S11 SX1250 RFO (14 dBm), S11 Figure 3.23 – Test results for the SX1250’s PA output impedance (not de-embedded). 3.3.3 Power tests definition These tests were not fully defined or carried out, but are included in this document for future reference. These measurements make use of common equipment: 1. An EB-POWER board. 2. A microcontroller development kit, to read and write configuration signals. 3. A configurable bench power supply. 4. An oscilloscope, to inspect waveforms and measure noise and ripple. 5. Several power resistor loads, e.g.: 1, 2, 5, 10, 50, 100, 200 and 500 Ω. 3.3.3.1 Test PWR.1: Evaluation of the TPS62912 DC/DC converter Power the TPS62912 with 5 V. Load it with a 500 Ω resistor. Measure the noise and ripple at the input and output voltages. Analyse its spectral content. Change the load current demand. Report overvoltage and undervoltage behaviour. Repeat the tests with different configurations, such as switching frequency, spread spectrum frequency modulation (SSFM), output voltage, and so on. 3.3.3.2 Test PWR.2: Evaluation of the INA232 power monitor Power the INA232 with 5 V. Load it with a 500 Ω resistor. Measure the voltage drop in the current-sense resistor while the INA232 is set to monitor the current. Change the load current demand. Compare the actual current with the one reported by the INA232. 3.3.3.3 Test PWR.3: Evaluation of the TPS259474 eFuse Power the TPS259474 with 5 V. Load it with a 500 Ω resistor. Measure the turn-on and turn-off times of the eFuse. Report overvoltage and undervoltage behaviour by varying the input voltage. Compare the measured currents with the analog output (ILM). Change the load to simulate different current demands, and to trip the set overcurrent protection. Short the output to evaluate the eFuse response. 44 Development of a CubeSat payload for computing and LoRa communications 3.4. Discussion 45 3.4 Discussion This chapter has explained the purpose of evaluation boards, how they are designed, manufactured, and tested. However, it is evident that the testing campaign has not proceeded as hoped. There is no output impedance data for any LoRa chip, and the measurements could not be de-embedded because the RFO de-embedding kit is not suitable, so the measurements cannot be compared to the estimates (section 5.1.3.1 (page 59)). Also, the results from the input impedance do not match the manufacturer’s figure for the SX1250 at 868 MHz, 74 +𝑗134 Ω [117]. However, due to the lack of a precise specification, it is unclear what type of impedance this could be (single-ended, differential, optimal noise, optimum gain, maximum power transfer, etc.). The lack of specifications means that the experimental results cannot even be compared to the manufacturer’s figure. Semtech’s documentation lacks the data required for the design process. Instead, they assume that designers will either copy the reference circuit and use the default firmware, or characterise and reverse-engineer the transceivers and firmware themselves [69], [118], [119]. Semtech was approached regarding these concerns, but no response was received. It is hypothesised that either the relevant data is disclosed only to industry partners, or the manufacturer has not fully characterised their devices in the first place. It is doubtful that the measured impedances are useful. The optimal noise source impedance and the maximum gain source impedance are not the same and are rarely equal [120]. Similarly, the maximum output power load impedance and the maximum power transfer load impedance are not the same either [121]. Determining the optimal impedances requires a complex set of analyses that could not be carried out due to lack of time and specialised equipment, but are described below for documentation purposes. 3.4.1 Optimum PA load impedance and 1 dB load pull The measurement method proposed in [118] involves measuring the output power of the modem using a spectrum analyser while sweeping the impedance seen by the power amplifier (PA) with an impedance tuner. Once the power has reached its maximum, the impedance is optimal. The dummy board, plus the impedance tuner and the spectrum analyser (which represents a 50 Ω load) are then measured using a VNA, which provides the optimum load impedance. The 1 dB comprises the set of impedances for which the output power is degraded 1 dB. In the Smith chart, the load pull appears as a circle around the optimum load impedance, similar to the contours seen in Figure 3.25. 3.4.2 Optimum LNA source impedance and 1 dB noise source pull The procedure for the 1 dB noise source pull is similar to that for the PA [119], but requires a bit error ratio tester (BERT). The signal generator is set to output a frequency shift keying (FSK) signal and monitors the bit error rate (BER) produced by the device under test (DUT). The impedance tuner is set to the optimum noise source impedance to give minimum BER. The signal power is then increased by 1 dB and the impedance tuner is adjusted to provide a 0.1 % BER. Multiple impedances will provide this BER, drawing the 1 dB noise source pull (see contours in Figure 3.25). Juan Del Pino Mena 45 52 Chapter 4. Specification 4.2.3 Power system The power system (Figure 4.3) is similar to the first iteration, with many components remaining the same. As the device is an engineering model, it was deemed convenient to be able to power it using USB-C power delivery; this is why power supply ORing is contemplated. The power system mainly uses low-noise DC/DC converters for efficiency, as well as some LDO regulators for ad hoc voltages needed in the RF domain. In order to size the power system correctly, Table 4.2 and 4.3 estimate the consumption at each voltage (only the largest consumers are considered). The total amounts to 10.4 W. USB Type-C 2.0 data port CubeSat Bus eFuse & protections Power supply ORing Power monitoring Power monitoring eFuse & protections Low-noise DC/DCs Low-noise DC/DCs Low-noise LDOs Digital-domain power supply RF-domain power supply Figure 4.3 – High-level block diagram of the power system. Component Notes Current (mA) Power (mW) 1.2 V 3.3 V 5.0 V RPi CM5* During benchmark [125] – – 1000 5000 MCP2518** 40 MHz CLK, 20 MHz SPI [126] – 20 – 66 MCP2558** Dominant, 𝑉𝑇𝑋 𝐷 =0 V [127] – – 55 275 SX1302 Maximum activity [124] 85 1 – 105 Current consumption per rail (mA) 85 21 1055 Total (mW) Power consumption per rail (mW) 102 69 5275 5446 Table 4.2 – Estimation of power consumption of the digital system. *Power minus the wall adapter and fan. **Only one CAN bus is active at a given time. Component Notes Current (mA) Power (mW) 3.3 V 3.6 V 4.2 V CMX90A004 𝑃𝑖𝑛 =5 dBm,868 MHz,−40 ◦C[128] – 1200 – 4320 QPL9095 40 MHz CLK, 20 MHz SPI [126] – – 75 315 SX1250 868 MHz, TX 14 dBm, SMPS [117] 90 – – 297 SX1261 868 MHz, RX boosted, SMPS [74] 6 – – 20 Current consumption per rail (mA) 96 1200 75 Total (mW) Power consumption per rail (mW) 317 4320 315 4952 Table 4.3 – Estimation of power consumption of the radio system. 52 Development of a CubeSat payload for computing and LoRa communications 4.2. Hardware architecture 53 4.2.4 Mechanical considerations The payload must adhere to the PC/104-based CubeSat Kit Bus (CSKB) form factor [26], [27], the de facto standard for CubeSats [16]. The form factor determines the size of the PCB and the position of the CSKB headers and mounting holes. The design of the payload will be inspired by the SatNOGS COMMS board (Figure 4.4), a S-band and UHF, software-configurable TT&C radio transceiver for CubeSats, that is also open source [129], [130]. This board has a comparable level of design complexity and shares many similarities with the payload of this master’s thesis: it is a mixed-signal, communications and processing subsystem, that is also designed to mount a COTS module with dense B2B connectors as its processing unit. It is also EMI-shielded. The electromagnetic interference (EMI) shield will be machined from aluminium, and anodised. Exposed copper in the PCB makes electrical contact with the shield. The EMI shield will also be beneficial for heat sinking, as the power consumption of some components can be very high, as seen in the previous section. The chips that consume the most power will have direct thermal contact with the shield. (a) Top view, with EMI shield. (b) Bottom view, with EMI shield. (c) Top view, without EMI shield. (d) Bottom view, without EMI shield. Figure 4.4 – Renders of the SatNOGS COMMS board [129]. Juan Del Pino Mena 53 54 Chapter 4. Specification 4.3 Component selection This section presents the components selected to satisfy the architecture and requirements. The selection involves balancing specifications, power consumption, price, availability, and the complexity of implementation. Many of the component choices made in the previous iteration remain relevant, so they are not mentioned again here. Additionally, the rigid architecture of the LoRa gateways means that specific components must be used. Therefore, for brevity, only the most important component choices are highlighted in this section. 4.3.1 Compute module Single board computers (SBC) modules in compact form factors offer an attractive combination of performance, size, cost-effectiveness and flexibility, making them an ideal choice for challenging embedded applications such as this one. Using an off-theshelf computing module can significantly shorten the development cycle, as developers do not need to design complex core processor circuitry from scratch. The compute module provides the processing power, while the carrier board allows for customisation and tailoring to meet the payload’s unique requirements. In accordance with Pluton UPV’s preferences, the processing unit must be a Raspberry Pi Compute Module 5. This is an external constraint that must be met. One reason for this choice is that Raspberry Pi hardware benefit from a vast and mature software and hardware ecosystem, documentation, and community support. One drawback is that standard Raspberry Pi boards are designed for consumer electronics. However, its modular design makes upgrades easier: if different specifications are required in the future, another compute module can be added to an existing carrier board with minor modifications, saving time and effort on redesigning. There are many Raspberry Pi CM5-compatible compute modules on the market, such as the Raxda CM5 [131], some even in robust, industrial-grade versions, such as the Raxda CM3J [132]. (a) Top view. (b) Bottom view. Figure 4.5 – The Raspberry Pi Compute Module 5 [133]. 54 Development of a CubeSat payload for computing and LoRa communications 4.3. Component selection 55 4.3.2 CAN-SPI converter and CAN transceivers As specified by SpaceCAN [34], two redundant CAN buses are needed in the payload. However, the Raspberry Pi Compute Module 5 does not have native CAN support and therefore requires CAN-SPI converters. To avoid writing kernel drivers for CAN-SPI for GNU/Linux, it is essential to choose components with preexisting firmware support. Commercial CAN solutions for the Raspberry Pi include the open source CAN-FD shield by SeeedStudio [134], which uses the MCP2558FD controller and MCP2518FD transceiver from MicroChip [126], [127]. Software support for the MCP2518FD controller is robust, as its drivers are part of the mainline Linux kernel [135]. Moreover, the fact that the SeeedStudio board exists guarantees compatibility with the Raspberry Pi ecosystem. 4.3.3 Power amplifier Power amplifiers (PAs) operating in or near their saturation region are highly efficient, but introduce severe nonlinear amplitude distortion. For varying-envelope signals, this distortion would be detrimental [136]. As a variant of Chirp Spread Spectrum (CSS), LoRa is a constant-envelope modulation, allowing the use of nonlinear amplifiers. The PA should be capable of outputing 2 W (33 dBm), with a power added efficiency (PAE) of at least 40 %, and must be stable with any connected impedance. Two Heterojunction Bipolar Transistor (HBT) options were considered: the CMX90A004 (GaAs) and the SKY65111 (InGaP). However, the SKY65111 was rejected due to its poor impedance matching and the cumbersome external circuit required, to which the PA was very sensitive [137]. Conversely, the CMX90A004 has on-chip matching networks and bias circuitry [128] (see comparison in Figure 5.5,section 5.1.3.1 (page 59)). At 868 MHz 25 ◦Cand with an input power of 0 dBm, PAE of the CMX90A004 reaches 45 %, and the gain 33 dB. It saturates at 33 dBm of output power. Current consumption ranges from 0.8 A at 85 ◦Cto 1.2 A at −40 ◦C[128]. 4.3.4 Low Noise amplifier The QPL9095 is the selected low-noise amplifier (LNA). At 868 MHz at 25 ◦Cprovides 22 dB of gain, a high output third intercept point (OIP3) of 33 dBm and a noise figure (NF) of 0.6 dB, while consuming 50 mA [138]. Its relatively high gain and low noise figure enhance the receiver’s sensitivity, as demonstrated in section 2.4.5.1 (page 23). The QPL9095 requires few external components, maintains performance over temperature, and a single inductor matches the input impedance (see section 5.1.3.1 (page 59)). 4.3.5 RF power splitter The selected power splitter is the SCN-3-13+, a compact Low Temperature Co-Fired Ceramic (LTCC) splitter, ideal for this application. It exhibits 0.2 dB amplitude unbalance, 1◦phase unbalance, 15 dB isolation and 0.5 dB insertion loss at 868 MHz. Only a few external resistors are required at the output, and a low-pass LC network provides an adequate impedance match [139]. Juan Del Pino Mena 55 56 Chapter 5 Design The PCB design process begins by defining the logic of the circuit and the electrical connections between all components in a schematic. Then, the Electrical Rule Check (ERC) analyses a circuit for common electrical errors. This phase is described in section 5.1:Schematics. Next, a corresponding physical footprint (or land pattern) is created for each component in the schematic, defining the size and shape of the component’s pads. Modern EDA software allows 3D models to be incorporated into footprints. It is important to take into account trade-offs relating to electrical noise, thermal management and mechanical constraints when laying out the parts on the board. Electrical connections are then routed using traces between the pads of the components, according to the schematic and manufacturing rules [140]. An overview of the best practices, layout and routing of the PCB is described in section 5.2:Printed circuit board (page 85). Once the routing is complete, a Design Rule Check (DRC) is performed to identify any errors, such as shorts and clearance violations. The design is then exported as a set of files –commonly Gerbers– with the information necessary to produce the PCB [140]. 5.1 Schematics This section provides explanations of the most relevant circuits of the payload. The complete schematics can be found in Appendix C (page 113). 5.1.1 Best practices The following list are the best practices employed in the schematic design, intended to avoid issues such as incorrect pin assignments, electrical misconnections, as well as ensuring clean drafting practices and thorough documentation. Based on [141], [142]. •A hierarchical design of the schematics is carried out [143]. •Notes on component selection, connection and chip configuration are included. •Different types of nets are defined to establish subsequent routing rules. •The symbols have a clear, consistent appearance. Signals are organised by functionality. Symbols follow the KiCAD Library Convention (KLC) guidelines [106]. •Pin numbers of all symbols have been verified against the datasheet, and the pin assignment in the footprint is consistent. •Logic levels and polarities of all signals are correct for each input pin. •There are resistor pull-ups on all open-drain outputs. •There is a termination resistor (or a placeholder) on clocks and high-speed signals. •TX/RX signals are paired correctly (for UART, SPI, etc.). •Differential pair polarity has been checked. •There are eFuses and reverse voltage protection at the system power inlet. 57 58 Chapter 5. Design •There are ESD protection measures in place for data lines leaving the board and at the system power inlet [144], [145]. •There are undervoltage (UV) and overvoltage (OV) protections. •The power usage per rail has been verified against the regulator’s rating. •Decoupling capacitors are a common and effective noise and ripple filtering technique. Decoupling capacitors are present for all chips and meets or exceeds the vendor’s recommendations. There is bulk decoupling in all PSUs [145]–[147]. •Ceramic capacitors are rated for their capacitance/voltage curve. •Linear regulators are stable with a selected output capacitors’ ESR. •The power rail sequencing is checked against the device datasheets. •Test points are provided on all power rails and on any signals that may need probing during bring-up or debugging. Ground points are also provided. •No errors or warnings in the Electrical Rule Check (ERC). If any ERC entries are invalid, each one is inspected and dismissed with an explanation. 5.1.2 General outline Figure 5.1 depicts the low-level, hierarchical block diagram of the payload. In KiCAD, each block represents a schematic sheet, which has inputs and output signals. The schematics are divided into three main parts: radio, digital and power supply, which will be explained in the next sections. Figure 5.1 – Low-level, hierarchical block diagram of the complete payload. 58 Development of a CubeSat payload for computing and LoRa communications 5.1. Schematics 59 5.1.3 Radio schematics The radio schematics are subdivided into the RF front-end, the LoRa transceivers, and the LoRa baseband processor. The hierarchy of this part is shown in Figure 5.3. 5.1.3.1 RF front-end As seen on section 4.2:Hardware architecture (page 49) and replicated in the circuit shown in Figure 5.4a, the RF front-end consists of a transmit and a receive paths. As the system is half-duplex, an RF switch controls access to the shared RF I/O path. RF input/output path The shared RF I/O path consists of an RF switch and an elliptic filter with an additional LC low-pass filter (see Figure 5.4). The filter is designed to have a transmission zero at twice the pass frequency so that any harmonic in that spot is greatly attenuated. The simulation accounts for the additional DC cut and coupling capacitor, as well as the parasitic capacitance from the ESD protection diode at the antenna port. (a) Simulated circuit of the antenna filter, also used as PA output filter. (b) Frequency response of the antenna filter, also used as PA output filter. Figure 5.2 – Simulated circuit and frequency response of the antenna filter. Juan Del Pino Mena 59 60 Chapter 5. Design Figure 5.3 – Low-level, hierarchical block diagram of the radio part. 60 Development of a CubeSat payload for computing and LoRa communications 5.1. Schematics 61 (a) Schematic of the RF front-end and RF input/output path. (b) Schematic of the filter for the antenna and for the power amplifier. Figure 5.4 – Schematic of the RF front-end and filter for the antenna and PA. Juan Del Pino Mena 61 68 Chapter 5. Design Figure 5.11 – Schematic of the radio receive path: low-noise amplifier, filters and power splitter. 68 Development of a CubeSat payload for computing and LoRa communications 5.1. Schematics 69 5.1.3.2 LoRa transceivers The schematics of the LoRa modems are based on Semtech’s gateway reference designs [64]–[67] and Nebra’s open source gateway [103]. The schematics for the two SX1250s (Radio A and B) and the SX1261 (Radio LBT) are very similar. Consequently, only the Radio A schematic is presented in this section, as it is more complex due to its dual role as receiver and transmitter (see Figure 5.17a). The complete schematics can be found in Appendix C (page 113) if needed. The SX1250 and SX1261 transceivers use either their integrated low-dropout (LDO) regulator or their DC/DC converter for self-biasing. The latter is used in this design due to its lower power consumption [117]. The modems are clocked by a 32 MHz ±0.5 ppm, GNSS-precision, clipped-sine wave TCXO model TG2520SMN 32.0000M-ECGNNM3. The oscillator output is connected to each transceiver via a series 10 pF DC-blocking capacitor and a 220 Ω resistor to reduce the clock amplitude [88], [124], [146]. SX1250 PA matching network The manufacturer does not provide any characterisation or experimental measurements to inform the design process, instead assuming that designers will simply copy the reference circuit [64]–[67] or characterise the transceivers as required [118], [119]. As the tests carried out on the evaluation boards were inconclusive and further tests are yet to be performed, the first option has been selected for this report and the matching network shown in Figure 5.13a has been used. The output impedance that this network matches is estimated to be 15 +𝑗2 Ω (see Figure 5.12). The frequency response of the filter is shown in Figure 5.13b. Figure 5.12 – Estimation of the output impedance of the SX1250 as the adapted impedance by the matching network proposed by the manufacturer. Juan Del Pino Mena 69 70 Chapter 5. Design (a) Simulated circuit of the SX1250’s RF output matching network. (b) Frequency response of the SX1250’s output matching network. Figure 5.13 – Circuit and simulation of the SX1250’s RFO matching network. SX1250/61 LNA matching network and balun The balun plays a dual role: it performs impedance matching and converts the singleended input to balanced for the differential input of the SX1250. Unfortunately, the only impedance figure provided for the SX1250 is the optimal source impedance at a single frequency point: 74 +𝑗134 Ω at 868 MHz [117]. The type of impedance (minimum noise or maximum power transfer) is ambiguous due to the absence of any explicit specifications, a situation that is compounded by the estimated noise figure of 6 dB of the LoRa modems. Consequently, it has been decided that, for the time being, the balun will be designed with the measured impedance from the experiment carried out in section 3.3:Tests (page 39) (which is not necessarily the optimal). To reduce costs, the reference design uses a three-element balun (Figure 5.14a), which has a poorer phase balance than other options. The proposed four-element balun (Figure 5.14b) can theoretically provide perfect 𝜋radians phase balance between the positive and negative inputs, optimizing LNA gain and receiver sensitivity [148]. 70 Development of a CubeSat payload for computing and LoRa communications 5.1. Schematics 71 In order to design the balun, the LNA impedance measured in section 3.3 is first converted into an equivalent series RC circuit: 𝑍LNA =20.6−𝑗119.8 Ω @ 𝑓=868 MHz =⇒𝑅𝑆=20.6 Ω ; 𝐶𝑆=1.53 pF (5.1) then transformed from series to parallel: 𝑄=𝜔·𝐶𝑃·𝑅𝑃≡ (𝜔·𝐶𝑆·𝑅𝑆)−1=5.82 𝑅𝑃=𝑅𝑆· (1+𝑄2)=717.3 Ω 𝐶𝑃=𝐶𝑆·𝑄2/(1+𝑄2)=1.49 pF (5.2) The topology in Figure 5.14b is synthesised following the steps described in [148]: 𝐿R2 =√︁𝑍0·𝑅𝑃/𝜔=34.72 nH 𝐶R2 =1/(𝜔2·𝐿R2)=0.97 pF 𝐶R1 =2·𝐶R2 =1.94 pF 𝐿LNA =1/(𝜔2·𝐶P)=22.62 nH 𝐿R1 =(𝐿LNA ·2𝐿R2)/(𝐿LNA +2𝐿R2)=17.06 nH (5.3) Following several simulation iterations, the following commercial values were agreed: 𝐿R1 =16 nH ; 𝐿R2 =33 nH ; 𝐶R1 =1.9 nH ; 𝐶R2 =1.0 nH (5.4) The 𝑆11 simulations results in Figure 5.15a prove that the impedance is matched. The phase balance is measured as the phase delta between the two input ports, shown in Figure 5.15b demonstrate the almost 180◦phase balance, specially good compared to the original manufacturer’s balun. On the other hand, Figure 5.16a shows that the fourelement balun achieves a far more precise magnitude balance than the three-element balun. However, with these balun structures there is a cost in terms of insertion losses, which amount to an additional 3 dB on top of the ideal 3 dB (see Figure 5.16b). (a) Three-element balun from the manufacturer. (b) Four-element balun proposed in this work. Figure 5.14 – Simulated circuits of the three-element and four-element baluns. Juan Del Pino Mena 71 72 Chapter 5. Design (a) Comparison of the return loss. (b) Comparison of the phase balance. Figure 5.15 – Comparison between the return loss and phase balance of the three-element and four-element baluns. 72 Development of a CubeSat payload for computing and LoRa communications 5.1. Schematics 73 (a) Comparison of the magnitude balance. (b) Comparison of the transmission coefficients. Figure 5.16 – Comparison between the transmission coefficient and the magnitude balance of the three-element and four-element baluns. Juan Del Pino Mena 73 74 Chapter 5. Design (a) Radio A: SX1250 in transmitter and receiver configuration. (b) Precision TCXO for the LoRa transceivers. Figure 5.17 – Schematics of a SX1250 modem and the transceivers’ TCXO. 74 Development of a CubeSat payload for computing and LoRa communications 5.1. Schematics 75 5.1.3.3 LoRa baseband processor As explained in section 4.2:Hardware architecture (page 49), the LoRa baseband processor transforms the I/Q data from the transceivers into a LoRa frame byte array and vice versa. Figure 5.18 shows the implemented circuit. The SX1302 has dedicated SPI and I/Q interface that are connected directly to radios A and B. It also controls the modems’ reset signals and manages the RF switch. The I/Q interface contains placeholder series termination resistor arrays that may be required for signal integrity. The SX1302 receives a 32 MHz clock through the LoRa transceivers. The SX1302 also provides a host SPI interface for configuration and data exchange. A pull-up resistor has been placed on the chip select pin to prevent the SX1302 from being accidentally selected upon reset of the host. Hardware design guidelines and programming guides for the SX130x chips are notably lacking. The functionality of the GPIO and RADIO_CTRL pins is not described, and the closest available resource is the SX1302 hardware abstraction layer (HAL) [69]. Therefore, to ensure compatibility with the software, the pin configuration was kept the same as in the reference designs [64], [66]. Similarly, due to the aforementioned lack of programming documentation, the truth table for activating the LNA and PA and shutting down the SKY66420-11 front-end module IC [102] used in the gateway reference designs [66] is replicated using several logic gates. This allows the default software to be used without modification. These gates are present on the RF I/O path circuit (Figure 5.4a). The chip is supplied with two power rails: 1.2 V for the core (main supply) and 3.3 V for the I/O. As recommended, 100 nF decoupling capacitors are placed on each power pin, along with an additional 1µFcapacitor for some specific pins [64]. 5.1.4 Digital schematics The hierarchy of the digital part is shown in Figure 5.19. The digital schematics comprise the Raspberry Pi Compute Module 5 single-board computer (SBC) and the interfaces provided for it: including two USB Type-C ports for power and data, a microSD card reader, two redundant CAN buses, and satellite-specific connectors. There are also four temperature sensors to be spread throughout the board (Figure 5.21). The engineering model has several debug configuration switches and solder bridges, as well as a power button, to assist with the development and debugging stages. 5.1.4.1 Compute Module The circuit is shown in Figure 5.20. The schematics have been informed by the Compute Module 5 (CM5) datasheet [133] and the official CM5 IO Board design resources [149]. The Ethernet, HDMI, integrated display, camera, USB 3.0 and PCIe interfaces are all disconnected. The compute module has been hard-configured to disable both Bluetooth and Wi-Fi. A 3 V battery maintains the real-time clock (RTC). The connection between the LoRa radio and the CM has been derived from Semtech’s gateway reference designs, their interface PCBs [64]–[67], SeeedStudio’s WM1302 gateway module and its Raspberry Pi hat [68], [72], [150] and Nebra’s LoRa gateway [103]. Juan Del Pino Mena 75 76 Chapter 5. Design Figure 5.18 – Schematic of the LoRa baseband processor. 76 Development of a CubeSat payload for computing and LoRa communications 5.1. Schematics 77 Figure 5.19 – Low-level, hierarchical block diagram of the digital part. Juan Del Pino Mena 77 84 Chapter 5. Design (a) 3.6 V RF supply DC/DC converter. (b) 4.2 V, 3.3 V and 1.8 V RF supply LDO regulators. Figure 5.28 – Schematic of the RF voltage regulators. 84 Development of a CubeSat payload for computing and LoRa communications 5.2. Printed circuit board 85 5.2 Printed circuit board 5.2.1 Design rules PCB editors allow design rules to be defined based on manufacturing constraints, such as materials, trace widths, clearances, hole sizes, and their tolerances. This helps engineers to create designs that can actually be produced. These rules can then be verified using the Design Rule Checker (DRC). The PCBs are expected to be manufactured by Eurocircuits N.V., and the PCB shall adhere to their materials [105], capabilities and tolerances [157]. A class-6D manufacturing process will be used [104]. 5.2.2 Materials, stackup and layer assignment A stack-up or build-up refers to the arrangement of the layers that make up a PCB. It refers to the sequence and type of conductive and insulating materials that are stacked and laminated together. The selection of a stackup is a compromise between design complexity, ease of routing, signal integrity and cost. Due to the inherent complexity of the PCB (a mixed-signal design with controlled impedance constraints) and the dense signal fanout required for the compute module and larger integrated circuits, a 6-layer stackup has been determined to be the minimum requirement for this design. The stackup is shown in Figure 5.29. Of the options available in the controlled impedance pool at Eurocircuits, a substrate based on Isola IS400 is used [105]. This material is suitable for controlled impedance without the outlay of more specialized substrates. Prepregs types are PR2116 for the external laminate and PR1080 for the internal one. The copper layers are 0.035 mm thick, enabling both controlled impedance signals and power to be routed in the same layer. The total estimated PCB height is 1.60 mm, a standard thickness offering good mechanical rigidity. Meanwhile, the 6-layer controlled impedance stackup achieves a target impedance of 50 Ω impedance with a thin 0.185 mm microstrip trace, necessary for small IC footprints (see section 5.2.3:Trace width, controlled impedance and via sizes). Figure 5.29 – 6-layer, controlled impedance PCB stackup. Juan Del Pino Mena 85 86 Chapter 5. Design The layer assignment is as follows, using KiCAD’s layer naming convention: L1, F.Cu Front (top) layer, for signal routing. Controlled-impedance microstrip traces. L2, In1.Cu GND plane. Reference for F.Cu. L3, In2.Cu Signal routing layer, stripline, for non-controlled-impedance digital signals. L4, In3.Cu Power routing layer. L5, In4.Cu GND plane. Reference for B.Cu. L6, B.Cu Bottom layer, for signal routing. Controlled-impedance microstrip traces. 5.2.3 Trace width, controlled impedance and via sizes Tools such as the KiCAD PCB calculator [158], WCalc [159], QUCStrans [160], or Saturn PCB Toolkit [161] can determine the trace width needed to achieve a given impedance, based on mathematical models of microstrip and stripline (see Figure 5.30). Table 5.1 summarizes the trace width for each net class, calculated using the manufacturer’s own tool. In the PCB, controlled-impedance signals are routed exclusively in the outer layers to ensure impedance accuracy. This is because striplines tend to be less accurate in stackups with a small number of layers, as the reference planes may be far from the signal layer and they may be discontinuous [162]. According to the Saturn PCB Toolkit [161], with the selected stackup a 0.3 mm power trace can handle 1.2 A for a temperature increase of 10 K,anda0.6 mm trace 1.8 A. Two types of vias are employed (Table 5.2): a signal via, which is designed for fanout and routing of all kinds of digital signals at the limit of the manufacturer’s Class 6D tolerances; and a power via with a larger drill hole and higher current rating. To reduce costs and simplify the design, the PCB will not use blind vias, buried vias or microvias. Single-Ended (SE) Differential pair (DP) Net class Target impedance (Ohms) Trace width (mm) Clearance (mm) Trace width (mm) Gap (mm) Default None 0.150 0.150 – – Power None 0.600 0.150 – – RF50 50 (SE) 0.185 0.150 – – USB90D 90 (DP) 0.185 0.150 0.185 0.195 CAN120D 120 (DP) 0.150 0.150 0.150 0.400 Table 5.1 – Trace widths in each net class. Calculated using Eurocircuits PCB configurator. Via type 𝑑 (mm) 𝑎 (mm) ℎ (mm) 𝑍 (Ω) 𝐿 (nH) 𝐶 (pF) 𝑓𝑠𝑟 (GHz) 𝐼𝐷𝐶 (A) Signal via 0.20 0.10 1.6 23 1.3 2.5 4.1 1.3 Power via 0.30 0.15 1.6 27 1.4 2.0 6.7 1.6 Table 5.2 – Via sizes and ratings. Calculated using Saturn PCB Toolkit [161]. 86 Development of a CubeSat payload for computing and LoRa communications 5.2. Printed circuit board 87 (a) Structure of a microstrip. (b) Structure of a stripline. Figure 5.30 – Structure of a microstrip and a stripline. ℎis the substrate height, 𝑤,𝑙and 𝑡are the conductor width, length and thickness, respectively, 𝜀𝑜is the dielectric constant of vacuum, and 𝜀𝑟the dielectric constant of the substrate. Extracted from [163] (modified). 5.2.4 Best practices This section outlines the best practices employed during the development of the board to prevent common manufacturing and assembly issues, as well as mechanical problems. It also covers electrical issues, clearances, proper trace routing, signal integrity, noise and EMI reduction techniques, and thermal considerations. Partially based on [141], [142]. •The schematic review has been completed, taking into account the pin swaps that were carried out during the layout process. •All components are available in the selected packages. •There are no errors or warnings in the Design Rule Check (DRC). Any invalid DRC entries are inspected and dismissed with an explanation. •All connectors to other systems comply with the appropriate mating connector, orientation, and pin assignment. The connectors and buttons are accessible elements on the outward-facing side of the board. •A footprint for an EMI shield with exposed ground copper and mounting holes is provided. There is clearance around the mounting holes and the shield’s landing. •Exposed pads (i.e. thermal pads) and vias use a solid connection to ground for heatsinking to the internal copper planes [63]. •The paste prints on the exposed pads are segmented to avoid excessive deposition. •All test points are labelled and there is clearance for probe tips. The exposed ground connection for the EMI shield provides easy access to ground. •The 6-layer stack-up that has been selected ensures the presence of continuous and close reference planes for the external layers. This allows the traces on F.Cu and B.Cu layers to be designed as microstrip. To avoid impedance mismatches, controlled impedance tracks are routed on a single external layer [162]. •The same ground plane is used in order to avoid current return path discontinuities. Instead, good layout, zoning and routing practices are employed. To achieve an effective ground plane, optimal current return path management techniques (such as via stitching) must be employed [145], [147], [164]–[166]. •Power, RF and digital circuits are in separate zones [145], [147], [162], [164], [166]. •Unused via pads are removed in internal layers to create the smallest slot possible in internal reference and power planes. Juan Del Pino Mena 87 88 Chapter 5. Design •Via stitching connects large areas of copper assigned to ground on different layers, creating strong vertical electrical and thermal connections through the PCB. It maintains low ground impedance and short return loops providing the best possible ground quality and low EMI coupling [145], [164]. •Via shielding is placed along a signal trace or surrounding a board zone to reduce crosstalk and EMI [145], [146]. •The routing angle is not a concern, except for microwave and high-speed signals, which can radiate at sharp turns [145]–[147]. RF traces will be rounded. •Rules for trace length are incorporated into USB and CAN buses to match skew. •Teardrops, copper fillets extend from traces to pads and vias to strengthen the electrical, thermal and mechanical properties, as well as mitigating the effects of drill wander and layer misalignment [167], [168]. •Non-critical, low-speed signals can be grouped together in bundles without considering crosstalk between them. However, signals that require signal integrity, or that could cause crosstalk (e.g. clocks), are given clearance to other nets [162] •Power is routed using polygons and/or wide traces to minimise conductor resistance and avoid voltage drops or trace heating [146], [166]. •ESD protections are located near ports to prevent the discharge from spreading. •The plating and head landings of the CSKB-stack protect against mechanical protect against mechanical stress. However, they are isolated to prevent noise injection, as the CubeSat structure could act as an inadvertent antenna [169]. •Decoupling capacitors provide an energy reserve close to the chip, supplying it during pulsed draws and preventing the supply voltage from dropping. To reduce loop inductance, decoupling capacitors must be located close to the power pins of a chip and make use of side vias near its power/ground pads. [145]–[147]. •Large capacitors are significant power reservoirs and provide low-frequency decoupling, but they are ineffective at high frequencies and increase inrush current. For this reason, it is common practice to use several capacitors of different capacities and sizes to reduce their ESR across a broad spectrum [145] (see Figure 5.31). 1051061071081091010 Frequency (Hz) 10 3 10 1 101 103 105 107 Impedance (| |) Impedance C0402C102K5RAC C0201C470K3GAC C0805C226K8PAC C0603X474K8RAC Combined impedance 1051061071081091010 Frequency (Hz) 10 3 10 2 10 1 100 101 102 ESR (| |) Equivalent Series Resistance Figure 5.31 – Impedance of capacitors and their combined impedance. Data from K-SIM [170]. 88 Development of a CubeSat payload for computing and LoRa communications 5.2. Printed circuit board 89 5.2.5 Walkthrough of the printed circuit board This section reviews the layout and routing of the final PCB after multiple iterations. The design makes extensive use of KiCAD’s comprehensive, high-quality built-in libraries [171]. Some additional footprints were taken from the LibreSpace Foundation KiCAD library [172]. The Raspberry Pi Compute Module 5 design files are derived from Trident Sensing’s KiCAD library [173] and the official Compute Module 5 IO Board design documents [149]. The shape of the PCB is based on the LibreCube board template [174]. The overall PCB design was inspired by the SatNOGS COMMS board, an open source, dual-band radio transceiver for CubeSats [129], [130]. PCB layer prints are shown in Figure 5.32,5.33 and 5.34. 3D renders are shown in Figure 5.35. See Appendix C (page 113) for the complete PCB prints. 5.2.5.1 Layout The layout is constrained by the CSKB form factor, which dictates the position of the CubeSat headers and mounting holes. The board has cut-outs to allow cables to be routed to the sides of the board. The diret-to-OBC PicoBlade connector is placed beside one of the cut-outs; and the uSD card reader is on the opposite side. The MMCX RF I/O connector is slightly sunken into the board, allowing the cable head to sit in the resulting space without protruding much. The USB type-C connectors are positioned at corners of the board to save space, and, as they may not be included in the flight model, the shield surrounds them to prevent noise from entering through their openings. For easier assembly, most of the components are located on the front layer, and most of the parts on the bottom layer are optional. However, due to the presence of the B2B connectors for the Compute Module 5 on the bottom layer, the PCB it will have to be soldered in two steps. First, reflow soldering will be performed using high-temperature solder paste on the front layer. A second reflow will be carried out using lower-temperature paste on the bottom layer to prevent the front components from falling off [168]. Due to the abundance of components, their placement will be automated using pickand-place machines. Because of this, and to prioritise optimal component placement, routing and reduce visual clutter, the component designators have been hidden. During the debugging phase, the board can be inspected using tools such as the interactive HTML BOM plugin for KiCAD [175], rather than only relying on the silkscreen. Test points are clearly labeled and in the front layer for easy access. Buttons, switches, jumpers, connectors, receptacles, and temperature sensors are also labelled. The areas of the board are marked, and text identifying the version and date of the PCB is included. Just like the circuits, the layout is divided into radio,digital and power circuits, physically separate. An overview of each will be provided below. 5.2.5.2 Radio The radio stage is located in its own shielded area away from the other circuits. The analogue RF traces are prioritised and given ample clearance from any copper, including the ground plane, to ensure trace impedance accuracy and minimise noise coupling. The LNA and PA –the most layout-sensitive components in the RF chain– are routed Juan Del Pino Mena 89 90 Chapter 5. Design in accordance with the manufacturer’s recommendations [128], [138]. The thermal design is critical for the PA, so abundant thermal vias have been placed. The PA is also expected to make contact with the EMI shield, which will absorb heat as thermal mass. Two temperature sensors have been placed in the bottom side, one between the four LoRa chips and the other below the PA. As the chips sinking heat onto the PCB and there is good vertical thermal conduction thanks to the thermal vias, the sensors will give an accurate measure of the ICs’ temperature on the opposite side. The LoRa transceivers are the intermediary between the digital and RF stages. The layout and routing of the LoRa transceivers follows the guidelines set forth by Semtech [118], [146], [176], and is based on their gateway reference designs [64]–[67] and Nebra’s open source gateway [103]. In the receiver path, the traces coming out of the power splitter to the transceivers are length-matched. The LoRa baseband processor’s fanout is the densest part of the board due to the pin density of the LoRa chip, the proximity of the B2B connector from the compute module, and the impossibility of routing certain signals through the outer layers due to the presence of the EMI shield landing. There was a trade-off between the proximity of the decoupling capacitors and the space required for the fanout, especially since almost all signals had to exit through vias to the internal layer tracks. This issue was tackled by applying orthogonal routing techniques. 5.2.5.3 Digital The compute module is in a quasi-central position on the board, providing convenient access to all signals. The B2B connector which contains the relevant GPIO and SPI buses has been placed near the circuits to which it connects. The USB type-C ports and uSD card reader are positioned relatively far from the CM, resulting in long routing in some cases. However, this is not anticipated to be a problem due to their slow speed. The CAN transceivers are placed in close proximity to the CAN pins of the CSKB. The power button and configuration switches are located in the bottom-left corner of the PCB. While their placement is not optimal, it was decided to keep them there due to space constraints and since their primary use is for debugging. 5.2.5.4 Power The power stage is distributed in two parts. The digital supply shares space with the CAN transceivers due to space constraints. Although CAN transceivers are not very sensitive, switching electronics are still placed as far away as possible. The radio supply has its own separated area to avoid injecting noise into the supply of the RF components. A temperature sensor have been placed in the middle of the large digital power area and another in the radio power supply. The layout of the DC/DC converter follows the manufacturer’s guidelines [177] and general step-down converter PCB layout recommendations [178]. A keepout zone has been placed for the ferrite bead to avoid switching noise coupling. Almost all of the power routing has been carried out in the In3.Cu layer (Figure 5.33b), and occasionally in the In2.Cu layer (Figure 5.33a) when space was lacking. 90 Development of a CubeSat payload for computing and LoRa communications 5.2. Printed circuit board 91 (a) Front copper,silkscreen,solder mask,paste,edge and courtyard. (b) Internal layer 1 (GND plane) ,edge cuts. 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Available: https : / / www . minicircuits . com/pdfs/ADTL1-12+.pdf. 108 Development of a CubeSat payload for computing and LoRa communications Appendix A Sustainable Development Goals The seventeen Sustainable Development Goals (SDG) provide a framework for achieving peace and prosperity for both people and planet Earth [182], [183]. The subsequent points detail how this thesis aligns with specific SDGs, with a summarised overview of the affinity for each SDG presented in Table A.1. 4. Quality education. The main focus of this master’s thesis is educational. This project is part of a student-led initiative within a university. This master’s thesis will serve as documentation, know-how and training for the next student members, as it demonstrates the application of engineering principles and contributes to the educational experience of the students involved, fostering the development of technical skills in a cutting-edge field. In addition, this document will be deposited in the institutional library of the UPV as open access. Furthermore, the ultimate goal of Estigia is to provide secondary school students with hands-on STEM learning experiences by communicating with a CubeSat, for which the payload developed in this master’s thesis is crucial. 9. Industry, Innovation and Infrastructure. Advances in CubeSat technology are driving innovation and industry development, with spillover effects into many sub-industries. This project aims to demonstrate the technical feasibility of novel communications electronics on CubeSats and to provide the space segment infrastructure for Earth-to-space communications by applying existing technologies to new domains. 10. Reduced inequality. A key feature of CubeSats is their role in democratising access to space services for a wider community. This Master’s thesis contributes to this goal by developing the satellite’s electronic systems for affordable, energy-efficient and long-range communications. 17. Partnership for the goals. Pluton UPV actively promotes collaboration with organisations that share a commitment to the Sustainable Development Goals. Furthermore, the inherent nature of open access publications such as this one promotes the widespread sharing of knowledge and encourages collaborative endeavours. 109 123456 123456 A B C D A B C D Date: 2025-05-22 KiCad E.D.A. 9.0.3 Rev: 0.1 Size: A4 Id: 1/19 Title: LoRa Payload - Cover and block diagram File: lora-payload.kicad_sch Sheet: / Pluton UPV, GAM-iTEAM-UPV Universitat þÿPolitècnica de Valencia Juan Del Pino Mena Development of a CubeSat payload for in-orbit computing and LoRa communications þÿMaster sThesis in Telecommunications Engineering SX1302_RESET RADIO_LBT_CSN RADIO_LBT_~{RESET} SX1302_CSN RADIO_LBT_DIO1 SX1302_SCK RADIO_LBT_MISO SX1302_MISO RADIO_LBT_SCK SX1302_MOSI RADIO_LBT_MOSI RADIO_LBT_BUSY SX1302_GPIO6 SX1302_GPIO8 RADIO_LBT_DIO2 2.0-radio File: schematics/2.0-radio.kicad_sch EN_RF_PSU PG_EFRF PG_3V6RF PG_3V3D PG_3V3RF PG_EFD PG_1V2D PG_1V8RF I2C.SDA I2C.SCL 3.0-power File: schematics/3.0-power.kicad_sch CM5_GPIO12_RADIO_POWER_EN CM5_SPI_0_SCLK CM5_GPIO27_SX1302_GPIO6 CM5_GPIO22_SX1261_DIO2 CM5_GPIO23_SX1261_DIO1 CM5_GPIO6_SX1302_RESET CM5_SPI_0_CSN_0_SX1302 CM5_SPI_0_CSN_1_SX1261 CM5_SPI_0_MOSI CM5_GPIO4_SX1261_BUSY CM5_GPIO5_SX1261_~{RESET} CM5_SPI_0_MISO CM5_GPIO26_SX1302_GPIO8 CM5_PG_EFUSE_D CM5_PG_EFUSE_RF I2C.SCL I2C.SDA 1.0-digital File: schematics/1.0-digital.kicad_sch H104H101 H103 GND H102 Shield 1 J102 RFShield Shield 1 J101 RFShield GND GND GROUND Mounting holes conenct to the CubeSat structure and are isolated. Shields connect to GND. The CM5 does not have enough free GPIOs to fit all power good signals LoRa gateway, RF front-end POWER SUPPLY Protections, DC/DCs, LDOs Common SPI interface for SX1302 and SX1261 RADIO Bottom DIGITAL Top Compute module, digital interfaces GNDGND J101 RFShield Shield 1 J102 RFShield Shield 1 123456 123456 A B C D A B C D Date: 2025-05-22 KiCad E.D.A. 9.0.3 Rev: 0.1 Size: A4 Id: 2/19 Title: Digital File: 1.0-digital.kicad_sch Sheet: /1.0-digital/ Pluton UPV, GAM-iTEAM-UPV Universitat þÿPolitècnica de Valencia Juan Del Pino Mena Development of a CubeSat payload for in-orbit computing and LoRa communications þÿMaster sThesis in Telecommunications Engineering I2C_1_SDA SPI_0_SCLK SPI_1_SCLK SPI_1_MOSI I2C_1_SCL USB2_DATA_P SPI_1_MISO SPI_0_MOSI SPI_0_MISO EEPROM_nWP PWR_BUTTON USB2_DATA_N UART_0_TX SPI_0_CSN_0_SX1302 SPI_1_CSN_0_CAN_A SPI_0_CSN_1_SX1261 SPI_1_CSN_1_CAN_B UART_0_RX GPIO4_SX1261_BUSY GPIO12_RADIO_POWER_EN GPIO5_SX1261_~{RESET} GPIO27_SX1302_GPIO6 GPIO22_SX1261_DIO2 GPIO26_SX1302_GPIO8 GPIO6_SX1302_RESET GPIO25_CAN_B_INT GPIO23_SX1261_DIO1 GPIO24_CAN_A_INT USB_CC1 USB_CC2 SD_DAT2 SD_DAT0 SD_DAT3 SD_CMD SD_DAT1 SD_CLK SD_ENABLE PMIC_ENABLE ~{nRPIBOOT} GPIO16_PG_EFUSE_RF GPIO13_PG_EFUSE_D 1.1-compute-module File: 1.1-compute-module.kicad_sch SPI_A_MISO SPI_B_MISO SPI_A_SCK CAN_A_INT SPI_B_CSN CAN_B_INT SPI_B_MOSI SPI_B_SCK SPI_A_MOSI SPI_A_CSN OBC_UART.TX OBC_UART.RX OBC_GPIO13_PWRBUT 1.2-interfaces File: 1.2-interfaces.kicad_sch USB2_DATA_N USB2_DATA_P USB_CC1 USB_CC2 SD_DAT1 SD_CMD SD_CLK SD_DAT2 SD_DAT0 SD_DAT3 SD_ENABLE 1.3-usb File: 1.3-usb.kicad_sch GND C201 0.1uF +3V3_D SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 U203 TMP117xxDRV C202 0.1uF +3V3_D SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 U204 TMP117xxDRV SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 U201 TMP117xxDRV +3V3_D +3V3_D GND C203 0.1uF SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 U202 TMP117xxDRV GND JP201 +3V3_D R202 +3V3_D C204 0.1uF GND GND R201 2.2 kOhms AC0402FR-7D2K2L JP202 GND 1 2 3 6 5 4 SW202 SW_DIP_x03 SW201 GND CM5_SPI_0_SCLK CM5_GPIO12_RADIO_POWER_EN CM5_GPIO23_SX1261_DIO1 CM5_GPIO26_SX1302_GPIO8 CM5_GPIO27_SX1302_GPIO6 CM5_GPIO22_SX1261_DIO2 CM5_PG_EFUSE_RF CM5_SPI_0_MOSI CM5_SPI_0_MISO CM5_GPIO6_SX1302_RESET CM5_SPI_0_CSN_1_SX1261 CM5_GPIO5_SX1261_~{RESET} CM5_SPI_0_CSN_0_SX1302 CM5_PG_EFUSE_D CM5_GPIO4_SX1261_BUSYI2C.SDA I2C.SCL I2C.SCL I2C.SCL I2C.SDAI2C.SDA I2C.SCL PWR_BUTTON I2C.SDA I2C.SDA I2C.SCL I2C.SDA I2C.SCL I2C.SCL PWR_BUTTON I2C.SDA RF power supply 0b1001011 SPI1 for CAN I2C for temp sensors and current-sense ADC CM5's power-up starts when the 5 V rail is above 4.75 V and PMIC_EN rises. Shouldn't be necessary to push the button. Power button can be controlled via OBC's GPIO13 The CM5 includes pull-up resistors Pull down CM5_EEPROM_nWP to prevent writing to the on-board EEPROM. Digital power supply 0b1001010 Push once to power on from a previous software poweroff. Push 5 s to force power off. Internally pulled up to 5 V via 10 kOhms Pull low CM5_PWR_EN to force the lowest possible power-down state SPI0 for LoRa **Usage is not documented. Some gateway designs do not use these GPIOs Pull CM5_~{nRPIBOOT}low to force booting from an RPI server (PC/USB) LoRa baseband 0b1001000 Power amplifier 0b1001001 Reset and enable signals must be correctly mapped in the lora_hal tools/reset_lgw.sh file Inter-subsystem communication COMPUTE MODULEUSB, SD CARD INTERFACE Temperature sensors SX1302 GPIOs** SX1261 GPIOs** Power & data CM5 control switches Disabled: Wifi/Bluetooth, video, SD card, PCIe. Power: 5 V & 5 A (peak, transient). Digital SAT INTERFACES C203 0.1uF GND +3V3_D U201 TMP117xxDRV SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 GND C202 0.1uF U203 TMP117xxDRV SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 GND C201 0.1uF U202 TMP117xxDRV SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 U204 TMP117xxDRV SDA 6 SCL 1 ADD0 4 V+ 5 GND 2 ALERT 3 JP201 +3V3_D R202 C204 0.1uF GND GND R201 2.2 kOhms AC0402FR-7D2K2L 123456 123456 A B C D A B C D Date: 2025-05-22 KiCad E.D.A. 9.0.3 Rev: 0.1 Size: A4 Id: 3/19 Title: Compute module File: 1.1-compute-module.kicad_sch Sheet: /1.0-digital/1.1-compute-module/ Pluton UPV, GAM-iTEAM-UPV Universitat þÿPolitècnica de Valencia Juan Del Pino Mena Development of a CubeSat payload for in-orbit computing and LoRa communications þÿMaster sThesis in Telecommunications Engineering BT301 Seiko MS621F MS621F GND R301 680 Ohms D301 Green USB 3.0 VBUS_EN 111 USB3-0-RX_N 128 USB3-0-RX_P 130 USB3-0-TX_N 140 USB3-0-TX_P 142 USB3-0-DP 134 USB3-0-DM 136 USB3-1-RX_N 157 USB3-1-RX_P 159 USB3-1-TX_N 169 USB3-1-TX_P 171 USB3-1-DP 163 USB3-1-DM 165 U301K Compute_Module_5 GPIO GPIO_VREF 78 ID_SD 36 ID_SC 35 GPIO2 58 GPIO3 56 GPIO4 54 GPIO5 34 GPIO6 30 GPIO7 37 GPIO8 39 GPIO9 40 GPIO10 44 GPIO11 38 GPIO12 31 GPIO13 28 GPIO14 55 GPIO15 51 GPIO16 29 GPIO17 50 GPIO18 49 GPIO19 26 GPIO20 27 GPIO21 25 GPIO22 46 GPIO23 47 GPIO24 45 GPIO25 41 GPIO26 24 GPIO27 48 U301B Compute_Module_5 +3V3_CM5 Ethernet Ethernet_SYNC_OUT 18 Ethernet_Pair0_N 10 Ethernet_Pair0_P 12 Ethernet_Pair1_N 6 Ethernet_Pair1_P 4 Ethernet_Pair2_N 9 Ethernet_Pair2_P 11 Ethernet_Pair3_N 5 Ethernet_Pair3_P 3 ~{Ethernet_nLED2} 17 ~{Ethernet_nLED3} 15 U301C Compute_Module_5 GND HDMI HDMI0_HOTPLUG 153 HDMI0_SDA 199 HDMI0_SCL 200 HDMI0_CEC 151 HDMI1_HOTPLUG 143 HDMI1_SDA 145 HDMI1_SCL 147 HDMI1_CEC 149 HDMI0_TX0_N 184 HDMI0_TX0_P 182 HDMI0_TX1_N 178 HDMI0_TX1_P 176 HDMI0_TX2_N 172 HDMI0_TX2_P 170 HDMI0_CLK_N 190 HDMI0_CLK_P 188 HDMI1_TX0_N 160 HDMI1_TX0_P 158 HDMI1_TX1_N 154 HDMI1_TX1_P 152 HDMI1_TX2_N 148 HDMI1_TX2_P 146 HDMI1_CLK_N 166 HDMI1_CLK_P 164 U301G Compute_Module_5 Display/Camera MIPI1_D0_N 175 MIPI1_D0_P 177 MIPI1_D1_N 181 MIPI1_D1_P 183 MIPI1_C_N 187 MIPI1_C_P 189 MIPI1_D2_N 193 MIPI1_D2_P 195 MIPI1_D3_N 194 MIPI1_D3_P 196 U301H Compute_Module_5 GND +5V_EFUSE_D Power +5V 77 GND 1 CM5_3.3V 84 CM5_1.8V 88 U301A Compute_Module_5 Miscellaneous VBAT 76 Fan_tacho 16 ~{WL_nDisable} 89 ~{BT_nDisable} 91 CAM_GPIO0 97 CAM_GPIO1 100 PWR_Button 92 EEPROM_nWP 20 ~{nRPIBOOT} 93 PMIC_ENABLE 99 Fan_PWM 19 ~{Pi_nLED_Activity} 21 ~{PI_LED_nPWR} 95 I2C_SCL0 80 I2C_SDA0 82 CC1 94 CC2 96 U301J Compute_Module_5 SD Card SD_VDD_Override 73 SD_CLK 57 SD_CMD 62 SD_DAT0 63 SD_DAT1 67 SD_DAT2 69 SD_DAT3 61 SD_DAT4 68 SD_DAT5 64 SD_DAT6 72 SD_DAT7 70 SD_PWR_ON 75 U301I Compute_Module_5 USB 2.0 USB_OTG_ID 101 USB_N 103 USB_P 105 U301D Compute_Module_5 Display/Camera MIPI0_D0_N 115 MIPI0_D0_P 117 MIPI0_D1_N 121 MIPI0_D1_P 123 MIPI0_C_N 127 MIPI0_C_P 129 MIPI0_D2_N 133 MIPI0_D2_P 135 MIPI0_D3_N 139 MIPI0_D3_P 141 U301F Compute_Module_5 GND U301L Compute_Module_5 PCIe ~{PCIe_CLK_nREQ} 102 PCIe_RX_P 116 PCIe_RX_N 118 PCIE_PWR_EN 106 PCIE_DET_nWAKE 104 ~{PCIe_nRST}109 PCIe_TX_P 122 PCIe_TX_N 124 PCIe_CLK_P 110 PCIe_CLK_N 112 U301E Compute_Module_5 +3V0_RTC GND +3V3_CM5 POWER GPIO22_SX1261_DIO2 SD_ENABLE SPI_1_MOSI SD_DAT1 SD_DAT3 SD_DAT2 GPIO24_CAN_A_INT GPIO23_SX1261_DIO1 SD_CLK GPIO25_CAN_B_INT SD_DAT0 GPIO26_SX1302_GPIO8 SD_CMD GPIO27_SX1302_GPIO6 I2C_1_SDA SPI_0_CSN_1_SX1261 SPI_0_CSN_0_SX1302 GPIO5_SX1261_~{RESET} GPIO4_SX1261_BUSY GPIO6_SX1302_RESET USB2_DATA_P USB2_DATA_N EEPROM_nWP SPI_0_MOSI SPI_0_MISO PMIC_ENABLE PWR_BUTTON ~{nRPIBOOT} USB_CC2 GPIO16_PG_EFUSE_RF I2C_1_SCL USB_CC1 SPI_1_MISO SPI_0_SCLK GPIO12_RADIO_POWER_EN UART_0_RX SPI_1_SCLK SPI_1_CSN_1_CAN_B UART_0_TX GPIO13_PG_EFUSE_D SPI_1_CSN_0_CAN_A GPIO2 and GPIO 3 already have 1.8 kOhm pull-up resistors - PWR_BUTTON: Pull low to power up the CM5, or power down if held low for longer than 5 seconds. - PMIC_EN: Pull low for the lowest possible power-down state. - EEPROM_nWP: Pull low to prevent writing the on-board EEPROM. - nRPI_BOOT: pull low to boot from USB2 instead of eMMC. Hat/shield identification Not used SD card only available on CM5 Lite Not used Activity LED Not used Compute Module 5 Not used Not used Not used Not used U301A Compute_Module_5 +5V 77 GND 1 CM5_3.3V 84 CM5_1.8V 88 +5V_EFUSE_D GND +3V3_CM5 U301L Compute_Module_5 GND GND R301 680 Ohms D301 Green BT301 Seiko MS621F MS621F +3V0_RTC U301B Compute_Module_5 GPIO_VREF 78 ID_SD 36 ID_SC 35 GPIO2 58 GPIO3 56 GPIO4 54 GPIO5 34 GPIO6 30 GPIO7 37 GPIO8 39 GPIO9 40 GPIO10 44 GPIO11 38 GPIO12 31 GPIO13 28 GPIO14 55 GPIO15 51 GPIO16 29 GPIO17 50 GPIO18 49 GPIO19 26 GPIO20 27 GPIO21 25 GPIO22 46 GPIO23 47 GPIO24 45 GPIO25 41 GPIO26 24 GPIO27 48 +3V3_CM5 123456 123456 A B C D A B C D Date: 2025-05-22 KiCad E.D.A. 9.0.3 Rev: 0.1 Size: A4 Id: 4/19 Title: CAN transceivers, interfaces File: 1.2-interfaces.kicad_sch Sheet: /1.0-digital/1.2-interfaces/ Pluton UPV, GAM-iTEAM-UPV Universitat þÿPolitècnica de Valencia Juan Del Pino Mena Development of a CubeSat payload for in-orbit computing and LoRa communications þÿMaster sThesis in Telecommunications Engineering R406 33 Ohms AC0402FR-0733RL GND +3V3_D C407 0.1uF GND C402 0.1uF R403 R402 R401 C406 1uF R405 0 Ohms AC0402FR-070RL GND ~{ST} 1 Vcc 4 GND 2 OUT 3 Y401 SG-210STF SG-210STF 40.0000ML C414 0.1uF GND R408 R411 0 Ohms AC0402FR-070RL +5V_CSKB R404 120 Ohms AC0402FR-07120RL C404 0.1uF GND GND TXD 1 RXD 4 VIO 5 S 8 VDD 3 VSS 2 CANH 7 CANL 6 U401 MCP2558FD-xMF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 CSKB-H401 ESQ-126-39-G-D +5V_CSKB R407 GND GND +5V_CSKB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 CSKB-H402 ESQ-126-39-G-D +3V3_D C401 1uF C403 1uF +3V3_D GND GND SDI 11 SDO 12 ~{CS} 13 SCK 10 OSC2 5 OSC1 6 VDD 14 VSS 7 RXCAN 2 TXCAN 1 CLKO/SOF 3 ~{INT} 4 ~{INT0}/GPIO0/XSTBY 9 ~{INT1}/GPIO1 8 U404 MCP2518FD-xQBB P13_UART.RX 1 P13_UART.TX 2 GND 3 PPS 4 GND 5 I2C.SDA 6 I2C.SCL 7 GND 8 CAN_A_H 9 CAN_A_L 10 OBC_UART.RX 11 NC 12 NC 13 OB_UART.TX 14 MP MP J401 PicoBlade-14 532611471 C412 0.1uF +5V_EFUSE_D GND GND R410 120 Ohms AC0402FR-07120RL +5V_EFUSE_D TXD 1 RXD 4 VIO 5 S 8 VDD 3 VSS 2 CANH 7 CANL 6 U403 MCP2558FD-xMF GNDGND GND C411 0.1uF C410 1uF R409 R412 33 Ohms AC0402FR-0733RL +3V3_D C405 0.1uF GND +3V3_D C409 0.1uF C408 1uF D401 SP0402B-ELC-01ETG SDI 11 SDO 12 ~{CS} 13 SCK 10 OSC2 5 OSC1 6 VDD 14 VSS 7 RXCAN 2 TXCAN 1 CLKO/SOF 3 ~{INT} 4 ~{INT0}/GPIO0/XSTBY 9 ~{INT1}/GPIO1 8 U402 MCP2518FD-xQBB GND GND +3V3_D ~{ST} 1 Vcc 4 GND 2 OUT 3 Y402 SG-210STF SG-210STF 40.0000MLGND C413 1uF CAN120D POWER CAN120DSPI_A_CSN OBC_GPIO13_PWRBUT OBC_UART.RX OBC_UART.TX CAN_A_INT SPI_A_MOSI SPI_A_MISO CAN_B_INT SPI_B_MOSI SPI_A_SCK SPI_B_MISO SPI_B_SCK SPI_B_CSN CAN_A.TXD CAN_B_N CAN_B_P CAN_A.RXD I2C.SCLCAN_A_OSC.OUT I2C.SDA CAN_A_P CAN_A_N CAN_A_N CAN_B.RXD CAN_B_OSC.OUT CAN_B.TXD CAN_B_P CAN_A_P CAN_B_N CAN_A_P CAN_A_N Power button control via an OBC GPIO The MCP2518FD is supported in the mainline linux kernel since version 5.10 Direct-to-OBC dedicated picoblade connector CSKB Header H2CSKB Header H1 Unused (Not used) CAN B TXCAN -- TXD RXCAN -- RXD (Not used) Same I2C as in the CSKB CAN A (Not used) SPI TO CAN CONVERTER / CAN TRANSCEIVERS CSKB AND OBC CONNECTOR Same CAN interface as in the CSKB (Not used) Unallocated pins for RS422 R404 120 Ohms AC0402FR-07120RL C404 0.1uF GND GND U401 MCP2558FD-xMF TXD 1 RXD 4 VIO 5 S 8 VDD 3 VSS 2 CANH 7 CANL 6 D401 SP0402B-ELC-01ETG +5V_CSKB +5V_CSKB +5V_CSKB CSKB-H402 ESQ-126-39-G-D 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +3V3_D C401 1uF C406 1uF GND +3V3_D GND R403 R402 R401 R406 33 Ohms AC0402FR-0733RL R405 0 Ohms AC0402FR-070RL GND Y401 SG-210STF SG-210STF 40.0000ML ~{ST} 1 Vcc 4 GND 2 OUT 3 GND R408 R411 0 Ohms AC0402FR-070RL R407 R409 R412 33 Ohms AC0402FR-0733RL +3V3_D C405 0.1uF GND +3V3_D C408 1uF C410 1uF U402 MCP2518FD-xQBB SDI 11 SDO 12 ~{CS} 13 SCK 10 OSC2 5 OSC1 6 VDD 14 VSS 7 RXCAN 2 TXCAN 1 CLKO/SOF 3 ~{INT} 4 ~{INT0}/GPIO0/XSTBY 9 ~{INT1}/GPIO1 8 GND GND +3V3_D Y402 SG-210STF SG-210STF 40.0000ML ~{ST} 1 Vcc 4 GND 2 OUT 3 GND C413 1uF GND +3V3_D GND U404 MCP2518FD-xQBB SDI 11 SDO 12 ~{CS} 13 SCK 10 OSC2 5 OSC1 6 VDD 14 VSS 7 RXCAN 2 TXCAN 1 CLKO/SOF 3 ~{INT} 4 ~{INT0}/GPIO0/XSTBY 9 ~{INT1}/GPIO1 8 C412 0.1uF +5V_EFUSE_D GND C403 1uF R410 120 Ohms AC0402FR-07120RL +5V_EFUSE_D U403 MCP2558FD-xMF TXD 1 RXD 4 VIO 5 S 8 VDD 3 VSS 2 CANH 7 CANL 6 GNDGND GND C411 0.1uF