Evaluating ECC for Cache Reliability Under Multi-Bit Upsets: A Design Space Exploration

Evaluating ECC for Cache Reliability Under Multi-Bit Upsets: A Design Space Exploration Foteini Kotsimpou George Papadimitriou Dimitris Gizopoulos University of Athens, Greece {fotkotsimpou |georgepap |dgizop}@di.uoa.gr Abstract—Cache memory reliability is a critical concern in modern processor architectures, particularly in systems deployed in fault-prone environments or at large scale. As modern computing systems increasingly rely on cache memories for performance, ensuring their reliability against transient faults (soft errors) is crucial. Several protection schemes, such as parity or error-correcting codes (ECC), have been proposed to enhance cache robustness. However, these techniques introduce trade-offs in terms of performance and effectiveness, which are particularly relevant in RISC-V-based CPUs due to their flexibility and modular design. This paper presents a comprehensive characterization and design space exploration of error protection mechanisms (parity and Single Error Correction Double Error Detection - SECDED - ECC) in the cache memories of RISC-V CPUs. We employ statistical fault injection at the microarchitecture level to evaluate the impact of transient faults on system reliability, analyzing their effects across system layers in a full-system setup using the gem5 simulator, the only environment that supports the execution of long workloads. By comparing caches with and without protection, we provide insights into error resilience, overheads, and the effectiveness of protection schemes. Our study can drive the selection of appropriate protection strategies for various RISC-V implementations, ranging from embedded systems to high-performance computing platforms. Our findings offer valuable guidance for the design of robust and efficient RISC-Vbased systems operating under reliability constraints. Index Terms—Reliability, RISC-V, ECC, microprocessors, caches, microarchitecture, fault injection, silent data corruption. I. INTRODUCTION Cache reliability is a critical concern in modern microprocessors, particularly as technology scaling increases susceptibility to transient faults and soft errors [1], [2]. In RISC-V architectures, which emphasize extensibility and open-source innovation, designers have flexibility in implementing various cache protection schemes. Moreover, new hardware-based protection solutions continue to emerge, aiming to improve essential aspects such as performance, energy efficiency, and area overhead, thereby enhancing the overall effectiveness of protection schemes [3]–[5]. However, selecting the optimal protection mechanism requires careful consideration of tradeoffs between reliability, performance, and hardware overhead. A widely adopted approach to mitigating soft errors in cache memories is the uniform integration of error detection codes (EDC) and error correction codes (ECC) across all cache blocks [3]. In these methods, each cache block is augmented with an EDC and/or ECC, ensuring that every read or write operation includes error detection/correction or the encoding of EDC/ECC, respectively. Typically, parity codes serve as the simplest form of error detection, while Hamming [6] and Hsiao [7] codes are the most common ECC techniques, enabling single-bit error correction and doublebit error detection (SECDED). These methods are usually used in cache memories of modern microprocessors due to the substantially low overhead associated with the storage and complexity of ECC circuitry [8]. Specifically, some microprocessors employ lightweight error detection codes (EDC), such as parity, in timing-critical L1 caches, while delegating error correction to lower levels of the cache hierarchy. This approach is a common protection strategy in modern microprocessors to reduce the latency overhead associated with ECC codes, during read operations [9], [10]. As microprocessor designs move towards more open and customizable architectures, ensuring cache reliability in RISCV CPUs is becoming an increasingly important challenge. Unlike traditional proprietary ISAs, RISC-V enables tailored microarchitectural decisions, including cache structures and protection mechanisms. However, this flexibility also means that there is no one-size-fits-all solution for cache reliability. Soft errors induced by radiation, aging effects, and manufacturing variations pose significant reliability risks, especially in safety-critical systems, edge computing, and high-performance computing environments [11]. Given the increasing adoption of RISC-V in automotive, IoT, and HPC applications, a systematic study of cache protection mechanisms tailored for RISC-V architectures is necessary. This paper aims to fill this gap by exploring the most prevalent protection techniques, assessing their effectiveness, and providing practical insights for designers. We employ a design space exploration approach, incorporating statistical fault injection to assess the impact of the ECC technique SECDED on single-bit, double-bit, and triple-bit faults and present a comprehensive investigation of fault behavior, comparing a non-protected with a SECDED scheme. All comparisons are conducted using single-, double-, and triple-bit fault injections. To the best of our knowledge, this is the first study to evaluate the impact of both singleand multi-bit flips on the dominant protection schemes for cache memories. By quantifying the reliability gains and overheads of different protection strategies, this work offers practical insight for RISC-V architects in selecting or assessing cache protection strategies. The main contributions of this paper are enumerated below: 1) We first quantify the rate at which doubleand triple-bit upsets lead to failures and assess the fraction of faults that are completely handled at the hardware level (i.e., they are getting masked due to microarchitectural operations 979-8-3315-3334-2/25/$31.00 ©2025 IEEE or corrected through SECDED) and do not propagate further. 2) We identify the proportion of faults that propagate beyond the hardware-level detection but do not impact software execution (masked at the software level). 3) We finally showcase whether specific software workloads or access patterns make errors more or less visible and determine if certain workloads are more prone to failure due to specific memory access patterns. II. BACKGROUND A. Reliability Concepts The Architectural Vulnerability Factor (AVF) quantifies the probability that a fault within a microprocessor’s hardware structure will result in a visible program error. AVF considers the interplay between the microarchitecture, program structure, and input data, enabling a comprehensive vulnerability assessment across multiple layers, including microarchitecture, architecture, and software [12]. Since AVF is technology-independent, it provides a holistic measure of system vulnerability by encompassing all stages of fault activation and propagation from hardware to software [13]. For example, in an out-oforder microprocessor, a fault in the physical register file may have no impact on execution if discarded due to a pipeline flush. Similarly, even if a fault propagates to the software layer, the affected data might be overwritten or ignored by the algorithm, ensuring correct program execution. Thus, faults can be masked at the hardware or software level. Computer architects typically rely on AVF to determine when and where to integrate redundancy in system designs, especially when evaluating runtime reliability techniques and conducting crosslayer analyses of fault-tolerant mechanisms (e.g., [14], [15]). To this end, in this study, we report AVF values for all results to provide insights into system reliability and fault resilience. B. Statistical Fault Injection (SFI) Designers typically rely on Statistical Fault Injection (SFI) [16] or analytical approaches such as Architecturally Correct Execution (ACE) analysis [12] to evaluate a program’s resilience to transient faults (i.e., soft errors). ACE analysis specifically applies to transient faults, whereas fault injection can assess both transient and permanent faults, by simulating program execution under fault conditions. Both methods aim to estimate the AVF for hardware structures, yet they differ in accuracy, efficiency, and complexity. SFI provides high accuracy by directly observing program behavior, but it requires multiple executions to achieve statistical confidence, making it computationally expensive. In contrast, ACE analysis is faster but requires significant development effort and tends to overestimate AVF [17]. As a widely used reliability evaluation method, SFI enables full-system AVF estimation by analyzing program outputs affected by injected faults. It offers flexibility in accuracy, depending on sample size, and generates failure data through simulation. However, its primary drawback is the high computational cost, from extensive simulations, which may be impractical depending on the model’s complexity. III. EXPERIMENTAL SETUP Through an extensive SFI and simulation-based study, we gather valuable insights that highlight the accuracy improvements our approach brings to vulnerability estimation in modern CPUs. Our analysis is based on 9 long-running benchmark programs, each simulated in an out-of-order (OoO) RISC-V microprocessor, evaluating both L1 instruction and data caches. We conduct experiments on gem5 simulator by injecting one, two, and three faults per run for each cache component, with low error margin and high confidence level, while assessing different protection mechanisms, including parity and SECDED ECC. Our implementation extends cache protection in gem5 by supporting both single-bit parity and SECDED at configurable granularity levels, blockand word-level, making the system flexible for various reliability-performance trade-offs. For each protection scheme, three key functions are implemented: one to encode and store parity or SECDED check bits during data initialization or write operations, another to update these parity/check bits on every write, and a third to verify, with correction in the case of SECDED, on read. A. Experimental Platform Among the various levels of abstraction available for system modeling, the microarchitecture level is the only one that provides sufficient hardware detail while also enabling fullsystem simulation, including the operating system [18]–[22]. Although Register Transfer Level (RTL) modeling offers a more hardware-accurate representation, its low simulation throughput makes it impractical for executing large-scale fault injection studies that involve a complete system stack, including the operating system and I/O interactions. Our microarchitectural modeling is built on the gem5 simulator, a state-of-the-art, flexible, full-system cycle-level simulator [23]–[25]. The gem5 framework provides comprehensive RISC-V ISA support and includes a detailed out-of-order core implementation. Table Ioutlines the configuration of the experimental CPU core used in our gem5 simulations. For fault injection and reliability assessment, we employed the GeFIN fault injection framework [26], which we extended by integrating a new fault generator capable of injecting spatial multi-bit upsets with varying geometries and cardinalities during system execution. For each structure, 500 randomly generated faults are injected, based on the statistical fault sampling method that follows the TABLE I MAJOR SIMULATOR CONFIGURATIONS. Parameter Value ISA RISC-V Pipeline 64-bit OoO (8-issue) L1 Instruction Cache 32KB, 64B line, 128 sets, 4-way L1 Data Cache 32KB, 64B line, 128 sets, 4-way L2 Cache 1MB, 64B line, 2048 sets, 8-way Physical Register File 128 Int; 128 FP LQ/SQ/IQ/ROB entries 32/32/64/128 IQ entries 64 Branch Predictor Tournament Predictor Branch Target Buffer Direct-Mapped, 4K entries RAS Size 16 entries Fig. 1. Examples of multi-bit upset categories in a 3x3 cluster used in our experiments. widely used formulation from [16], ensuring an error margin below 5% with a 99% confidence level. Fault injection at the microarchitecture level provides high observability, enabling precise tracking of where faults occur (e.g., distinguishing between kernel mode vs. user mode or whether corrupted data was used or discarded). Additionally, this approach allows for a detailed analysis of system-wide effects, which we further explore in the following subsection. B. Fault Modeling (Singleand Multi-bit Flips) For the single-bit fault, we follow the widely used formulation from [16] injecting a single bit-flip for each execution based on the uniform distribution. On the other hand, we augment this formulation for spatial multi-bit fault as described below: spatial multi-bit faults can impact neighboring memory cells that share a p-well or n-well, as well as other cells within close proximity. Based on prior research [1], [27], [28], we adopt the fault cluster model introduced in [27], similar to the approach in [1]. In this model, for a cluster size of X rows by Y columns, the generator randomly assigns N fault locations (bit flips) within the defined region. The fault cluster is then randomly placed inside the SRAM array, marking the locations where faults will be injected. This framework allows the configuration of cluster sizes and fault distributions to reflect realistic patterns observed in modern fabrication technologies. Each cluster’s vulnerability is assessed individually, and its contribution to the overall AVF is weighted based on technology-specific characteristics. This level of customization enables evaluations for both current and future technology nodes. Our experiments introduce single-, double-, and triple-bit faults within a 3×3 cluster (fault rates for larger clusters, such as quadruple-bit faults, are negligible, as reported in [1], [27]). To conduct fault injection, we generate a fault mask containing multi-bit errors that are applied to the CPU hardware. In each experiment, we isolate a 3×3 region, randomly select faulty cells within this cluster, and inject faults accordingly. These adjacent bit flips closely resemble fault patterns observed in accelerated beam testing [29]–[32], where multi-bit errors typically manifest in neighboring memory blocks [1]. Fig. 1 presents examples of single-bit, double-bit, and triple-bit faults within a 3×3 cluster, generated by our fault injection model. Unlike the MBU (Multiple Bit Upset) coding approach from [27], which defines the cluster as the smallest possible region encompassing all faults, our methodology allows faults to fit within smaller clusters (e.g., some double-bit errors could be accommodated within a 2×2 cluster). This approach provides a more realistic fault distribution, ensuring that sub-clusters of varying sizes are incorporated into our analysis. IV. METHODOLOGY & EXPERIMENTAL RESULTS A. Total AVF for Every Number of Bit-Flips Fig. 2shows the total AVF for single-bit, double-bit, and triple-bit fault injections. This graph clearly shows that doublebit and triple-bit provide higher AVF than single-bit flips in both L1 data and instruction caches. Surprisingly, L1 instruction cache shows that the impact of double-bit and triple-bit flips are significantly larger than in L1 data cache, suggesting that L1 instruction cache is clearly more prone to multi-bit upsets and may require stronger protection than L1 data cache. B. SECDED vs. No-Protection AVF Fig. 3presents the AVF for double-bit flips in both the L1 data and instruction caches, while Fig. 4shows the AVF for triple-bit flips. These figures clearly illustrate that SECDED provides effective protection (i.e., correction) against both doubleand triple-bit flips; however, there is still room for improvement. The data in these graphs reveal that the SECDED AVF (green bars) is significantly lower than the No-Protection AVF (red bars), demonstrating that SECDED can substantially reduce failure rates. Specifically, in Fig. 3, SECDED reduces the AVF in the L1 data cache more effectively than in the L1 instruction cache, where the SECDED AVF remains relatively uniform across all benchmarks used in this study. Interestingly, in Fig. 4, the L1 instruction cache exhibits a lower SECDED AVF for triple-bit fault injections. This suggests that SECDED becomes more efficient at correcting bit flips as the number of adjacent faults increases beyond double-bit flips. One possible explanation is that multiple-bit flips, particularly triple-bit flips, are more likely to be distributed across different cache blocks or words within a cache block rather than being clustered together as in double-bit flips. Overall, across all benchmarks, SECDED reduces the failure rate by a factor of 2–6x, confirming its effectiveness in mitigating the impact of multiple-bit faults. 0% 10% 20% 30% 40% 50% 60% 70% dijkstra sha bf caudio daudio corners edges smooth cornersL AVF [%] L1D Cache 123 0% 10% 20% 30% 40% 50% 60% 70% dijkstra sha bf caudio daudio corners edges smooth cornersL AVF [%] L1I Cache 123 Fig. 2. AVF for all fault injection (single-bit, double-bit, and triple-bit). 0% 10% 20% 30% 40% 50% 60% 70% dijkstra sha bf caudio daudio corners edges smooth cornersL AVF [%] L1D Cache (Double-Bit) Unprotected SECDED 0% 10% 20% 30% 40% 50% 60% 70% dijkstra sha bf caudio daudio corners edges smooth cornersL AVF [%] L1I Cache (Double-Bit) Unprotected SECDED Fig. 3. AVF for double-bit flips for both L1 data and instruction caches. 0% 10% 20% 30% 40% 50% 60% 70% dijkstra sha bf caudio daudio corners edges smooth cornersL AVF [%] L1D Cache (Triple-Bit) Unprotected SECDED 0% 10% 20% 30% 40% 50% 60% 70% dijkstra sha bf caudio daudio corners edges smooth cornersL AVF [%] L1I Cache (Triple-Bit) Unprotected SECDED Fig. 4. AVF for triple-bit flips for both L1 data and instruction caches. C. Overall Fault Distribution Fig. 5shows the breakdown of the overall fault distribution using SECDED for doubleand triple-bit fault injections and for both L1 data and instruction cache memories. Specifically, for each pie chart, we can see five (mutually exclusive) categories: 1) HW Masked Faults category includes any fault in the L1 data or instruction cache that occurs in an invalid cache block. 2) Non-Critical Corrections category includes all faults that are corrected by SECDED, but the affected words (whether instructions or data) are ultimately masked at the software level. This means that even if this subset of faults were not corrected by the protection scheme, they would never impact the program’s execution. 3) Detectable but Uncorrectable Errors (DUE) masked in SW category includes faults that were detected but could not be corrected; however, they were masked by the software. Thus, although this category consists of DUEs, the program’s execution remains correct. 4) Detectable but Uncorrectable Errors (DUE) causing failure category includes faults that were detected but could not be corrected, ultimately affecting the program’s execution. 5) Needed Corrections category includes all faults that were ultimately corrected by SECDED. This correction is essential for the correct execution of the program. If faults in this category were not corrected by the protection scheme, they would impact the program’s execution. These categories offer key insights into how faults impact the system. Each chart highlights how injected faults are handled, including whether they are masked, corrected, or result in failures. In the L1 data cache with double-bit faults, 31.9% of the faults are masked by the hardware, i.e., they do not propagate further and no SECDED operation was needed. 35.1% of the faults are categorized as non-critical corrections, where SECDED applied error correction even though these faults would have been masked later. 8.5% of faults were detectable but uncorrectable and got masked in software, while only 5.1% resulted in failure. The remaining 19.1% are real needed corrections, meaning SECDED successfully prevented potential failures. This breakdown highlights the combined effectiveness of HW/SW masking and SECDED, although a significant portion of corrections could have been avoided. For the L1 instruction cache with double-bit faults, only 6.8% are hardware-masked, showing higher fault propagation. 31.9% 35.1% 8.5% 5.1% 19.1% L1D Cache (Double-Bit) 6.8% 33.8% 15.6% 8.1% 35.5% L1I Cache (Double-Bit) HW masked faults Non-critical corrections DUE (masked in SW) DUE (causing failure) Needed Corrections 25.9% 20.9% 20.1% 11.3% 23.7% L1D Cache (Triple-Bit) 1.4% 7.4% 45.6% 2.9% 42.6% L1I Cache (Triple-Bit) HW masked faults Non-critical corrections DUE (masked in SW) DUE (causing failure) Needed Corrections Fig. 5. Breakdown of overall fault distribution using SECDED for doubleand triple-bit fault injections and for both L1 data and instruction caches. Non-critical corrections account for 33.8%, while 15.6% of the faults passed the HW/SW interface but were masked at the software level. 8.1% of faults resulted in failures, a slight increase compared to L1 data cache. Meanwhile, a significant 35.5% are genuine SECDED corrections. This suggests that the instruction cache is more vulnerable to double-bit faults that do not get masked across the layers, resulting in more DUEs. However, SECDED corrects a significant amount of them, bringing the rate of failures down to the same level as the L1 data cache. For triple-bit faults in L1 data cache, hardware masking increases to 25.9%., than in the double-bit scenario. A small 20.9% portion of faults fall under non-critical corrections, while a similar 20.1% portion of faults fall under software-masked DUEs, suggesting that SECDED still attempts to correct many errors that may not affect execution at the same rate as the double-bit scenario. However, failures rise to 11.3%, more than twice the double-bit rate. The proportion of needed (i.e., critical) corrections is 23.7%, indicating that SECDED still handles many triple-bit faults effectively. The L1 instruction cache exhibits a notably different pattern, with just 1.4% hardware masking for triple-bit faults. This percentage is much lower than the L1 data cache in the same scenario; however, it aligns with our observations for the doublebit case. Non-critical corrections decrease to 7.4%; however, we can see a notable increase in the software-masked DUEs from 15.6% to 45.6%. Only 2.9% of the faults led to failure, while 42.6% were needed corrections. This suggests that the L1 instruction cache is more effective in correcting triple-bit than double-bit faults, which is attributed to more than 95% of all faults. Nonetheless, nearly half of these faults did not need to be corrected, as they would get masked at the software level. Overall, these results demonstrate that L1 instruction cache is more vulnerable to both doubleand triple-bit faults than L1 data cache. The effectiveness of hardware masking decreases with triple-bit faults, allowing more faults to propagate. While SECDED appears to successfully handle many double-bit and triple-bit upsets in L1 instruction cache, a significant portion would have been masked at the SW level. While in the L1 data cache the corrections are less compared to the L1 instruction cache, resulting in more failures, the corrections that get masked are also decreased. Notably, non-critical and software-masked detectable but uncorrectable errors dominate the L1 instruction cache, exceeding 50% for both fault types. This emphasizes the need for enhanced error protection mechanisms that improve the reliability while avoiding redundant corrections. To further assess SECDED’s capabilities, and provide valuable insights for future designs, we analyze two additional metrics: the effectiveness and the efficiency of the most prevailing protection scheme in cache memories. Fig. 6shows SECDED’s effectiveness against double-bit and triple-bit faults across all the studied benchmarks. The effectiveness is measured by the reduction in AVF compared to an unprotected baseline. This way, we can measure the magnitude, in which SECDED can correct the failures from the doubleand triple-bit faults. At the double-bit faults, SECDED appears to be slightly more effective in L1 instruction cache against the L1 data cache across most benchmarks. This insight aligns with the observations we made in Fig. 5, in which although the instruction cache had more failures compared to the data cache, the corrections balanced the results. At the triple-bit faults, the difference becomes more pronounced, with the SECDED in the L1 instruction cache being more effective than the data cache in all benchmarks but one. In this figure, it is also clear that the SECDED in L1 data cache shows less consistent effectiveness, with one benchmark performing notably worse in both fault scenarios. Efficiency, shown in Fig. 7, is calculated based on the ratio of needed to non-critical corrections—higher efficiency corresponds to fewer unnecessary corrections. In the double-bit case, SECDED shows similar results in both cache memories with the instruction cache appearing as slightly more efficient in most benchmarks. These results support Fig. 5where the instruction cache had nearly twice the needed corrections of the data cache, while non-critical corrections increased by less than 1.5%. At the triple-bit faults, efficiency improves further in L1 instruction cache, which is virtually 100% in most cases. These results derive from a sharp drop in noncritical corrections compared to the double-bit scenario for the instruction cache, but not that substantial for the data cache. These results give SECDED a clear edge in the L1 instruction cache, offering valuable insight into its effectiveness and use in both caches. V. RELATED WORK Sadler and Sorin in [33] presented a comprehensive evaluation of error correction schemes for L1 data caches, comparing parity-protected write-through L1 caches with ECC-protected L2 caches against ECC-protected L1 caches. They introduced the Punctured ECC Recovery Cache (PERC), which combines the advantages of both schemes to enhance performance and reliability. Yoon and Erez in [3] proposed Memory Mapped ECC, a novel technique that reduces the cost of error protection in last-level caches by storing ECC bits within the memory hierarchy as data. This approach minimizes hardware overhead while maintaining strong error correction capabilities. Weaver et al. in [14] explored techniques to reduce the soft error rate in high-performance microprocessors. They introduced methods to selectively squash instructions experiencing long delays and proposed modifications to error detection logic to differentiate between true and false errors, thereby enhancing processor reliability. Zhang et al. in [4] investigated adaptive ECC techniques aimed at improving the yield and reliability of flash memories. Their work focuses on dynamically adjusting error correction strength based on the error characteristics, thereby optimizing performance and reliability. These studies collectively contribute to the advancement of error correction methodologies in various memory hierarchies, offering insights into balancing performance, area, and power considerations. However, none of them presented a comprehensive and detailed study that compares the most prevalent EDC and ECC schemes 0% 20% 40% 60% 80% 100% dijkstra sha bf caudio daudio corners edges smooth cornersL Effectiveness [%] Double-bit SECDED L1D L1I 0% 20% 40% 60% 80% 100% dijkstra sha bf caudio daudio corners edges smooth cornersL Effectiveness [%] Triple-Bit SECDED L1D L1I Fig. 6. Protection effectiveness per benchmark for SECDED for doubleand triple-bit fault injections and for both L1 data and instruction caches. 0% 20% 40% 60% 80% 100% dijkstra sha bf caudio daudio corners edges smooth cornersL Efficiency Ratio [%] Double-bit SECDED L1D L1I 0% 20% 40% 60% 80% 100% dijkstra sha bf caudio daudio corners edges smooth cornersL Efficiency Ratio [%] Triple-Bit SECDED L1D L1I Fig. 7. SECDED efficiency ratio per benchmark for doubleand triple-bit fault injections and for both L1 data and instruction caches. that are commonly used in modern microprocessor chips. Alam et al. in [34] introduced Parity++, a lightweight error correction scheme for last-level caches that provides single error detection for all messages and single error correction for a subset of messages. This approach achieves approximately 9% lower storage overhead and reduced error detection energy compared to traditional SECDED codes. Qureshi and Chishti in [35] proposed FLAIR (FLexible And Introspective Replication), a technique that enables ultra-low voltage operation of SECDEDbased caches by performing two-way replication during testing to maintain robustness and disabling lines with multi-bit failures after testing. FLAIR achieves a Vmin of 485 mV, similar to ECC-8, while incurring minimal storage overhead. Ko et al. in [36] conducted a quantitative evaluation of parityprotected L1 data cache design alternatives to maximize protection against soft errors. They developed an algorithm to accurately model data vulnerability in caches with various parity protection configurations and formulated guidelines for designing power-efficient and reliable L1 data caches. These studies further contribute to the advancement of error correction methodologies in memory hierarchies, offering insights into balancing performance, area, and power considerations. Our study is orthogonal to these works, augmenting the landscape by providing insights into the predominant protection schemes. Manoochehri et al. in [37] presented PARMA+, an accurate and efficient model for estimating cache FIT rates under multibit transient faults. Their work emphasizes the importance of modeling realistic fault patterns and accounting for spatial failure dependencies.Wilkening et al. in [38] introduced an extension of ACE analysis, to estimate the AVF under spatial multi-bit transient faults. They demonstrated that multi-bit AVF behaves differently from single-bit AVF, emphasizing the need for distinct modeling. George et al. in [39] revisit traditional AVF estimation by proposing a scalable probabilistic fault model that accounts for spatial multi-bit upsets in SRAM arrays. While conventional single bit-flip models can significantly overestimate AVF, by using detailed fault injection and microarchitectural simulation, they provide tighter and more realistic vulnerability bounds. VI. CONCLUSION & FUTURE WORK In this paper, we conducted a comprehensive evaluation of cache reliability by analyzing the impact of single-, doubleand triple-bit faults (common in modern manufacturing nodes) under a SECDED protection scheme. Through SFI, we quantified the fraction of errors that are masked at the hardware and software levels, providing insights into how faults propagate through the system. Our findings highlight that while SECDED effectively corrects single-bit errors and reduces failures, in multi-bit injections, a large portion of corrections involve non-critical faults already masked at higher layers, highlighting the need for diligently designed stronger protection in more demanding applications. Future work could explore alternative error correction schemes beyond SECDED, expand the analysis to other architectural components, and consider more complex workloads and system configurations. We have also implemented the technique of bit interleaving and plan to evaluate its effectiveness in combination with ECC for further enhancements in fault resilience. ACKNOWLEDGMENT Research funded by HFRI through grant No 16973 (REDESIGN), supported by research gifts from Meta, AMD, OCP (Open Compute Project), as well as the European Union’s Horizon Europe programme under grant No 101093062 (Vitamin-V), the Chips JU grant No 101097224 (REBECCA), and the EuroHPC JU grant No 101202459 (DARE SGA1). Views and opinions expressed are, however, those of the authors only and do not necessarily reflect those of the European Union. Neither the European Union nor the granting authority can be held responsible for them. REFERENCES [1] A. Chatzidimitriou, G. Papadimitriou, C. Gavanas, G. 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