Non-Volatile Memory Extraction by Deep Learning Methods

1 Non-Volatile Memory Extraction by Deep Learning Methods Raul Quijada∗†, Jofre Pallar` es∗, Roger Dur` a∗, Xavier Formatj´ e∗, Francisco Serra-Graells∗‡,Member, IEEE, and Salvador Hidalgo∗ ∗Institut de Microelectr` onica de Barcelona, IMB-CNM(CSIC) †UGIAT Technologies S.L. ‡Dept. of Microelectronics and Electronic Systems, Universitat Aut` onoma de Barcelona Abstract—Data extraction from large-scale non-volatile memories is a fundamental process in hardware digital forensics that requires extremely high accuracy to minimize manual supervision. Traditional image processing techniques have demonstrated reasonable success, but they are heavily dependent on meticulous sample preparation and image processing. This paper presents an enhanced methodology leveraging the latest advancements in deep learning methods. A comparative analysis is performed between three deep learning models trained with images from mask ROM and OTP fuse memories in 14-nm and 28-nm CMOS technology nodes. The experimental results demonstrate that the proposed approach surpasses in accuracy and offers an almost zero-code versatility. Index Terms—Integrated circuits, CMOS, reverse engineering, NVM, ROM, OTP fuses, deep learning. I. INTRODUCTION NON-VOLATILE memories (NVMs) are integral components of electronic systems, storing crucial firmware and data. Consequently, the ability to reverse engineer NVM contents hold immense importance for applications such as security analysis, competitor study and intellectual property protection. Traditionally, the reverse engineering of NVMs involves invasive attacks, delayering the integrated circuit (IC) die and utilizing image processing techniques to extract their logical values [1]. These methods rely on classical algorithms that primarily focus on image thresholding and basic morphologic analysis [2]. However, as CMOS technology nodes continue to scale, resulting in smaller transistor dimensions and the utilization of larger on-chip memory blocks, the die sample preparation and imaging processes have become more complex. Therefore, the application of traditional image processing algorithms leads to increased errors. Furthermore, the generalization of these methods becomes challenging as they are developed for specific technology cases, requiring adhoc adjustments to adapt to newer scenarios. The remarkable success of artificial intelligence, particularly deep learning, has revolutionized various fields, including image processing. Numerous models have been published focusing on image segmentation, classification, object detection and recognition, among other tasks [3], [4]. These models demonstrate significant potential in tackling complex problems and improving success rates. However, they typically rely on supervised learning, which demands the generation of a considerable dataset (often consisting of several thousand samples) and a training process to teach the model the target task, such as image classification. Nonetheless, the community concerted efforts have led to the development of methodologies to address these challenges. Transfer learning [5], for instance, mitigates the dataset and training process difficulties by leveraging a pre-trained neural network as the backbone of a secondary network. This approach enables the usage of the already acquired knowledge from the pre-trained model to fine-tune the second network using the target dataset. By doing so, it avoids the need to learn low-level descriptors from scratch, as would be the case without transfer learning. Traditional image processing methods for the reverse engineering of NVM contents in modern IC technologies can be tedious, error-prone, as well as time-consuming. This paper explores the application of deep learning techniques to enhance this reverse engineering process, addressing the limitations and drawbacks of traditional approaches. Moreover, the presented work also demonstrates the automation and streamlining of the proposed methodology through extensive experimentation towards the evaluation of its performance and effectiveness at scale. In this sense, the current paper is organized as follows: Section II reviews the sample preparation process of two types of NVMs and identifies the main issues when extracting memory contents from their die images; the three deep learning architecture candidates for NVM extraction are explained in Section III; Section IV describes the experiment in terms of dataset, evaluation and training; the comparative results with traditional image processing are discussed in Section V; and finally conclusions are summarized in Section VI. II. NVM REVERSE ENGINEERING OVERVIEW This work addresses the two most common types of readonly NVM in current embedded systems: mask read-only memory (ROM) and one time programmable (OTP) memory. They differ largely in the physical form in which logical data is stored. Mask ROMs are immutable once the chip is fabricated, as data is physically encoded in the circuit topology and programmed at the chip design stage. They are usually based on arrays of connected or disconnected transistors, whose connection state can be read and determines the binary value of each bit cell. For cost reasons, ROM programming relies on 2 data from a single mask only, and this mask is usually one of the lower layers of metal or interconnection vias of the CMOS backend stack. OTP memory, however, offers a single chance for the chip vendor to program them after production. It is often implemented as a bank of integrated micro-fuses. These fuses can be blown from their initial factory-default state, but once done, its state cannot be reverted. The fuse device itself commonly consists of narrow strips of metal from the lower interconnect layers, which can be melted by applying a high enough current density through them. A. Die Sample Processing The IC samples used in this study were taken from systemin-package (SiP) components of commercially available smartphones. These SiPs contain the phone main processor, in the form of a system-on-chip (SoC), along with a stack of RAM memory chips and a tiny printed circuit board (PCB) that acts as the chip carrier, connecting all these elements together and to the overall package. In order to remove the SoC die, the SiP component was placed in a beaker with fuming nitric acid at 85◦C inside a chemical fume hood. The acid dissolved all the molding compound and most of the PCB, remaining only the RAM and SoC dies along with some thin layer of fiber from the PCB itself. Since the NVM memories in our study were located in the lower layers of the chip stack, the most convenient way to expose them was to process the die from its backside. The X-Prep micro-milling machine from Allied High Tech Products, CA, with 0.7 mm fine diamond metal-bonded tip was used to open a wide aperture on the silicon bulk. The goal was to remove all of the bulk material around the area of interest, leaving only a small thickness of 15 to 20 µm as a safe margin. The SoC was then immersed in 50% aqueous choline hydroxide solution at 100◦C for 1 hour to etch the remaining silicon material over the area of interest. 1) ROM Specific Processing: Figure 1 shows a schematic of the chip cross-section after removing the bulk material from the area around the mask ROM. The memory studied in this work was fabricated in a 28-nm CMOS process node and its binary data is encoded on the presence (or absence) of the metal 1-2 copper vias (VIA1). In order to expose the structures of interest, reactive ion etching (RIE) was applied to remove the silicon dioxide dielectric, shown in gray on the same image. Etching from the top, the RIE attack was stopped when it reached the bottom of the metal 1 structures (M1) of Figure 1. A regular etch recipe was employed for this purpose with a gas mixture of C4HF8, CH4and He following 3/2/2 ratios. After this dry etching step, all the constitutive material over the slabs of the M1 layer was removed and only the metal contact plugs (CONT) remained. Then, a short soft polishing step on planar polisher with soft cloth and 0.05-µm alumina slurry was needed to remove the contact plugs and planarize the M1 slabs. Finally, these slabs and the copper layers underneath were further removed by wet etching using a 46% aqueous solution of nitric acid at 40◦C. Since the ROM VIA1 M1 CONT M2 POLY Fig. 1. Schematic upside-down cross-section of the ROM area after removal of bulk silicon. Data encoded in the layer marked by the red arrow. Drawing not to scale. Fig. 2. SEM image of a mask ROM memory region after sample processing and detail of grid placement. Binary data encoding seen as presence or absence of holes on the grid vertices. Out of grid holes come from polarization vias. information is contained in the VIA1 layer, the logical symbols 1s and 0s can be seen as a hole and no-hole in the scanning electron microscope (SEM) image example of Figure 2. 2) OTP Fuses Specific Processing: After the removal of the bulk silicon, the fuse bank areas show the schematic cross-section of Figure 3. Two sets of OTP memories from different CMOS technology nodes (14 nm and 28 nm) have been studied. For the 14-nm case, a broad ion beam was employed to expose the fuses [6] located in the second metal routing layer (M2), while the 28-nm fuses were processed using the same RIE attack explained for the ROM samples but with longer attack times to reach the bottom side of the M2 layer. Here, it has to be noted that, before the dry etching process, it is advised to clean the sample surface with deionized water or isopropanol followed by regular O2 plasma cleaning. Indeed, this step is critical since the exposed structures are very fragile, and any contact on them can cause huge damage on the sample surface. B. Data Extraction After the sample preparation and SEM imaging, the data extraction process for mask ROMs is performed through the placement of a grid over the memory block to identify each bit location, as depicted in Figure 2. In fact, each grid intersection defines the image patch to be evaluated when detecting the presence or absence of each via. To this extend, via detection 3 VIA1 M1 CONT M2 POLY Fig. 3. Schematic upside-down cross-section of the OTP fuse area after removal of bulk silicon. Data encoded in the layer marked by the red arrow. Drawing not to scale. (a) (b) Fig. 4. Image examples of (a) not altered and (b) blown OTP fuses to define their binary values. Bounding box in both cases is 121 px×222 px. is treated as an image classification task, where presence or absence of vias defines the binary states of the stored data. In the case of OTPs, a template matching technique is chosen to detect the fuses within the region of interest from the memory block. Data extraction is then performed by classifying each fuse as blown or not blown, like in Figure 4. Again, this problem is reduced to image classification: blown fuses must be distinguished from non-blown ones through the detection of a hole, discontinuity or protuberance in their fusing element. Hence, data extraction for both types of NVMs is addressed as an image classification task, which should allow the application of a unified approach. In general, both cases of study do not show high complexity for traditional image processing techniques, but the increasing capacity of NVMs really demands high accuracy, otherwise the manual supervision of the results is unfeasible. In practice, accuracy can be affected by several issues. For instance, Figure 5 shows how problematic can be the detection of some vias that may be easily interpreted as background noise. A similar example is illustrated in Figure 6 for the classification of fuses. Because of the deep learning architectures, original SEM images are first interpolated to the expected input size of 224 ×224 pixels using bilinear interpolation [7]. III. DEEP LEARNING FOR NVM REVERSE ENGINEERING In recent years, deep learning (DL) architectures, particularly convolutional neural networks (CNNs) [8], have dominated the field of digital image processing, demonstrating outstanding performance in tasks such as image classification, segmentation and recognition. However, a newer architecture (a) (b) Fig. 5. Image examples of mask ROM vias for (a) easy and (b) difficult identification cases. Bounding box in both cases is 224 px×224 px. (a) (b) Fig. 6. Examples of noisy images for (a) not altered and (b) blown OTP fuses. Bounding box in both cases is 46 px×166 px. called transformers [9] has emerged and started to challenge CNNs in certain tasks, albeit at the cost of increased complexity [10]. In terms of balance between complexity and task difficulty, CNNs still present a favorable trade-off. The high complexity of these neural networks requires of huge datasets for their training process and also significant computational resources. Transfer learning techniques [5] in image classification overcome these drawbacks by isolating the image feature extractor from the classifier. Therefore, the feature extractor reuse models pre-trained on large datasets that do not need to be retrained, whereas the classifier is built on top of the feature extractor that must be fine-tuned for the particular target task. This strategy allows to reduce the dataset and alleviates the training process. The selection of pre-trained models depends on the architecture type, model size, and the datasets they were trained on. There is a myriad of possible configurations, but for the sake of simplicity we have selected only three different architectures trained on the same dataset, in this case ImageNet [11]. Table I lists a brief overview of the implemented architectures, along with their model size. Our goal is to compare different DL models in terms of performance figures, training complexity and model size. ResNet50 [12] is one of the most popular architectures. It presents several other flavors, like ResNet38, ResNet101 or ResNet152, that differ in the number of layers to have a shallower or deeper model. The depth in DL models improve the abstraction capability but at expenses of more complex networks. In this sense, the most balanced and popular one is still ResNet50. EfficientNetV2 [13] represents a newer architecture that states the best trade-off when comparing performance versus 4 TABLE I DESCRIPTION OF THE IMPLEMENTED DL ARCHITECTURES Network Dataset #Params Model Size Year Resnet50 [12] ImageNet ∼23.5 M 98 MB 2015 EfficientNetV2B0 [13] ImageNet ∼5.3 M 29 MB 2019 ConvNeXtBase [14] ImageNet 88.5 M 339 MB 2022 TABLE II DATASET CHARACTERISTICS Device Id. Mask ROM OTP Ones Zeros Ones Zeros 1 264,440 915,200 20,443 107,841 2 - - 888 7,607 computational costs. Again, there are different submodels that are ranged from B0 to B7 according to their complexity. The B0 flavor has been selected here to have one of the lightest models within the current state-of-the-art references. The last architecture has been chosen in the opposite direction, actually. In this case, the purpose is to have a more complex network oriented towards a better classification accuracy rather than the optimization of the model complexity. ConvNeXt [14] is the most recent and advanced architecture within the above choices. There are also different flavors based on their size. To this regard, ConvNeXtBase model has been selected being not the most complex nor the lightest variant. The implemented classifier built on top of these pre-trained models has been the same for all the experiments to achieve a fair comparison. This classifier is based on a fully connected layer with 1024 hidden units using a ReLU activation function, followed by a fully connected sigmoid layer for binary classification. It has been trained using a RMSProp optimizer with the binary cross-entropy as loss function. IV. EXPERIMENT DESCRIPTION A. Dataset The dataset used in this study comprises mask ROMs and OTP fuses extracted from two different embedded devices, whose data statistics are summarized in Table II. For OTPs, the type of fuses extracted from the first device is illustrated in Figure 6 with a total number around 128.3 K instances. The second device contributes with 8.5 K fuses, whose type is shown in Figure 4. In the case of mask ROMs, the samples are exclusively obtained from the first device, but the number of samples significantly exceeds that of OTP counterparts since its dataset consists of approximately 1.1 M samples. The full dataset has been supervised manually to generate the ground truth. The problematic samples due to defective imaging have been corrected by repeating the acquisition process. B. Evaluation The purpose of the following experiments is twofold. Firstly, we aim to evaluate the performance of the proposed DL models in classifying the binary states of different NVM (a) (c) (b) (d) Fig. 7. Example of OTSUS segmentation for mask ROMs: original image (a) with and (b) without vias, and corresponding results (c,d). types compared to traditional image processing techniques. Secondly, we intend to measure the trade-off between training complexity and performance for the proposed DL architectures. In order to fulfill the first objective, traditional image processing algorithms have been implemented for each NVM type. The classification results obtained from these solutions will serve as the baseline for evaluating the DL models. The implemented algorithm for mask ROMs is based on thresholding using the OTSUS algorithm [15] to separate the foreground objects (vias) from the image background. The segmented mask is then analyzed using the coefficient of variation (CV) as statistical measurement. This metric is defined as the ratio of the standard deviation to the mean value, thus it measures the dispersion of data. In this sense, a higher CV value indicates a greater dispersion. Hence, segmentations with presence of vias offer lower CV values, since the foreground segmentation concentrates all the information. Conversely, in cases where there are no vias, no foreground is present and the segmentation becomes noisy, resulting in a higher dispersion. All these practical cases are illustrated in Figure 7. Finally, we apply two thresholds, one for the CV values and the other one for the mean image intensity, to classify each instance as either via or non-via instances. In the case of OTP fuses, the algorithm follows a similar approach but with a slight variation. Instead of using OTSUS for segmentation, the first derivative of the image is applied to obtain its energy distribution, as illustrated in the examples of Figure 8. This distribution is then measured using the CV metric, while classification is based on its thresholding. Lower values indicate the presence of holes or protuberances that concentrate all the energy, resulting in a lower dispersion. For the second evaluation purpose, the study of the DL architecture trade-off between complexity versus performance is conducted by training the model using different dataset sizes for each NVM type. A favorable trade-off would involve that a small model can achieve a high classification success rate 5 (a) (c) (b) (d) Fig. 8. Examples of OTP fuse image energy distributions along the vertical axis: original patch images for (a) blown and (b) non-blown fuses, and corresponding distribution results (c,d). with a relatively small dataset. The F1-score metric is utilized in all the experiments to quantify the classification performance. This metric is particularly well-suited for imbalanced datasets, as in Table II. C. Training Training of the selected DL models has been conducted using the RMSProp optimizer configured with the same learning rate of 0.001 for all cases. The batch size has been adjusted based on the model size and GPU hardware specifications, i.e. NVIDIA GeForce RTX 2070 SUPER with 8 GB VRAM. The number of epochs has been optimized by analyzing the learning curve during the training process. Finally, data augmentation has been limited to vertical and horizontal flip plus a shift of a maximum 10% in both directions. In order to compare the performance of the three models in terms of training complexity, multiple datasets have been created by varying the number of samples. Consequently, a model is trained for each dataset and architecture type, allowing for a more comprehensive comparison. V. RESULTS AND DISCUSSION A. Traditional Image Processing Performance of the proposed features descriptors for the traditional image processing (TIP) techniques are firstly analyzed. In this sense, the distribution of the ground-truth data is projected based on these descriptors. For mask ROMs, the distribution of samples is represented by the mean and CV metrics, as depicted in Figure 9. The colors in the plot represent the binary classes derived from the ground-truth information, rather than the classifier results. As it can be observed, the data is predominantly grouped into two clusters, indicating good discrimination capability of the descriptors. However, there are several instances where these features fail to accurately group data, which may lead to classification errors. In the case of OTPs, the distribution is along the CVs values of the image energy. This feature shows also a good discriminator performance by means of the two different clusters of Figure 10. Nonetheless, the cluster overlapping highlights the problematic samples that would lead into identification errors. Fig. 9. TIP projection of the mask ROM ground-truth dataset using the mean image intensity and the CV of the segmented mask for vias (yellow) and non-vias (purple) cases. 0.0 0.1 0.2 0.3 0.4 0.5 Coefficient Variation Number of Instances Fig. 10. TIP distribution of the OTP ground-truth dataset based on the energy CV parameter for unblown (orange) and blown (blue) cases. B. Comparative Classification Performance The classification performance results for mask ROMs and OTPs are presented in Table III and IV, respectively. These tables contain all the experiments conducted using both the TIP approach and the three DL model candidates to provide a comprehensive overview of their comparative performance across different training dataset sizes (N), using metrics as Recall, Precision, F1-Score and the total number of classification errors (#Errors). In order to provide a fair comparison, the datasets selected to perform the grid search for the optimal thresholds in the feature descriptors of TIP strategies are exactly the same as the datasets for training the three DL models. The classification performance using TIP demonstrates excellent values for a general-purpose classification task. However, the extremely high success rate required for the reverse engineering of large-scale NVMs is pointed by the number of errors that must be supervised, which is still significantly high for a manual review. Although OTPs show lower values, this is due to the low count of total samples. In fact, the best F1-score for OTP fuses is worse than for mask ROMs. Anyway, it is worth to highlight that the descriptor performs well for OTPs even with smaller datasets compared to DL models. For large datasets, DL models consistently outperform TIP 6 TABLE III CLASSIFICATION PERFORMANCE - MASK ROMS TIP N Recall Precision F1-Score #Errors 1 99.93% 85.81% 93.33% 151,747 5 99.85% 97.56% 98.69% 24,182 50 99.72% 99.18% 99.45% 10,047 100 99.65% 99.65% 99.65% 6,300 500 99.62% 99.69% 99.66% 6,181 ResNet50 N Recall Precision F1-Score #Errors 1 83.52% 99.99% 91.01% 150,839 5 85.13% 99.99% 84.91% 136,099 50 95.35% 99.99% 99.01% 42,554 100 98.80% 99.99% 99.62% 10,990 500 99.86% 99.99% 99.92%1,294 EfficientNetV2B0 N Recall Precision F1-Score #Errors 1 93.16% 99.99% 96.46% 62,542 5 98.81% 99.96% 99.38% 11,194 50 99.01% 99.94% 99.47% 9,506 100 99.00% 99.97% 99.48% 9,385 500 99.51% 99.99% 99.75% 4,474 ConvNeXtBase N Recall Precision F1-Score #Errors 1 97.79% 99.99% 98.88% 20,183 5 97.58% 99.99% 98.77% 22,075 50 99.26% 99.99% 99.62% 6,821 100 99.48% 99.96% 99.72% 5,073 500 99.80% 99.75% 99.77% 4,066 solutions for all architectures, except for mask ROMs using ConvNeXt. The high complexity of its image descriptor requires larger datasets to converge to a better solution. Nonetheless, ConvNeXt performs remarkably well with small datasets, highlighting its potential to model the target task with limited samples. Another interesting observation from the experiment results is the performance of the different architectures as the training dataset size changes. For datasets larger than 100 samples, most DL models exhibit superior performance compared to TIP solutions for both types of memories. Additionally, the classification performance evolution can be applied to iterative dataset generation using weakly supervised methods. A model trained with a small number of samples can be used to label a larger dataset for training a new model. This larger dataset only requires manual supervision for samples with low confidence. For a comparison in terms of computation costs, Table V shows the required resources and processing time of the different implemented architectures. Although EfficientNetV2B0 slightly underperforms compared to ResNet50, it is the lightest TABLE IV CLASSIFICATION PERFORMANCE - OTP FUSES TIP N Recall Precision F1-Score #Errors 1 99.96% 81.02% 89.50% 5,002 5 99.93% 90.93% 95.22% 2,139 50 99.99% 95.87% 97.85% 936 100 98.84% 99.52% 99.18% 346 500 99.63% 99.33% 99.45% 220 ResNet50 N Recall Precision F1-Score #Errors 1 84.31% 19.05% 31.08% 79,745 5 92.27% 78.64% 84.91% 6,994 50 98.25% 99.77% 99.01% 420 100 99.87% 99.37% 99.62% 160 500 99.41% 99.84% 99.63%157 EfficientNetV2B0 N Recall Precision F1-Score #Errors 1 78.31% 18.36% 29.75% 78,890 5 18.74% 99.20% 31.53% 17,364 50 98.46% 98.75% 98.61% 591 100 99.86% 98.51% 99.18% 350 500 99.93% 99.18% 99.56% 188 ConvNeXtBase N Recall Precision F1-Score #Errors 1 71.35% 18.03% 28.79% 75,289 5 91.04% 89.51% 90.27% 4,185 50 99.64% 97.65% 98.63% 587 100 99.46% 98.74% 99.10% 385 500 99.93% 97.49% 98.70% 561 model in terms of GPU resource usage. Conversely, ConvNeXt base is the most resource-intensive and complex model. In terms of inference time, TIP is the fastest as it involves significantly fewer mathematical operations compared to DL models. ResNet50 offers the best classification performance for both types of memories being the fastest DL model in the prediction process, but it requires more GPU memory for training. VI. CONCLUSIONS The proposed deep learning-based approach for the reverse engineering of NVM contents showcases remarkable classification performance, surpassing traditional image processing solutions. Deep learning also offers unparalleled versatility, enabling its application to various types of memory or devices, like mask ROMs and OTP fuses in modern CMOS technologies. Indeed, when facing a new case study, only training a new model with a labeled dataset specific to the problem is required. This approach can be considered a zero-code solution, as no coding is necessary to analyze a new device or 7 TABLE V COMPUTATIONAL COSTS Training dataset 500 and 20 epochs Architecture GPU Memory Time ResNet50 7450 MB 199 s EfficientNetV2B0 1297 MB 195 s ConvNeXtBase 6929 MB 439 s Inference for 1K images Architecture GPU Memory Time TIP average - 11 s ResNet50 4881 MB 112 s EfficientNetV2B0 1297 MB 173 s ConvNeXtBase 6929 MB 251 s memory type. In contrast, traditional image processing entails developing a new image descriptor for each new case, which can be time-consuming and resource-intensive. Dataset generation poses the greatest challenge when utilizing supervised learning algorithms. For this reason, part of the study has been conducted to explore different training dataset sizes in order to determine the optimal number of samples for the target classification task using transfer learning techniques. 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