Design and Analysis of Second and Third Order PLL at 450MHz

International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 DOI : 10.5121/vlsic.2011.2109 97 Design and Analysis of Second and Third Order PLL at 450MHz B. K. Mishra 1 , Sandhya Save 2 , Swapna Patil 1 1 Department of Electronics and Telecommunication Engineering,TCET, Mumbai University, India [email protected] [email protected] 2 Department of Electronics Engineering, TCET,Mumbai University, India [email protected] A BSTRACT Designing of an analog circuit satisfying the design constraints for desired application is a challenging job. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. In this paper, selection and design for Second order and third order PLL suggested using MATLAB, Simulink as a simulation tool. The simulated results for the design PLL at 450 MHz indicates good accuracy when the behavior model is compared with the mathematical model. Finally the performance of PLL is tested and calculated for parameters like lock time, lock range, Bandwidth. K EYWORDS PLL, Charge Pump PLL, Baseband PLL, VCO, Simulink, CAD, EDA tool. 1. INTRODUTION Phase locked loop is an excellent research topic as it covers many disciplines of electrical engineering such as Communication Theory, Control Theory, Signal Analysis, Noise Characterization, Design with transistors and op-Amps, Digital Circuit design and non-linear circuit analysis. The first PLL ICs came in existence around 1965 was built using purely analog devices. Recent advances in integrated circuit design techniques have led to an increased use of the PLL as it has become more economical and reliable. Now a whole PLL circuit can be integrated as a part of a larger circuit on a single Chip i.e SoC [1] [13]. MATLAB simulink [15] is effective tool to get prior idea about PLL parameters to fulfill requirements before actual chip design. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 98 Phase-locked loops [17] are known to have plenty of applications, from low-frequency ones, e.g., motor controller [18] and synchronous power converters [19], to RF applications, e.g., frequency synthesizers [2][20]. For low-speed applications, phase-locked loop (PLL) systems can be implemented in DSP [19], [21]. On the other hand, for high-speed applications, PLL systems are realized in analog way [18], [20]and in digital way [3]. The accuracy of the required frequencies is very important in these designs as the performance is based on this parameter [1] [13] [4]. As the name suggests, the phase locked loop operates by trying to lock to the phase of a very accurate input signal through the use of its negative feedback path. A basic form of a PLL consists of three fundamental functional blocks namely Phase Detector (PD), Loop Filter (LF), Voltage Controlled Oscillator (VCO).The block diagram of PLL is shown in the figure 1.The different types of PLL can broadly categories as Analog PLL, Digital PLL and Hybrid PLL. Figure 1. The block diagram of PLL The presence of two nonlinear devices as phase-detector and VCO, in closed loop makes PLL, a nonlinear device. Therefore in this work, the performance of PLL designed for 450 MHz frequency is tested against VCO sensitivity, free running frequency, amplitude and phase of VCO, Loop filter transfer function. The remainder of the paper is organized as follows. In Section 2, the basic of Linearized model of PLL and structure of third order PLL is explained. The equation for lock time ( L T ), Bandwidth ( BW ) and lock range ( L w ∆ ) is listed. In section 3, the frame for PLL design using Matlab/Simulink is explained. In section 4, the obtained results were compared with theoretical calculation. 2. LINEARIZED PHASE DOMAIN MODEL FOR PLL The generalized loop response for the higher ordered PLL can be written as equation 1[1], [2], [14] ( ) ( ) 0p v i p v K K F s s K K F s θ θ =+ ……………………... (1) Where, 0 θ = the output phase in radians i θ = the input phase in radians p K =the phase detector gain in volts per radian International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 99 v K = the VCO gain in radians per volt-second ( ) F s = the loop filter transfer function (dimensionless) The loop characteristics can be controlled by changing different types of loop filters then the order of PLL is 1 n + where n order of the loop filter. The simplest filter is a one-pole RC circuit. The loop transfer function in this case is given an equation 2. ( ) 1 1 F s sRC =+ ……………………………... (2) The loop response for 2 nd order PLL can be found out using equation (2), (3). 0 2 p v p v i K K RC K K s s RC RC θ θ = + + ……………………….… (3) Comparing the equation (3) with standard transfer function equation of second order filter we get, 2 1 p v K K RC ξ = ……………………………. (4) p v n K K RC ω = ……………………………….. (5) Where, RC =Time constant in sec. ξ = damping ratio n ω = natural frequency For sinusoidal phase detector K P is ½ of peak to peak voltage of PD output [4]. Using equation (3), (4), (5) we get, Lock time, 2 L n T ω = Π ………………………….(6) Lock range, L n w ξω ∆ = Π ……………………...(7) Bandwidth, ) ( 1/2 1/2 2 2 4 1 2 2 4 4 n BW ω ξ ξ ξ   = − + − +   ..(8) Using these mathematical model formulae, the corresponding values for lock time, Lock range, Bandwidth is calculated for different types of PLL, Baseband PLL, Charged Pump PLL [2]. While designing charged pump PLL the pump current p I and selection of C( mostly in nF) are the International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 100 important design factor to be considered. Typically for most of the designs value of Ip is 100 A µ to 1 mA [2] [7] [4]. p P n C KvcoI Π =2 ω …………………………………(9) Π =2 KvcocI R pp p ξ …………………………(10) As expected, if Rp=0, then ζ =0. With complex poles, the decay time constant is given by equation (11) n ξω 1 = vcopp KIR Π 4 …………………………..(11) As seen from the closed loop transfer function of second order PLL. [2] if we decrease the vcop KI * , the gain crossover frequency decreases (or shifts toward the origin), degrading the phase margin. But this compensated type PLL suffers from a drawback. Since the charge pump drives the series combination of P R and P C , each time a current is injected into the loop filter, the control voltage experiences a large jump. Even in the locked condition, mismatches between I UP I and DOWN I and the charge pump injection and clock feed through of S1 and S2 introduce voltage jump in CONT V as shown in figure 3. Figure.2. Structure of third order charge pump PLL International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 101 Figure. 3.Addition of C2 to improve stability Design and analysis of third order PLL is important as higher order design are concerns with system stability designed for wide applications. Transfer function for second order filter for charge pump PLL is given by equation (12) . The structure of third order charge pump PLL and System model of charge pump PLL block diagram shown in figure 2,figure 4 respectively. Transfer function of loop filter is given by equation (12) { 2 1/ }//1/ P Rp C S C S + …………………….. (12) The open loop and closed loop transfer function is given by equations (12), (13). ( ) 1 03 2 1 2 1 2 ( 1) 2 ( ) p vco I K sRC G s S RC C S C c π + =+ + ……..…………….… (13) 1 3 1 1 2 2 ( ) 2 2 p vco p vco c p vco p vco sI K R I K C G s sI K R I K s mRC C + Π Π = + + Π Π ………….......... (14) Where, p I is the current of charge pump, vco K is the VCO gain constant m= 1 2 c c is the capacitance ratio. Usually, C2 is much smaller than C1 (m«1). Comparing equation (13) with equation (14) will get ξ , n ω and m. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 102 2 3 2 2 2 ( ) 2( 1) n c n n s G s m s m s ξω ω ξ ω ω + = + + + ………… (15) Figure 4.System model of charge pump PLL block diagram 3. FRAME WORK FOR PLL DESIGN The set up arrangement done for PLL( Charge Pump PLL )is parameter measurement is shown in the figure 5. 3.1. Setup for PLL Simulation in Simulink The input provided in set up is the order coefficient of Loop filter. For e.g., using the transfer function of Loop filter incorporated in automated program written in Matlab which guides to find the input to find the proper range of input applied to the set up assembly to get desired output. Similarly for other input parameters Like, VCO gain in Hz/volts and quiescent frequency were found out. For analysis of third order PLL setup used is almost same as second order PLL, Input for assemble are Transfer Function of loop filter, Kvco, quiescent frequency of VCO. Figure 5. Setup for measurement of PLL parameters in Simulink International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 103 3.2Measurement of PLL parameters The simulation is done in Simulink/Matlab 2009b on Intel processor core 2 Duo processor@ 2.93 GHz with 1.96GBRAM .The simulated results for filter output ,phase detector output and VCO outputs can seen in real time using scope in Simulink. The obtained VCO output filter output, Phase detector output for Charge pump PLL is shown in figure 7, figure 8 and figure 9 respectively. Similarly filter output (control signal),PD output and reference signal & VCO output shown in figure 10,11,12 respectively. These obtained data at least 5000 samples per result were stored in workspace. The peak value i. e 1 A and next peak value 2 A are found out from these samples using program written in Matlab [9], [10]. Using these retrieved values ξ and n ω was found out using the formulae figure 6 [4].The automated program files guides to find calculated and observed value for given RC time constant. Figure 6. Measurement of PLL ( ) ( ) 2 2 ln 1/ 2 ln 1/ 2 A A A A ξ =   Π +   …………………(11) 2 2 1 n T ω ξ Π =− ……………… (12) Where, 1 A =First maximum peak amplitude 2 A = First minimum peak amplitude International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 104 Figure 7. Charge pump PLL filter output Figure 8. Charge pump PLL Phase detector output Figure 9. Charge pump PLL VCO output and input signal Figure 7,8.9 shows Charge pump PLL filter output, Charge pump PLL Phase detector output and Charge pump PLL VCO output and input signal respectively these results is obtained by design and simulation of second order charge pump PLL ,shows once the refernce signal is tracked then phase detector outputs with minimum phase differnce between input and output signal. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 105 Figure 10. Third order Charge pump PLL filter output Figure 11. Third order Charge pump PLL Phase detector output Figure 10, 11, 12 shows Third order Charge pump PLL filter output, Phase detector output and VCO output and input signalwith 90 = ∆ θ respectively. It can be obsered that when 90 = ∆ θ ,and the reference signal is track PD output is zero. Figure 13 shows the step response of third order system for different damping factor. It can be obsered that ,as the damping factor of the system increases the settling time decreases. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 112 Table 1. Comparative result table for all types of PLL Table 2.Simulation results for 0.707 and 0.9 Parameter ξ =0.707 ξ =0.9 Settling time 125.7nsec 98.76nsec Overshoot% 1.18% 0.0000347% m 0.000083 0.00001 Loop gain 4.575Mhz 7.9056Ghz 5. CONCULSION Design and Analysis of PLL parameters using Mathematical model and the behavior model of PLL is tested with MATLAB simulink tool . The effect on parameters of second order and third International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011 113 order PLL at 450Mhz is discussed in this work. Simulation results show that ξ and n ω affect the behavior of different PLL types. From the observed results, it is found out that , Linearzed PLL is not used widely in communication applications due to constraint of smaller lock range for higher value of K VCO. The use Baseband PLL is restricted to for narrow BW applications such as GPS systems in mobile communication whereas, Charge pump PLL can be widely used for many communication application due to its advantage as it provides wider Bandwidth, less setting & wider lock range. Design and simulation of third order PLL by propose novel method is more efficient to provide stability of system using Matlab/ Simulink model and this novel method shows very good precision in designed parameters for wider communication applications. 6. REFERENCES [1] A. B. Grebene, The monolithic phase-locked loop - a versatile building block, IEEE Spectrum, vol. 8, pp.38-49, March 1971. [2] B. Razavi (ed.), Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE 2003. 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