Plasma Behavior of SiC MOSFETs with Engineered Substrates During Reverse Recovery

© 2025 IEEE. This is the author’s version of the work accepted for publication in 2025 37th International Symposium on Power Semiconductor Devices and ICs (ISPSD). The final version of record is published in IEEE Xplore at: https://doi.org/10.23919/ISPSD62843.2025.11117512 Plasma Behavior of SiC MOSFETs with Engineered Substrates during Reverse Recovery Mohamed Alaluss Chair of Power Electronics Chemnitz University of Technology Chemnitz, Germany [email protected] Madhu Lakshman Mysore Chair of Power Electronics Chemnitz University of Technology Chemnitz, Germany [email protected] Clemens Herrmann Chair of Power Electronics Chemnitz University of Technology Chemnitz, Germany [email protected] Sudhanshu Goel Robert Bosch GmbH Reutlingen, Germany [email protected] Ahmed Elsayed Robert Bosch GmbH Reutlingen, Germany [email protected] Thomas Basler Chair of Power Electronics Chemnitz University of Technology Chemnitz, Germany [email protected] Abstract—The plasma density and distribution are crucial factors in optimizing the reverse recovery behavior of power semiconductor devices, particularly under conditions of high temperature and current density. This paper investigates the impact of hydrogen ion implantation during the manufacturing process of SiC engineered substrates on the reverse recovery performance of MOSFETs, comparing them to devices based on monocrystalline substrates. The results indicate a lower reverse recovery charge, faster plasma formation, and a reduced charge carrier lifetime in the engineered substrates. Electro-thermal simulations further support these findings by demonstrating a lower carrier density. Index Terms—SiC MOSFET, SiC engineered substrate, body diode, reverse recovery, carrier lifetime, TCAD I. INTRODUCTION The reverse recovery characteristics of silicon carbide (SiC) MOSFETs are critical for optimizing performance, particularly in achieving fast, efficient switching with minimal losses. During the reverse recovery phase, the depletion of stored charge accumulated during the dead time introduces additional losses, affecting both the active and complementary switches. Various factors influence the reverse recovery charge, including minority carrier lifetime, operating temperature, and load current. As temperature increases, the ionization of pdoped regions and the prolonged carrier lifetime lead to higher plasma density. These effects negatively impact reverse recovery performance, resulting in increased switching losses, pronounced snappiness, and higher induced voltages. Optimizing plasma behavior is essential to minimize losses and enhance efficiency and robustness. A proven method for This work has been carried out within the FastLane project. The project is supported by the Chips Joint Undertaking (JU) and its members, including top-up funding by Austria, France, Germany, Romania, Slovakia, under grant agreement No 101139788. silicon PIN diodes involves local lifetime control through the introduction of recombination centers, which optimize plasma distribution. Recent studies suggest that this approach is also applicable to silicon carbide devices [1] [2], resulting in improved plasma distribution and a corresponding reduction in reverse recovery charge. However, this reduction is accompanied by an increase in the on-state voltage drop. A recent study demonstrated a reduction in reverse recovery charge without impacting on-state voltage drop by using SiC engineered substrates based on SmartCutTM technology [3]. The implantation of hydrogen ions during the manufacturing process of bonded substrates, which is used to split the donor wafer, leads to the formation of point defects that reduce the effective carrier lifetime [5]. This study investigates plasma behavior as a function of current density, temperature, and dead time. A novel method for more accurate determination of carrier lifetime is proposed. Furthermore, electro-thermal simulations provide additional insights into the plasma behavior. II. DEVICE STRUCTURE AND METHODOLOGY SiC MOSFETs with a voltage class of 1200 V and a trench structure were fabricated using a SiC engineered substrate based on SmartCutTM technology. This technology combines a thin, high-quality monocrystalline SiC layer with a thick, low-resistivity polycrystalline SiC carrier [4]. For comparison, reference SiC MOSFETs were fabricated on a monocrystalline substrate. Both types of SiC MOSFETs were processed under the same conditions, ensuring the same cell design, n-base region, and buffer layer. This enables the investigation of the substrate’s impact on plasma behavior during reverse recovery. The measured static C-V characteristics of the parasitic capacitances in the devices are shown in Fig.1. The capacitances demonstrate similar trends with respect to the applied drainsource voltage (VDS), indicating that the capacitive switching behavior remains comparable under similar conditions for both technologies. 0.1 1 10 100 1000 10p 100p 1 n 10n C a p a c i t a n c e [ F ] VD S [ V ] R e f e r e n c e S i C e n g i n e e r e d s u b s t r a t e Ci s s Co s s Cr s s Fig. 1. Comparison of the measured C-V characteristic for both technologies. The reverse recovery behavior of the body diode in the SiC MOSFET was investigated using a double-pulse setup. Both the high-side and low-side switches utilized the same type of MOSFET. The DC-link voltage (VDC) was adjusted to 800 V, and the gate-source voltage (VGS) was set to −10 V to eliminate the influence of the n-channel during the dead time (tdead). A dead time of 1 µs was selected to ensure complete plasma formation. Measurements were conducted at current densities reaching up to three times the nominal value and temperatures up to 200°C. A coaxial shunt was used for current measurement, while voltage was measured using a passive probe connected to a separate oscilloscope. Fig. 2 shows the results obtained at maximum current density for both technologies. The reverse recovery charge (QRR) was determined according to JEDEC JEP201 standards (see Fig. 2). The determined QRR consists of capacitive stored charge (QC) and stored charge from charge carriers (QPlasma). The capacitive charge is derived from the device’s output capacitance Qoss, determined by the Coss(V) curve (Fig. 1) and the applied VDC. Additionally, the parasitic capacitance of the load inductance − 8 0 − 4 0 0 40 80 120 160 − 0 . 8 − 0 . 4 0 . 0 0 . 4 0 . 8 1 . 20 250 500 750 1000 1250 1500 jS ( D i o d e ) [ k A / c m ² ] t i m e [ n s ] dif/ d t = - 5 k A / µ s tc 1 e x t r a c t i o n o f QR R VD S ( D i o d e ) [ V ] R e f e r e n c e S i C e n g i n e e r e d s u b s t r a t e 9 8 % VD C Fig. 2. Comparison of the reverse recovery behavior at VDS = 800 V, jS= 1 kA/cm², VGS =−10 V,tdead = 1 µs, and Tvj = 200°C. and the test circuit contributes further to QC. To accurately quantify QC, measurements were conducted during the initial pulse of the double-pulse test according to JEDEC JEP201 [6], ensuring no bipolar charge component in the absence of current. A QCof 325 nC was determined for the reference device and 328 nC for the SiC engineered substrate based device. III. EXPERIMENTAL RESULTS AND DISCUSSION A. Plasma Stored Charge The plasma stored charge was initially analyzed as a function of current density and temperature for both technologies. Fig. 3 illustrates the temperature dependence of QPlasma, corrected by the previously mentioned QC, at nominal and three times the nominal current density. 20 40 60 80 100 120 140 160 180 200 220 0 . 0 0 . 4 0 . 8 1 . 2 1 . 6 2 . 0 2 . 4 R e f e r e n c e S i C e n g i n e e r e d s u b s t r a t e QP l a s m a [ µ C ] T e m p e r a t u r e [ ° C ] 44% 30% jnom 3x jnom Fig. 3. Plasma stored charge (QPlasma) as a function of temperature (T) for different current densities (j) at VDS = 800 V, VGS =−10 V, and tdead = 1 µs. In general, QPlasma increases with temperature due to the higher ionization degree of the p-doped regions and the enhanced effective carrier lifetime (τeff). However, the increase observed in the device based on the SiC engineered substrate is smaller, resulting in a lower QPlasma compared to the reference. This difference becomes more pronounced with increasing temperature and current density. Moreover, a significant increase in QPlasma for the SiC engineered substrate based device is only observed at temperatures above 100°C. Since QPlasma is directly proportional to both current and effective carrier lifetime, the observed reduction in QPlasma for the SiC engineered substrate based device under identical test conditions can be attributed to a lower effective carrier lifetime. B. Dead Time Dependency A deeper understanding of the plasma formation process during forward recovery in both technologies can be gained by analyzing the relationship between the reverse recovery charge and the dead time. Fig. 4 shows the ratio of QRR to QC as a function of dead time at the nominal current density and at three times the nominal value, measured at a Tvj of 200°C. Plasma formation occurs with a lower time constant for the SiC engineered substrate, referred to as the forward recovery time constant (τFR), compared to the reference device. At three times the nominal current, τFR is reduced by 33% for the 100 1000 10000 3 4 5 6 7 8 QRR/QC td e a d [ n s ] R e f e r e n c e S i C e n g i n e e r e d s u b s t r a t e Fig. 4. Ratio of QRR to QCas a function of dead time (tdead) for different current densities at Tvj = 200°C. SiC engineered substrate based device, resulting in plasma saturation at shorter dead times. At nominal current density, the difference is less pronounced. Plasma saturation during forward recovery is achieved only when an equilibrium between charge carrier generation and recombination is reached. This process is influenced by the carrier lifetime and emitter efficiency, with a shorter carrier lifetime leading to faster plasma saturation. Hence, the faster plasma saturation observed in the SiC engineered substrate based device is primarily attributed to a lower carrier lifetime. C. Carrier Lifetime The observed reduction in QPlasma and the faster plasma formation in the SiC engineered substrate based device compared to the reference device indicate a strong dependence on carrier lifetime. The effective carrier lifetime τeff, determined from the relationship between QPlasma and load current, ranges from 10–15 ns for the reference device and 5–10 ns for the SiC engineered substrate based device, based on the measurements in Fig. 3. Thus, τeff is lower for the SiC engineered substrate based device. However, this value is underestimated compared to the expected carrier lifetime in conduction mode due to surface recombination effects. Moreover, τeff primarily reflects the carrier lifetime in the heavily doped emitter region, making it significantly shorter than the bulk carrier lifetime in the lightly doped region [7]. To propose an additional approach for evaluating the carrier lifetime, similar to the open-circuit voltage decay (OCVD) method, the behavior of VSD is analyzed during the transition from bipolar to unipolar current conduction in the third quadrant, i.e., during plasma depletion. For this purpose, the device is continuously operated under a constant current (also to avoid di/dt effects influencing the measurement), while the gate voltage is switched between VGS = 18 V (channel open - unipolar mode) and −10 V (channel closed - bipolar mode). Fig. 5 shows the behavior of VSD during the transition from bipolar to unipolar operation for both technologies at a temperature of 150°C and approximately the nominal current density. For the reference device, a slightly higher current density was required to achieve the same device temperature. An exponential function was fitted to the voltage waveform to extract the charge decay time constant (τCD). The SiC engineered substrate based device exhibits a faster charge decay, as indicated by a faster voltage rise, with τCD being 40% smaller than that of the reference device. This aligns with a 37% decrease in QPlasma under comparable conditions (see Fig. 3). The reduced voltage drop in unipolar mode is attributed to the lower resistance of the highly doped poly-SiC layer [3]. 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 0 . 8 1 . 0 1 . 2 1 . 4 1 . 6 1 . 8 2 . 0 − 1 2 − 8 − 4 048 1 2 1 6 2 0 0 . 0 0 . 2 0 . 4 0 . 6 0 . 8 VS D [ V ] t i m e [ µ s ] τ C D ≈ 4 1 5 n s τ C D ≈ 6 9 5 n s e x p o n e n t i a l f i t jS [ k A / c m ² ] VG S [ V ] R e f e r e n c e S i C e n g i n e e r e d s u b s t r a t e u n i p o l a rb i p o l a r Fig. 5. Forward voltage drop during the transition from bipolar to unipolar third quadrant DC current conduction for both technologies at approx. nominal current density, with Tvj = 150°C, and VGS =+18 V/−10 V. D. Electro-Thermal Simulation Results To analyze the plasma distribution within the device based on substrate technology and its impact on reverse recovery charge reduction, electro-thermal simulations were performed using Synopsys TCAD [8]. A half-cell 1200 V SiC MOSFET with a trench cell structure was utilized to reproduce the fundamental behavior. The substrate-specific characteristics were incorporated by introducing lifetime-killing traps in the bonded mono SiC layer and adjusting the doping density for the poly SiC layer as described in [3]. The reverse recovery behavior of both technologies was initially simulated at three times the nominal current density and a temperature of 200°C, using dead times of 100 ns and 1000 ns. As shown in Fig. 6, longer dead times result in higher reverse recovery current peaks and longer recovery times for both substrates, consistent with measurements. However, the total charge is lower in the SiC engineered substrate based device compared to the reference device, which aligns with experimental measurements (see Fig. 4). Plasma formation in both substrate technologies was examined by analyzing electron and hole distribution at various time points within a 1 µs dead time. As shown in Fig. 7, time point t1marks the onset of bipolar current conduction. At t1, the SiC engineered substrate device exhibits a slightly higher electron density in the drift region compared to the reference, which is attributed to increased doping from the poly-SiC layer. This enhances electron injection and increases the initial hole density. After 50 ns (t2), the carrier density near the p-region become similar for both substrates. However, the − 8 0 − 6 0 − 4 0 − 2 0 0 2 0 4 0 6 0 8 0 1 0 0 − 0 . 8 − 0 . 4 0 . 0 0 . 4 0 . 8 1 . 20 250 500 750 1000 1250 1500 jS ( D i o d e ) [ k A / c m ² ] t i m e [ n s ] VD S ( D i o d e ) [ V ] R e f e r e n c e S i C e n g i n e e r e d s u b s t r a t e td e a d : 1 0 0 n s 1000 ns Fig. 6. Comparison of the simulated reverse recovery behavior at three times the nominal current density for different dead times at VDS = 800 V, VGS =−10 V, and Tj= 200°C. 1 E 1 0 1 E 1 2 1 E 1 4 1 E 1 6 1 E 1 8 1 E 2 0 1 E 1 4 1 E 1 6 1 E 1 8 1 E 2 0 h o l e d e n s i t y [ c m - 3 ] C h i p t h i c k n e s s [ a . u . ] t1 = 0 µ s t2 = 0 . 0 5 µ s t3 = 0 . 2 µ s t4 = 0 .3 µ s t5 = 1 µ s e l e c t r o n d e n s i t y [ c m - 3 ] p - r e g i o n d r i f t r e g i o n b u f f e r s u b s t r a t e R e f e r e n c e S i C e n g i n e e r e d s u b s t r a t e l i f e t i m e k i l l i n g t r a p s Fig. 7. Comparison of the electron and hole density for different time points at three times the nominal current density, with VGS =−10 V,Tj= 200°C, and tdead = 1 µs. SiC engineered substrate device shows a lower carrier density toward the buffer due to the lifetime-killing effect, resulting in a reduced penetration depth. Hydrogen ion implantation into the mono-SiC layer, followed by annealing, increases the concentration of Z1/2 and other recombination centers, which reduce electron lifetime and limit carrier injection [5]. Consequently, the hole density decreases, particularly at the drift/buffer interface. During forward recovery, the electron and hole densities in the drift region continue to increase. Fig. 8 shows the hole distribution in the drift region at different time points for both technologies to improve visibility. The hole concentration saturates earlier in the SiC engineered substrate based device compared to the reference. In the reference device, saturation occurs after 350 ns, whereas in the SiC engineered substrate based device, it occurs after 250 ns. This earlier saturation is attributed to the lower effective carrier lifetime and the lower emitter efficiency. These findings align well with the measurements shown in Fig. 4. According to the trade-off between plasma density and voltage drop in bipolar devices, MOSFETs based on SiC engineered substrates are expected to exhibit a higher voltage drop in the third quadrant during bipolar operation due to the 3 E 1 6 4 E 1 6 5 E 1 6 6 E 1 6 7 E 1 6 8 E 1 6 9 E 1 6 1 E 1 7 8 E 1 6 8 . 4 E 1 6 8 . 8 E 1 6 9 . 2 E 1 6 9 . 6 E 1 6 1 E 1 7 h o l e d e n s i t y [ c m - 3 ] C h i p t h i c k n e s s [ a . u . ] t1 = 0 . 1 0 µ s t2 = 0 . 1 5 µ s t3 = 0 . 2 0 µ s t4 = 0 . 2 5 µ s t5 = 0 . 3 0 µ s t6 = 1 µ s t1 = 0 . 1 5 µ s t2 = 0 . 2 0 µ s t3 = 0 . 2 5 µ s t4 = 0 . 3 0 µ s t5 = 0 . 3 5 µ s t6 = 1 µ s t S i C e n g i n n e r e d s u b s t r a t e t R e f e r e n c e h o l e d e n s i t y [ c m - 3 ] Fig. 8. Comparison of hole density in the drift region at three times the nominal current, with VGS =−10 V,Tj= 200°C, and tdead = 1 µs. lower plasma density. Electrostatic potential analysis in Fig. 9 confirms this expectation in the drift region, buffer, and the initial micrometers of the substrate. However, the presence of a highly doped poly-SiC substrate compensates for the increased voltage drop in these regions. Consequently, the overall voltage drop VSD is reduced from 3.55 V to 3.3 V at given conditions. Electrostatic Potential [V] -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 p-region drift region buffer substrate Reference SiC engineered substrate −1.3 −1.4 −1.5 −1.6 −1.7 −1.8 Electrostatic Potential [V] Chip thickness [a.u.] Reference SiC engineered substrate substrate drift region buffer Fig. 9. Comparison of electrostatic potential at three times the nominal current, with Tj= 200°C, VGS =−10 V, and tdead = 1 µs. IV. CONCLUSION The reverse recovery behavior and plasma formation of SiC MOSFETs fabricated on engineered substrates were investigated through measurements and electro-thermal TCAD simulations. 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