Interleaved Quadratic Boost DC-DC Converter with Extended Voltage Gain and Reduced Switch Voltage Stress for Photovoltaic Applications

RESEARCH ARTICLE  Interleaved Quadratic Boost DC-DC Converter with Extended Voltage Gain and Reduced Switch Voltage Stress for Photovoltaic Applications [version 2; peer review: 2 approved] Daniel Ferreira 1,2, Armando Cordeiro 1,3, Paulo Gambôa1,3, Luis Rocha1,3, Filipe Barata1, José Fernando Silva 3,4, João F. Martins5, Vitor Fernão Pires 2,3 1PolyTechnic University of Lisbon, Department of Electrical Engineering Energy and Automation, Instituto Superior de Engenharia de Lisboa (ISEL), Rua Conselheiro Emídio Navarro, Lisboa, 1, 1959-007, Portugal 2Department of Electrical and Computer Engineering (DEEC), Nova University of Lisbon, Faculdade de Ciência e Tecnologia (FCT), 2829-516 Caparica, Portugal, CTS-UNINOVA and LASI, Portugal, LASI, Portugal 3Polytechnic Institute of Setubal, Department of Electrical Engineering (DEE), Escola Superior de Tenologia de Setúbal, Campus do IPS, Estefanilha, Setúbal, 2914-508, Portugal 4INESC-ID Lisboa, Rua Alves Redol, Lisboa, 9, 1000-029, Portugal 5Department of Electrical and Computer Engineering (DEEC), University of Lisbon, Instituto Superior Técnico, Av. Rovisco Pais, Lisboa, 1, 1049-001, Portugal First published: 24 Feb 2025, 5:55 https://doi.org/10.12688/openreseurope.19625.1 Latest published: 28 Oct 2025, 5:55 https://doi.org/10.12688/openreseurope.19625.2 v2 Abstract Background DC-DC power converters are essential devices in the modern world, playing a crucial role in managing the power supply from different power sources converting and adapting voltage levels. These power converters are fundamental to numerous applications, from charging your mobile phone to powering different types of machinery. Lately, due to climate change problems and the floating nature of most renewable power sources, they are essential to a carbon-free world and zero emissions target. Methods Our investigation method was based on an initial theoretical approach using mathematical equations to describe the operation of the electrical circuit and evaluate the performance compared to other topologies, followed by the validation through some computational simulations using MATLAB/SIMULINK software. Next, the operation of the proposed converter was also confirmed by several experimental Open Peer Review Approval Status 1 2 version 2 (revision) 28 Oct 2025 view version 1 24 Feb 2025 view view Siva Asapu , Shri Vishnu Engineering College for Women, Bhimavaram, India 1. Rachananjali K, Vignan Foundation for Science Technology & Research, Guntur, India 2. Any reports and responses or comments on the article can be found at the end of the article. Open Research Europe  Page 1 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 tests using a laboratory prototype developed exclusively for these tests. Results Based on the achieved results, an efficiency analysis was performed showing that in addition to high-voltage gain, from the range of six to eight times the input voltage, the converter maintains a very high efficiency, around 95% to 96% up to a duty cycle of 0.50, where a voltage gain of 5.82 is achieved in a real setup Also, the optimal operating point was identified, based on the duty cycle, where the converter operates at maximum efficiency. In PLECS® simulation environment, dynamic tests under PI output voltage control revealed fast transient response and good voltage regulation, while MPPT PV simulations demonstrated effective maximum power extraction and tracking under variable irradiance and temperature conditions. Conclusions In conclusion, it is possible to claim that the proposed converter presents a stable and efficient operation and has a very high potential for applications that require high-voltage gain, such as photovoltaic solar systems or even electrical vehicles or energy storage systems. Other relevant aspect is the reduced value of capacitors, due to the interleaved operation, leading to reduced stress over capacitors and distributed voltage over them. Plain language summary This paper shows the study, development, and results of a new DirectCurrent to Direct-Current (DC-DC) electric power converter topology, designated as interleaved quadratic Boost DC-DC converter topology. The converter topology is capable of achieving significantly higher voltage gains (higher voltage in the output when compared with the input voltage) than most conventional existing topologies. A theoretical approach was introduced in this paper and then validated through some computer simulations (using MATLAB/SIMULINK software). Finally, the performance of the topology was also confirmed in an experimental setup using a practical prototype of the proposed converter. From the experimental results, it was possible to achieve a maximum output voltage gain of over eight times the input voltage. An efficiency analysis (allowing us to identify the energy losses during the operation of the converter) was also performed, showing that the proposed topology converter maintains a very high efficiency, around 95% to 96%. The optimal operating point was also identified, based on the duty cycle (turn-on and turn-off of the power devices at a certain frequency), where the converter operates at maximum efficiency. The results show that the proposed converter has a very high potential for applications that require high-voltage gain, such as photovoltaic solar systems or even electrical vehicles or energy storage systems. Open Research Europe  Page 2 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Corresponding author: Armando Cordeiro ([email protected]) Author roles: Ferreira D: Investigation, Methodology, Project Administration, Supervision, Validation, Writing – Original Draft Preparation; Cordeiro A: Conceptualization, Formal Analysis, Investigation, Methodology, Project Administration, Supervision, Validation, Writing – Original Draft Preparation, Writing – Review & Editing; Gambôa P: Supervision, Validation, Visualization, Writing – Original Draft Preparation, Writing – Review & Editing; Rocha L: Resources, Supervision, Validation, Visualization, Writing – Original Draft Preparation, Writing – Review & Editing; Barata F: Resources, Supervision, Validation, Visualization, Writing – Original Draft Preparation, Writing – Review & Editing; Fernando Silva J: Conceptualization, Investigation, Methodology, Project Administration, Validation, Visualization, Writing – Original Draft Preparation, Writing – Review & Editing; F. Martins J: Funding Acquisition, Investigation, Methodology, Project Administration, Validation, Visualization, Writing – Original Draft Preparation, Writing – Review & Editing; Fernão Pires V: Conceptualization, Funding Acquisition, Investigation, Methodology, Project Administration, Resources, Supervision, Validation, Visualization, Writing – Original Draft Preparation, Writing – Review & Editing Competing interests: No competing interests were disclosed. Grant information: This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 101123175. (Herit4Ages project). The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. Copyright: © 2025 Ferreira D et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. How to cite this article: Ferreira D, Cordeiro A, Gambôa P et al. Interleaved Quadratic Boost DC-DC Converter with Extended Voltage Gain and Reduced Switch Voltage Stress for Photovoltaic Applications [version 2; peer review: 2 approved] Open Research Europe 2025, 5:55 https://doi.org/10.12688/openreseurope.19625.2 First published: 24 Feb 2025, 5:55 https://doi.org/10.12688/openreseurope.19625.1 Keywords DC-DC Converters; Interleaved Quadratic Boost; High-Voltage Gain; High Efficiency; Photovoltaic systems This article is included in the Horizon Europe gateway. This article is included in the Energy Systems Modelling collection. Open Research Europe  Page 3 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Introduction The increasing global demand for energy-efficient and sustainable systems has driven significant advancements in power electronics, particularly in DC-DC conversion technologies1. Traditional Boost converters, while effective in many applications, often have difficulty to achieve the high-voltage gains required in modern power systems, such as photovoltaic solar systems2, electrical vehicles (EV)3, High-Voltage Direct Current (HVDC) power transmission systems4, water pumping systems5, or others. Addressing the limitations of conventional topologies, this work introduces a novel interleaved quadratic DC-DC Boost converter designed to provide significantly higher voltage gain without sacrificing efficiency. Over the years, numerous DC-DC Boost converter topologies have been developed for different applications in a wide range of emergent multidisciplinary engineering fields, such as renewable energy sources (RES), photovoltaic solar energy conversion, EV, energy storage systems (ESS), fuel cells, among others. Typically, DC-DC converters can be classified according to different features, such as isolated6,7 or non-isolated8,9, unidirectional10,11 or bidirectional12,13, voltage-fed14,15 or current-fed16,17, hard-switch18,19 or soft-switch20,21, minimum-phase22 or non-minimum-phase23. Most of these DC-DC converters are well represented in 24–27. Another way to classify the DC-DC converters is specifying their voltage Boost technique. Some of the most well-known techniques are the switched capacitors28,29, voltage multiplier cells30,31, switched inductors32,33, voltage lift34,35 and multi-stage/-level36,37 topologies. A review of some of these step-up voltage techniques can be found in 38–40. Nowadays, engineering research is also focused on the development of converters with higher reliability, higher efficiency, combined with less volume, weight and cost41. Among the DC-DC converter topologies developed recently that have stood out for the high-voltage gains obtained are those that present quadratic gains. In this way, is possible to highlight some significantly important topologies developed with such features. The solution proposed in 42 is a transformerless high step-up DC-DC converter with a quadratic voltage gain. In this converter, using a duty cycle greater than 0.309 is possible to achieve a higher voltage gain than the classic Boost converter. This solution includes three switches, five diodes, two inductors and three output capacitors. Despite its interest, this solution requires too many components when compared with other solutions. Other quadratic gain topology can be found in 43, where the authors propose a modified classic DC-DC buck-boost converter. Since this topology allows a buck-boost operation, it is only necessary to control one power switch for each operation mode and the additional power switches remain always ON or always OFF. By controlling only one power switch, they developed a setup capable of achieving a quadruple voltage gain for a duty cycle of 0.5. Another similar topology can be found in 44, which created a quadratic high-gain Boost converter, where it was possible to obtain a gain of two times the input voltage at the output with a duty cycle of 0.50. More recently a new DC-DC Boost converter setup with quadratic gain was proposed45. In this solution using a duty cycle of 0.50 is also possible to achieve a triple output voltage. This solution includes one switch, three diodes, two inductors and two output capacitors. Recently, a new quadratic DC-DC Boost converter topology was proposed in 46, which can achieve a quintuple output voltage with a duty cycle of 0.50. This solution requires only one switch, four diodes, two inductors and three capacitors. The main disadvantage of this solution is that the switch must withstand the maximum output voltage. It is well-known that high-voltage gain is critical in applications with low input voltages, such as those using a reduced number of solar panel strings or where, due to weather variability sometimes produce reduced voltages, and it required to efficiently convert them into much higher output voltages47. Most quadratic DC-DC Boost converters typically offer voltage gains of three to four times the input voltage, which may not be sufficient for advanced applications. The interleaved quadratic Boost topology proposed in this study aims to overcome these limitations by achieving an extended voltage gains over eight times the input voltage, or six times considering a duty cycle of 0.50, providing a more effective solution to integrate additional RES systems. This converter is also characterized by a simple control technique, continuous input and output current, reduced switching voltage stress over the power devices. The proposed solution takes advantage of the interleaved operation, which allows to use multiple circuits (or phases) to process power in parallel. These circuits are operated with time-shifted (interleaved) switching signals to achieve improved performance compared to a single-phase or single-circuit converter. Also, the interleaved operation avoids the need of large output capacitors. The solution is also able to achieve good efficiency according to some preliminary experimental results. This paper presents the theoretical framework behind the proposed interleaved quadratic DC-DC Boost topology, complemented by some experimental results to confirm the theoretical results and efficiency. This paper is organized into five main sections. Section I is dedicated to the introduction of this subject and importance of DC-DC converters in most modern applications, followed by a brief state-of-the-art over DC-DC Amendments from Version 1 This new version include an extensive analisys of efficiency in different operation modes. Also includes additional comparisons with other similar DC-DC topologies considering additional aspects. Several sections were added to include aditional information and explain the design process of the proposed converter. Also the images were enhanced to increase quality. Finally, some text was introduced to explain how to perform closed-loop control. Any further responses from the reviewers can be found at the end of the article REVISED Page 4 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 converters with quadratic gain. Section II provides a detailed explanation of all the design procedures and considerations on the prototype of the proposed converter. Section III presents a comparison between the proposed converter and other interleaved quadratic Boost DC-DC converters already proposed and implemented in the literature. Section IV is dedicated to presenting and demonstrating the laboratory setup and validation of the results regarding the operation principle, voltage gain obtained and efficiency. Finally, section V presents some conclusions. Methods and theoretical analysis Our investigation methodology was based on an initial theoretical approach using mathematical equations to describe the operation of the electrical circuit and evaluate the performance compared to other topologies, followed by the validation through some computational simulations using MATLAB/ SIMULINK software. Next, the operation of the proposed converter was also confirmed by several experimental tests using a laboratory prototype developed exclusively for these tests. The next subsections are dedicated to show these procedures. Power circuit layout of the proposed quadratic Boost DC-DC converter Figure 1 shows the diagram of the interleaved quadratic Boost DC-DC converter proposed in this paper. It is a new topology that has never been published before, according to extensive research conducted in the main bibliographic reference resources in the field. The power circuit consists of an input inductor, Lin, along with two input diodes, Din1 and Din2, and a capacitor, Cin. Connected to these components are two additional circuits, one at the top and another at the bottom, each consisting of and inductor, L1 and L2, a capacitor, C1 and C2, and a diode, D1 and D2, respectively. Finally, to ensure the capability of voltage regulation and Boost operation, two power MOSFET, S1 and S2, are included, controlled by a command circuit through their gates, represented in the figure as G1 and G2, respectively. Operation mode analysis in steady-state The converter under study has four different operation modes, all in continuous conduction mode (CCM), depending on the operation of the two switches, S1 and S2. Although both power semiconductors can operate simultaneously (overlapping the conduction mode) for duty cycles above 0.50, this mode of operation is not advantageous for lower duty cycles, as it generates higher current peaks without resulting in improved voltage gain. Therefore, in the following analysis, it will be considered whether the converter operates with S1 turned ON and S2 turned OFF or S1 turned OFF and S2 turned ON or both switches turned OFF, providing four different operating intervals as explained next. Figure 2 shows a simplified representation of a classic PWM (Pulse-WidthModulation) control strategy in order to achieve the described operation mode. This is considered an interleaved operation. In the following figures, the four stationary operation modes are illustrated in detail, where the current flow directions in the different paths are represented with different colours to help understanding the operation principle of the converter. S1 turned ON and S2 turned OFF (δ1Ts). During this operating mode, the input diode Din2 is turned OFF, while the input diode Din1 is turned on. Also, during this mode, the input inductor Lin, discharges the energy accumulated in the previous operating mode over the input capacitor Cin which is in charging mode. Meanwhile, the diode D1 is also turned OFF because the inductor L1 is charging and the capacitor C1 is discharging, creating a reverse voltage over D1. On the other hand, D2 is turned ON, meaning that L2 is discharging the energy previously accumulated, and as a result, C2 is in charging mode. The current flow described is illustrated in Figure 3. Figure 1. Circuit topology of the proposed interleaved quadratic DC-DC Boost Converter. Page 5 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 2. PWM switching strategy of S1 and S2. Figure 3. Current flow analysis when S1 turned ON and S2 turned OFF (δ1Ts). S1 OFF and S2 OFF (δ2Ts). In this operating mode, Din2 remains turned off while Din1 remains turned ON. Similar to the previous operating mode, Lin is still discharging and Cin in charging mode. Both D1 and D2 are now turned ON since both inductors, L1 and L2, are discharging the accumulated energy over C1 and C2, respectively. The current paths described can be found in Figure 4. S1 OFF and S2 ON (δ3Ts). In this operating mode, after turning ON the switch S2, Din2 turns ON to flow the current over the input inductor Lin, while Din1 turns OFF due to reverse voltage. Thus, Lin is charging, and Cin is discharging the accumulated energy in the previous operating mode over the inductor L2, which is storing energy. As a consequence of passive components polarity, D2 becomes reverse-biased and Page 6 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 turned off, while C2 starts to discharge over the load. In the opposite direction, D1 is forced to turn ON to discharging the energy accumulated over the inductor L1 into C1, which is in charging mode. Figure 5 shows the representation of the current path flow described now. S1 OFF and S2 OFF (δ4Ts). In this operating mode, both switches are turned off and the current’s path flow is the same as the ones presented in the interval δ2Ts. Component stress analysis Following the operation modes described previously, it can be observed and concluded that the current in inductor L1 increases when the switch S1 is turned ON and decreases when S1 is turned OFF. This means that the switching state of S1 does not affect the current in Lin and L2. On the contrary, the current in inductors Lin and L2 increase when switch S2 is turned ON and decreases when S2 is turned OFF. This means that the switching state of S2 does not affect the current in L1. This indicates a partially independent operation of the two power switches, when the switching states of S1 and S2 do not overlap. According to the principle of operation detailed in the previous subsection, it is possible to obtain the theoretical waveforms of the four-operating mode of the proposed converter (see Figure 6). When analyzing the evolution of the voltage across each inductor and semiconductor presented in this figure is possible to establish the voltage relationships shown in Table 1. According to Table 1, as result of the analysis of the voltage relationships between components it is possible to see that the maximum voltage stress over power devices S1 and S2 are vCin + vC1 and vCin + vC2, respectively, which is far reduced when compared to most DC-DC converters whose power devices must support the maximum output voltage. Theoretical voltage gain analysis In this way, it is possible to establish the following voltage relationships for each inductor. Assuming ideal components and considering one switching cycle, the relationship between the output and input current, function of the duty cycle, can be obtained through the volt-second relationship of the inductors L1, L2 and Lin, as presented from (1) to (3), respectively: 1 2 3 4 1 ( ) ( )( ) CC in v vδ δ δ δ− = + + (1) 3 1 2 4 2 ( ) ( )( ) CC in v vδ δ δ δ− = + + (2) 3 1 2 4 ( ) ( )( ) Cin in in v v vδ δ δ δ= + + − (3) Knowing that (δ2 + δ3 + δ4) = (1 – δ1) and (δ1 + δ3 + δ4) = (1 – δ3), as well as δ1 = δ3 = δ; equalizing and solving the Equation (1) to Equation (3) to each capacitor voltage, it is possible to establish the voltage equations listed below from (4) to (6): 11C Cin v v δ δ = − (4) Figure 4. Current flow analysis when S1 and S2 are turned OFF (δ2Ts). Page 7 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 5. Current flow analysis when S1 is turned OFF and S2 is turned ON (δ3Ts). 21 C C in v v δ δ = − (5) 1 Cin in v v δ δ = − (6) Equalizing and solving Equation (4) to Equation (6) in order to vin, and knowing that vout = vCin + vC1 + vC2, it is possible to establish the expression that characterizes the voltage gain of the proposed interleaved quadratic DC-DC converter (7): 2 1 (1 ) out in v v δ δ + = − (7) Design considerations In this section, the entire design process of the passive components used in the proposed experimental prototype will be presented and discussed. The following characteristics were considered in the design of the prototype: vin = 50 V, δmax = 0.5, RLoad = 450 Ω, Pout(max) = 200 W, vout (δmax) = 300 V, iout (δmax) = 300/450 = 0.67 A, ΔiLmax = 0.5 A, ΔvCmax = 1 V to 3 V, fPWM = 50 kHz, efficiency of 95%. Inductors design For the inductors design, the generic adopted expression to define the minimum inductance value is presented in (8). This expression is based on the linear variation of the current in the inductor and is well explained in most design chapters about DC-DC converters, such as 48–50. L PWM L max v Lf i δ ∆ ⋅ > ⋅ (8) Where vLmax is the maximum voltage applied to the inductor, δ is the maximum duty cycle intended for the converter, fPWM is the switching frequency of the converter, and ΔiL is the maximum current variation (ripple) desired in the inductor. For the input inductor, Lin, the following equation can be used: 1 PWM L in in in v L L mH f i δ ∆ ⋅ > ⇒ > ⋅ (9) For the remaining inductors, L1 and L2, the following equation can be used: 1 2 (1 ) 2 PWM L PWM L in Cin v v L L mH f i f i δ δδ ∆ ∆ ⋅ ⋅− = > ⇒ > ⋅ ⋅ (10) Ferromagnetic material saturation analysis The material of the inductors, applied in this prototype, uses a Litz 420x0.08 SE F155 G1 wire type (widely used in high frequency applications, as it reduces losses and the skin effect), a plastic inductor winding support from the CF model -E70-1S and a set of ferrite cores from model E70/33/32DG in “U” shape, from the manufacturer TDK, with type N87 ferrite. Using the manufacturer datasheet, it is possible to obtain some essential parameters (see Table 2) for analyzing the electromagnetic saturation of the ferrite core. Page 8 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 6. Theoretical wave forms of the proposed DC-DC Converter. Page 9 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Inductors and power devices waveforms Figure 13 shows the experimental result of the three inductor currents obtained from the power circuit of the proposed converter for δ = 0.4 and relation with the switching of the power devices. The results presented in Figure 13 confirm the dependence between each inductor and one of the power switches, specifically, the state of charge of Lin and L2 depends on the conduction state of S2, and the same situation occurs between L1 and S1. The mean current values are: iLin = 1.169 A, iL1 = 810.2 mA and iL2 = 758.2 mA. Diodes and power devices waveforms Figure 14 illustrates the experimental results of the relationship between the diodes and the power switches voltage for δ = 0.4. According to the results shown above (Figure 13a) and Figure 13b), the conduction states of D1 and D2 are symmetric to the conduction state of S1 and S2, respectively. On the other hand, the conduction states of both input diodes Din1 and Din2 are dependent on the S2 (see Figure 14c) state, just like iLin, as concluded before in Figure 13a). Notice that the power devices voltage waveforms are different depending on the experimental result for the same duty cycle, which is probably due to coupling of common mode noise, which is more intensive as the switching frequency increases. Capacitors and power devices waveforms Figure 15 shows the experimental results of each capacitor and the power switches voltages for δ = 0.4. Interpretating the results shown in Figure 15 and remembering the symmetric relation between D1 and S1, along with D2 and S2, it is clear the correspondence between the state of charge of both Cin and C2 and S2, as well as, between C1 and S1. Making a parallel analysis between the results of Figure 13 and Figure 15, it is also possible to observe when an inductor is discharging the corresponding capacitor is charging and vice-versa. The mean voltage values are: vCin = 80.26 V, vC1 = 52.20 V and vC2 = 50.20 V. Notice that in the following figure, the Ch2 voltage gain is only 2V/div, and the reference is virtually several divisions bellow the minimum visible at the screen (this Peaktech oscilloscope allows this configuration). Thus, the noise is not so high as it seems at first sight. Concerning the comparison between the simulation and experimental results, it is shown in all the figures presented from Figure 13 to Figure 15 that the simulation behavior is correctly confirmed by the experimental results. Output voltage and voltage gain In this subsection several experimental results are presented of the output voltage, output current and a voltage gain comparison for different duty cycles. Figure 16 features the experimental voltage and current output result obtained with δ = 0.4. Observing Figure 16 it is possible to see that for δ = 0.4 the proposed prototype is able to produce an output voltage vout = 189.8 V, which translates to a voltage gain (vout/vin) of 3.66. The mean value of the output current is equal to 453.4 mA. Figure 17 shows the experimental result of the output voltage and output current obtained in the prototype for δ = 0.5. Observing Figure 17 with this duty-cycle is possible to observe an output voltage vout = 291.00 V, which translates to a voltage gain (vout/vin) of 5.82. The mean value of the output current is equal to 690.6 mA, which translates into a Pout ≈ 200 W. As a final experimental result, the prototype was tested with a duty-cycle value δ = 0.6. Figure 18 shows the output voltage in this condition. According to Figure 18, the experimental result obtained of the output voltage obtained with a duty-cycle δ = 0.6 is 436.7 V. Which means it is possible to get a voltage gain (vout/vin) of 8.62. Above this duty-cycle is difficult to increase the voltage gain due to increased losses. Figure 19 compares the theoretical voltage gain of the proposed converter, the computational simulation results (simulated in PLECS®) and also the experimental voltage gain obtained. Analyzing Figure 19 is possible to observe in the duty-cycle range from 0.05 to 0.60, the output voltage and voltage gain of the experimental prototype shows a high degree of similarity when compared with the simulation and theoretical calculations. Additionally, it is confirmed that with a duty-cycle of 0.20, a gain voltage greater than 1.7 is achieved, with a duty-cycle of 0.30, a voltage gains greater than 2.5, with a duty-cycle of 0.40, a voltage gains greater than 3.6 and with a duty-cycle of 0.50, a gain greater than 5.8 is achieved. A maximum gain of 8.62 was achieved with a duty-cycle of 0.60. Behind this duty-cycle is difficult to improve the voltage gain since the losses become extremely high. Efficiency analysis This section discusses the results obtained based on experimental test observations, oscilloscope waveforms, and measured voltages and currents. The analysis aims to evaluate the converter’s overall efficiency and to identify the optimal operational point. Both simulated and experimental results are compared to assess the validity of the proposed design. In experimental prototypes of DC-DC converters, the total efficiency depends not only on ideal power transfer but also on several non-ideal factors such as conduction, switching, and magnetic losses. Since the current and voltage waveforms vary with the duty-cycle (δ), the efficiency and total losses are inherently functions of δ. The converter’s efficiency can be expressed as: ( ) ( ) ( ) ( ) ( ) ( ) ( ) Out Output Out in in Input PV i P V i δδ δ η δ δ δ δ ⋅ = = ⋅ (22) During the experimental measurements, the efficiency of the DC-DC converter prototype was evaluated using (22), based on the measured input and output voltages and currents. However, in PLECS® environment, to better understand the internal loss mechanisms, an equivalent non-ideal circuit model was developed, including parasitic elements such as the MOSFET on-resistance (RDS(on)), diode forward voltage (VF), inductor series resistance (RL), and capacitor equivalent series resistance (RC). The total power loss can then be expressed as: Page 16 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 13. Inductor currents and power devices voltages for δ = 0.4: a) iLin and vS2; b) iL1 and vS1; c) iL2 and vS2. Page 17 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 14. Diodes and power switches voltages for δ = 0.4: a) vD1 and vS1; b) vD2 and vS2; c) iLin , vDin1 and vDin2. Page 18 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 15. Capacitor and power switches voltages for δ = 0.4: a) vCin and vS2; b) vC1 and vD1; c) vC2 and vD2. Page 19 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 16. Output voltage and current for a duty cycle, δ = 0.4. Figure 17. Output voltage and current for a duty cycle, δ = 0.5. Page 20 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 19. Comparison between theoretical, simulation and experimental voltage gain. Figure 18. Output voltage for a duty cycle, δ = 0.6. Page 21 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 , , , , ( ) ( ) ( ) ( ) ( ) ( ) CL S CL D CL L CL C SL Losses P P P P P Pδ δ δ δ δ δ= + + + + (23) Where: • , 2 , ( ) ( ) ( ) CL S DSSwitch rms on P i Rδ δ= ⋅ : Conduction losses in MOSFETs • PCL,D (δ) = VF ∙ iD,avg(δ): Conduction losses in diodes • , 2 , ( ) ( ) L CL L L rms P i Rδ δ= ⋅ : Conduction losses in inductors • , 2 , ( ) ( ) CL C C C rms P i Rδ δ= ⋅ : Conduction losses in capacitors • PSL (δ) = 0.5 ∙ Vsw (δ) ∙ isw (δ) ∙ (ton + toff) ∙ fsw: Switching losses The current and voltage stress of the power devices are proportional to the duty cycle, which means that at higher δ values, both conduction and switching losses increase. Conversely, at lower δ values, current ripple and average currents dominate, leading to higher conduction losses in inductors and MOSFETs. The analytical efficiency model was implemented in PLECS®, using parasitic parameters obtained from datasheets. The simulated efficiency curve exhibits the same trend observed experimentally, where efficiency increases with δ up to an optimal operating point, then gradually decreases as both switching and conduction losses become more significant. In the PLECS® simulation environment, two dedicated functional blocks were used, one for switching loss calculation and another for conduction loss calculation. The resulting losses were then summed up and applied in (24) to obtain overall converter efficiency. ( ) ( ) ( ) ( ) Output Losses Output P P P δ η δ δ δ = + (24) Figure 19 shows the graphical result of the efficiency obtained in both simulation and experimental tests, as function of the converter duty cycle. After analysing the results presented in Figure 20, a close correlation is observed between the efficiency variation and the duty-cycle applied to the converter. For a duty-cycle variation from 0.05 to 0.60, an efficiency range around 97% to 90% was obtained in the simulation tests and an efficiency range around 96% to 90% was obtained in the experimental tests. It is also observed that a maximum efficiency of 96.79% was achieved for a duty-cycle δ = 0.25. Figure 21 illustrates the evolution of experimental efficiency and voltage gain over the duty cycle. The purpose of this relationship is to evaluate at which output voltage gain value it is possible to achieve the best efficiency, helping us to identify an optimal operating point for the proposed DC-DC converter prototype. Examining Figure 21 is possible to observe that the optimal operating point of the converter happens with a duty-cycle of δ =0.25 which results in a voltage gain of 2.09 (marked in red in the figure). However, it is clear that, up to a duty-cycle of 0.60, the converter maintains an efficiency between 90% and 96%, which can be considered quite satisfactory. At the maximum value for which it was designed, with a duty-cycle Figure 20. Comparison between the simulation and the experimental results concerning the converter efficiency. Page 22 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 of 0.50, the converter presents a voltage gain of 5.82 and an efficiency of 94.76%. Additionally, there is very little variation in efficiency, as it remains between 96% and 95% until reaching a duty-cycle of 0.50. Finally, Figure 22 shows the relation between the output power and the output voltage gain of the proposed topology considering a fixed duty-cycle of 0.50, showing certain limitations over the output gain due to several losses. For duty cycles (δ) above 0.5, an additional operating condition appears in which both S1 and S2 conduct simultaneously. This fourth state, shown in Figure 23, creates an overlap between the interleaved channels. The current-loop analysis corresponding to this additional operating mode is illustrated in Figure 23. As observed, D1, D2, and Din1 are turned off, whereas Din2 conducts. During this interval, all three inductors store energy (charging mode), while the three capacitors release energy (discharging mode). Although this regime increases the converter’s voltage gain, it also raises the instantaneous current stress on the power devices and amplifies switching losses, as both switches share conduction intervals. Consequently, this overlapping mode is critical for understanding the efficiency degradation observed experimentally for δ > 0.5. To quantify these effects, Figure 24 and Figure 25 present the simulated loss distribution obtained from PLECS® for δ = 0.4, 0.5, and 0.6. Figure 24 shows the total losses per component (S1, S2, D1, D2, Din1, Din2), where it details the switching and conduction losses of both MOSFETs. Two dedicated PLECS® functional blocks, one for switching losses estimation and another for conduction losses estimation were employed. As confirmed before in Figure 20, simulated efficiency curve follows the same pattern as the experimental curve, with slightly higher values due to idealized parasitic parameters and datasheet values used in the modeling. Although, the similarity between simulated and experimental efficiency results confirms the high accuracy of the simulation model and provides confidence in the reliability of the simulated data. The results clearly indicate that losses increase with the dutycycle and that their distribution becomes progressively unbalanced. At δ = 0.4, total power losses are relatively balanced between switches and diodes. At δ = 0.5, S2 already exhibits higher conduction and switching losses, and at δ = 0.6 this imbalance becomes dominant, with S2 accounting for nearly half (48%) of the total dissipation. This asymmetry between S1 and S2 arises from differences in their respective current paths. As shown in Figure 3 (S1 ON) and Figure 5 (S2 ON), as well as in Figure 23 (both switches ON), the conduction path associated with S2 consistently carries higher current levels, resulting in greater conduction losses. Regarding switching losses, S2 also experiences higher voltage stress during turnon and turn-off transitions due to capacitor interactions and interleaving effects. The overlapping conduction mode depicted in Figure 23 reinforces these findings: simultaneous operation of S1 and S2 produces higher current peaks through both inductors and diodes, leading to increased switching and power losses. Although this mode extends the voltage gain, it compromises efficiency and thermal balance. Therefore, in practical implementations, operation beyond δ = 0.5 should be avoided. Figure 21. Comparison between experimental voltage gain result and experimental efficiency result. A maximum efficiency of 96.79% was achieved for a duty-cycle around δ = 0.25. Page 23 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 In a nutshell, the converter achieves a maximum efficiency of approximately 96.8% at δ ≈ 0.25, where both conduction and switching losses are minimized. For δ > 0.5, the increased switching transitions and diode recovery effects contribute to a measurable reduction in efficiency. The results confirm that the proposed interleaved quadratic boost converter maintains high efficiency and stable performance across a wide duty-cycle range, validating both the analytical and experimental findings. This reinforces its suitability for applications such as PV microgrids and other RES systems, Figure 22. Output voltage gain versus Output Power, considering a fixed duty-cycle of 0.50. Figure 23. Current flow analysis when both S1 and S2 are turned ON. Page 24 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 24. Simulated diodes and MOSFETs power losses (PLECS®) for δ = 0.4–0.6. Page 25 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 32. PLECS® result for MPPT PV control between 0.0 s and 0.4 s. presented in the datasheet (17.6 V × 3). The PV current varies between 3.43 A and 3.95 A, translating in an average current of 3.69 A (±7%), matching the MPP voltage presented in the datasheet. The PV power waveform is between 182 V and 208 V, which means an average power of 195 W (±7%), exactly same as the datasheet. The next simulation interval is between 0.4 s and 0.8 s, where the irradiance decreases from 1000 W/m2 to 700 W/m2, as depicted in Figure 33. According to the results in Figure 33, following the irradiance step-down, the PV power decreases from 195 W to approximately 134.5 W and stabilizes in less than 0.05 s. The PV voltage remains nearly constant at 52.2 V, while the current decreases to an average of 2.58 A, consistent with the expected irradiance reduction. Figure 34 presents the waveform results from 0.8 s to 1.2 s, when the irradiance returns from 700 W/m2 back to the initial 1000 W/m2. As before, the converter successfully tracks the maximum power point after the irradiance increase, recovering the PV generation to its nominal level. The PV voltage stabilizes at an average of 52.8 V, and the current returns to 3.69 A, both within 0.05 s, demonstrating the fast and stable response of the MPPT controller. Finally, Figure 35 shows the results obtained between 1.2 s and 1.6 s, where the irradiance remains constant in the 1000 W/m2 while the temperature is increased to 40 ºC. As shown in Figure 34, the increase in temperature causes the PV voltage to decrease to an average of 48.7 V (approximately –8% compared to STC), while the current slightly increases to 3.72 A (+1% compared to STC). These variations are consistent with the well-known temperature dependence of PV cells, where higher temperatures reduce the open-circuit voltage and slightly increase the short-circuit current. Across all simulated intervals, the converter consistently achieved efficiencies ranging from 95.6% to 96.1%, demonstrating the MPPT PV control’s capability to maintain dynamic stability and high efficiency under fluctuating irradiance and temperature conditions. Discussion The proposed interleaved quadratic boost DC-DC converter demonstrated robust performance and consistent behavior across simulation and experimental stages. The component stress analysis confirmed that the voltage stress over each power switch was reduced compared to other similar proposed topologies in the literature, with the maximum voltage stress over power devices S1 and S2 as vCin + vC1 and vCin + vC2, respectively. There is still constant research regarding the design of new DC-DC converter topologies with high-voltage gain ratio and boost ability to extend the operation of RES, and other sources, all over the available voltage ranges, extracting efficiently as much energy as possible. In this article, it was made a brief research about other types of DC-DC converters and it was Page 32 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 33. PLECS® result for MPPT PV control between 0.4 s and 0.8 s. Figure 34. PLECS® result for MPPT PV control between 0.8 s and 1.2 s. decided to create a new interleaved quadratic DC-DC converter topology. Quadratic DC-DC converters are some of the topologies that can achieve high voltage gains and are the most suitable for several RES applications due to the variability of most of them, which are dependent on weather conditions, location, distribution system and other aspects. When compared with other topologies in the literature, especially other quadratic DC-DC converters, the proposed topology is the one with higher Page 33 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Figure 35. PLECS® result for MPPT PV control between 1.2 s and 1.6 s. voltage gain but presents a reduced number of components and the interleaved solution allows to reduce the voltage and current stress over power devices which allows to increase the reliability of the solution. The laboratory prototype was tested in several conditions during several days to evaluate the overall performance, namely the voltage and current stress, robustness, overheating issues, hot spots, electromagnetic noise, efficiency, sensitivity to parameters variation and other aspects. Regarding the electromagnetic noise, some adjustments need to be made to future work on the printed circuit board and components, but the overall performance is quite acceptable. This will allow us to improve some waveform and interference due to electromagnetic noise. Efficiency was measured in several conditions and real values between 90% (worst conditions) and 96% (best condition) were achieved. Its analysis revealed that conduction and switching losses increase with duty-cycle, especially when both switches overlap in conduction for δ > 0.5. Loss modeling in PLECS® confirmed that S2 experiences higher conduction and switching stress due to its current path characteristics. Nevertheless, the correlation between simulated and experimental data was high, confirming the precision of the analytical model. Another relevant aspect is the reduced capacitance of capacitors, due to the interleaved operation. This leads to reduced stress over capacitors and distributed voltage. Notice that the output voltage is the sum of the voltage over the three capacitors. A low power laboratory prototype was developed but it is possible to develop a similar converter with higher power density. Dynamic performance tests under closed-loop PI control demonstrated good voltage regulation and transient response. For output reference steps from 150 V to 300 V, the converter exhibited fast settling (around 0.1 s), minimal overshoot (<5%), and maintained efficiency above 95%. Under load variations, voltage deviations remained within ±5%, ensuring operational stability and adaptability. Furthermore, the MPPT PV control simulations confirmed the converter’s ability to effectively extract maximum power from photovoltaic arrays under varying irradiance and temperature. The Perturb and Observe (P&O) algorithm maintained the PV voltage within 1% of its MPP reference and achieved full recovery to MPPT stage within 0.05 s after irradiance changes, confirming the converter’s capability to operate in PV systems. Conclusions This article proposed a new interleaved quadratic DC-DC boost converter topology with high-voltage gain, including the first theoretical operation analysis, design and further experimental validation, using a 200 W laboratory prototype operating at 50 kHz. The experimental results demonstrate that the proposed topology allows higher voltage gains than most Page 34 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 well-known quadratic topologies, reaching a voltage gain from six to more than eight in a real prototype without compromising the efficiency significantly. The proposed converter provides continuous input and output current and a simple PWM control strategy. It was possible to optimize the converter’s efficiency by adjusting the duty cycle, which is important when we want to minimize conduction and switching losses. The results obtained indicate that there is an optimal operating point where efficiency is maximized, achieving an efficient balance between voltage gain and associated losses. Additionally, there is no significant variation in efficiency, which remains between 95% and 96% up to a duty-cycle of 0.50, where a voltage gain of 5.82 is achieved in a real setup. However, when the voltage gains increase behind this point, efficiency began to decrease, resulting in an evident tradeoff between maximizing voltage gain and energy efficiency. This trade-off is particularly relevant in solar photovoltaic applications, where it is necessary to find an appropriate compromise between voltage gain and efficiency based on the specific requirements of the system. Furthermore, the converter can effectively combine a high stepup ratio with simple control and robust dynamic response, as confirmed by both PI output voltage control and MPPT PLECS® simulations. Under varying irradiance and temperature conditions, the converter maintained accurate power point tracking and stable output voltage, confirming its suitability for photovoltaic integration and energy management in DC powered systems. Ethics and consent Ethical approval and consent were not required. Data availability No data associated with this article. Acknowledgments Authors would like to acknowledge the Instituto Politécnico de Lisboa (Polytechnic University of Lisbon), Portugal, (IPL/ IDI&CA2024/ResCONVERT_ISEL) for using the facilities of the institution and also the Instituto Superior de Engenharia de Lisboa (ISEL), Portugal, for all the experimental laboratory support. References 1. Vakacharla VR, Gnana K, Xuewei P, et al.: State-of-the-art power electronics systems for solar-to-grid integration. Solar Energy. 2020; 210: 128–148. Publisher Full Text 2. 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Muhammad M, Armstrong M, Elgendy MA: A nonisolated interleaved boost converter for high-voltage gain applications. In: IEEE J Emerg Sel Top Power Electron. 2016; 4(2): 352–362. Publisher Full Text Page 36 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Open Peer Review Current Peer Review Status: Version 2 Reviewer Report06 November 2025 https://doi.org/10.21956/openreseurope.23466.r62941 © 2025 Asapu S. This is an open access peer review report distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Siva Asapu Shri Vishnu Engineering College for Women, Bhimavaram, Andhra Pradesh, India I am satisfied with the revised version of the article. The authors have adequately addressed the previous comments and incorporated the necessary revisions into the manuscript. I have no further comments to make. Competing Interests: No competing interests were disclosed. Reviewer Expertise: DC - DC converters, MPPT and multilevel inverters I confirm that I have read this submission and believe that I have an appropriate level of expertise to confirm that it is of an acceptable scientific standard. Version 1 Reviewer Report08 August 2025 https://doi.org/10.21956/openreseurope.21228.r55982 © 2025 K R. This is an open access peer review report distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Rachananjali K Vignan Foundation for Science Technology & Research, Guntur, Andhra Pradesh, India Authors have addressed the issues and focused on extended voltage gain and reduced switch count. Open Research Europe  Page 37 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Topology is being implemented for photovoltaic application. Theirinvestigation method was based on an initial theoretical approach using mathematical equations to describe the operation of the electrical circuit and evaluate the performance compared to other topologies, followed by the validation through some computational simulations using MATLAB/SIMULINK software. Next, the operation of the proposed converter was also confirmed by several experimental tests using a laboratory prototype developed exclusively for these tests. Is the work clearly and accurately presented and does it cite the current literature? Yes Is the study design appropriate and does the work have academic merit? Yes Are sufficient details of methods and analysis provided to allow replication by others? Yes If applicable, is the statistical analysis and its interpretation appropriate? Yes Are all the source data underlying the results available to ensure full reproducibility? Yes Are the conclusions drawn adequately supported by the results? Yes Competing Interests: No competing interests were disclosed. Reviewer Expertise: Renewable and converters I confirm that I have read this submission and believe that I have an appropriate level of expertise to confirm that it is of an acceptable scientific standard. Reviewer Report12 June 2025 https://doi.org/10.21956/openreseurope.21228.r54070 © 2025 Asapu S. This is an open access peer review report distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Siva Asapu Shri Vishnu Engineering College for Women, Bhimavaram, Andhra Pradesh, India The paper describes an Interleaved Quadratic Boost DC-DC Converter. The topic of Interleaved Open Research Europe  Page 38 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Quadratic Boost Converters has been widely explored in the literature over the past few decades. Various studies have discussed different topologies and designs aimed at achieving high-gain conversion and high efficiency. Therefore, determining the novelty of the proposed circuit is challenging. In the abstract, the author mentions the converter's efficiency values, but in the body of the article, the efficiency analysis is missing. Including the converter’s efficiency formulas, derivations, and equivalent circuit under non-ideal conditions would greatly enhance the reader's understanding of the converter's dynamic performance. While efficiency is a critical metric for DC-DC converters, its discussion in the manuscript is minimal. Please elaborate on how the efficiency was calculated, and provide deeper insights into switching and conduction losses. The authors are encouraged to include a discussion on voltage and current stress on key components, which would help evaluate the reliability of the proposed converter. The comparison section is incomplete and requires significant improvement. It should convincingly compare the proposed converter with existing topologies. Specifically, comparisons should include power losses (both switching and conduction), power density, efficiency, and other relevant performance metrics. In the manuscript, hardware results are presented and explained. However, the implementation details using MATLAB software are lacking—particularly with respect to the voltage and current waveforms of inductors, capacitors, and switches. There is no step response analysis presented for the converter. Including this analysis would significantly improve the understanding of the converter's dynamic performance. Detailed information on how the gate drivers are integrated into the circuit and the component selection criteria would also be beneficial. The quality of the figures throughout the manuscript is substandard. Most figures are lowresolution and appear pixelated, which hampers clarity and readability. It is recommended to provide high-resolution vector graphics (preferably in PDF or EPS format) to ensure clear visualization of plots and circuit diagrams. Is the work clearly and accurately presented and does it cite the current literature? Partly Is the study design appropriate and does the work have academic merit? Yes Are sufficient details of methods and analysis provided to allow replication by others? Partly If applicable, is the statistical analysis and its interpretation appropriate? Yes Open Research Europe  Page 39 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025 Are all the source data underlying the results available to ensure full reproducibility? Yes Are the conclusions drawn adequately supported by the results? Yes Competing Interests: No competing interests were disclosed. Reviewer Expertise: DC - DC converters, MPPT and multilevel inverters I confirm that I have read this submission and believe that I have an appropriate level of expertise to confirm that it is of an acceptable scientific standard, however I have significant reservations, as outlined above. Open Research Europe  Page 40 of 40 Open Research Europe 2025, 5:55 Last updated: 06 NOV 2025