Binary Neural Networks for FPGAs

Binary Neural Networks for FPGAs August 2025 Author: Maria Mastoreka SUPERVISORS: Ioannis Xiotidis David Reikher David Miller openlab summer student report CERN openlab Report // 2025 2 Binary Neural Networks for FPGAs ABSTRACT This report investigates the feasibility of implementing Binary Neural Networks (BNNs) for real-time tau identification in the ATLAS Level-0 trigger, in the context of the ATLAS Phase-II Upgrade and the Next Generation Global Trigger project. BNNs, which operate with binary weights and activations, offer a promising solution by drastically reducing power consumption and FPGA resource usage. In this study, BNN architectures are evaluated against Convolutional Neural Network (CNN) baselines in terms of suitability for hardware deployment. The models are designed to process calorimeter data, specifically from the Liquid Argon (LAr) electromagnetic calorimeter, to identify tau leptons in real time. Selected models will be implemented on FPGAs using the HLS4ML framework, with the goal of comparing resources used and efficiency. CERN openlab Report // 2025 3 Binary Neural Networks for FPGAs TABLE OF CONTENTS INTRODUCTION .................................................................................... 4 ATLAS Detector and Calorimeter ................................................................................................... 5 Triggers and TDAQ ...................................................................................................................... 5 FPGAs in ATLAS Triggers .............................................................................................................. 6 Project Overview Workflow ........................................................................................................... 6 Convolutional Neural Networks (CNNs) .................................................................................... 6 Input Clustering and Preprocessing .............................................................................................. 6 Evaluation with ROC / AUC .......................................................................................................... 7 Binary Neural Networks (BNNs) ................................................................................................. 8 What are BNNs? ........................................................................................................................ 8 Brevitas and Bi-Real Net Architecture ............................................................................................ 9 BNN Evaluation ……………………………………………………..…………………………………………………………….. 10 HLS4ML implementation ......................................................................................................... 10 Conclusion .............................................................................................................................. 11 References ............................................................................................................................... 12 CERN openlab Report // 2025 4 Binary Neural Networks for FPGAs 1. INTRODUCTION All major CERN experiments, including ATLAS, are entering a new phase of upgrades in preparation for the High-Luminosity Large Hadron Collider (HL-LHC). As part of the ATLAS Phase-II Upgrade, one of the most critical developments involves improving the trigger and data acquisition (TDAQ) systems. A central goal is to extract more information and enable more advanced algorithms at the hardware trigger level. A description of the ATLAS detector and its main components is necessary to provide the proper context. Figure 1 ‘Schematic overview of the ATLAS Phase-II Trigger and Data Acquisition (TDAQ) system, consisting of the Level-0 hardware trigger, the Dataflow system, and the Event Filter. The Level-0 trigger processes detector data at 40 MHz and issues accept decisions within 10 µs, while the Event Filter reduces the event rate to ~10 kHz for permanent storage [8]’’ CERN openlab Report // 2025 5 Binary Neural Networks for FPGAs a. ATLAS Detector and the Calorimeter The ATLAS detector is a large, general-purpose experiment at the LHC, designed to observe and record the outcomes of proton-proton collisions, among other physics processes. One of its key subsystems is the calorimeter system, which measures the energy of particles produced in collisions by absorbing them and detecting their energy deposits [10]. The calorimeter system is composed of two main parts: 1. The Liquid Argon Calorimeter (LAr), which measures the energy of electrons, photons, and hadrons. Its central region is finely segmented and optimized for the identification of electrons and photons. The LAr system includes the electromagnetic (EM) and hadronic endcaps, as well as the forward calorimeter. 2. The Tile Hadronic Calorimeter, which surrounds the LAr calorimeter and measures the energy of hadrons that penetrate beyond the electromagnetic layers. It plays a complementary role by capturing hadronic energy not fully deposited in the LAr. b. Triggers and TDAQ The ATLAS Trigger and Data Acquisition (TDAQ) system is responsible for selecting the most interesting proton-proton collision events for physics analysis. In the Phase-II Upgrade, the system adopts a twolevel architecture [9][11]: 1. Level-0 Trigger (L0): Implemented in custom hardware, L0 receives inputs from the calorimeters and the muon system. It operates with a latency below 10 μs and an accept rate of up to 1 MHz. This stage is designed to apply more sophisticated algorithms than previous generations, enabling better real-time event discrimination. Figure 1 ''ATLAS calorimetry system'' CERN openlab Report // 2025 6 Binary Neural Networks for FPGAs 2. Event Filter (EF): Serving as the high-level trigger, the EF is based on a large processing farm complemented by custom hardware accelerators. It performs near offline-quality reconstruction and reduces the data rate to approximately 10 kHz, which is stored permanently for physics analysis. As part of the HL-LHC preparations, ATLAS is upgrading its trigger system to handle higher data rates and more complex events. The Next Generation Trigger (NGT) project focuses on enhancing real-time event selection using high-granularity calorimeter data and advanced algorithms, including AI-based methods [3]. c. Field Programmable Gate Arrays (FPGAs) in ATLAS Triggers Field-Programmable Gate Arrays (FPGAs) are reprogrammable integrated circuits that allow for the implementation of flexible digital logic. In the ATLAS trigger system, FPGAs are used extensively due to their ability to perform real-time, parallel processing with ultra-low latency, often below 1 μs. These characteristics make them ideal for fast decision-making at the Level-0 hardware trigger. However, the challenge is not the FPGA devices themselves, but the demanding environment in which they are used: extremely high data throughput, strict latency requirements, and the complexity of reconstruction algorithms. These factors translate into constraints on power consumption (driven by high switching activity) and FPGA resources (logic, memory, and input bandwidth). To meet these challenges, efficient machine learning models, such as Binary Neural Networks (BNNs), are explored to maximize performance within the available hardware budgets. d. Project Workflow Overview The project began with the development of a baseline model using CNNs to classify tau candidates from calorimeter data. CNNs were chosen for their ability to capture spatial features and were evaluated using standard performance metrics, including the Receiver Operating Characteristic (ROC) curve and the Area Under the Curve (AUC). Once the baseline was established, a BNN was implemented, replacing the weights and activations with binary values to significantly reduce resource usage. The final goal was to deploy both models on FPGAs using the HLS4ML toolchain, which required exporting the networks to ONNX and QONNX formats for compatibility with hardware synthesis. 2. Convolutional Neural Networks (CNNs) For the first stage of the project, a baseline classifier using a CNN was built and trained to distinguish truth-matched tau leptons from Quantum Chromodynamics (QCD) background based on calorimeter data. The network operated in 32-bit floating point precision, offering high accuracy but with increased resource cost. a. Input clustering and preprocessing Training was performed using 12×12 cluster images, representing energy deposits in a Δη × Δφ window of 0.3 × 0.3, centered on tau candidates (signal) or eFEX seeds (background) the Regions of Interest identified by the Level-0 electron Feature EXtractor, used for electron/photon/tau candidate finding. CERN openlab Report // 2025 7 Binary Neural Networks for FPGAs Each image pixel corresponds to a cell from the EM2 layer (the finely segmented second sampling layer of the LAr electromagnetic calorimeter), encoded with 16-bit transverse energy (Et). To generate training samples, calorimeter cells were grouped into clusters around physics objects of interest: • Signal: Cells were clustered around truth taus from the γ*→ττ sample using a Δφ and Δη window. • Background: Clusters were formed around eFEX RoIs (Regions of Interest) from a low-pT dijet sample (0-20 GeV dijets), representative of QCD background jets. After filtering EM2 cells (sampling == 2), clusters were converted into 12×12 images and normalized using the per-image max (Et) method. Only events with nonzero energy clusters were kept. Figure 1 displays the EM2 calorimeter cells displayed in η-φ space for selected signal events and Fig.2 two examples of signal and background normalized as 12×12 input images used for training. Figure 2: EM2 calorimeter cells displayed in η-φ space for selected signal events. The colour indicates the local density of calorimeter cells. The red boxes mark the Regions of Interest (RoIs) centred on truth-matched tau candidates. Figure 3: Examples of signal (left and background (right)) normalized 12×12 input images used for training. CERN openlab Report // 2025 8 Binary Neural Networks for FPGAs b. Evaluation with ROC /AUC The baseline CNN model achieved strong classification performance with an AUC of approximately 0.84, using a full-precision architecture of around 90.000 trainable parameters. To explore resourceefficient alternatives, a reduced CNN variant with only ~6.000 parameters was also evaluated, resulting in an AUC of 0.807, as shown in Fig. 5 below. Figure 5: AUC result of CNN with ~6k parameters Despite the significant reduction in model complexity, the performance remains competitive, highlighting the potential for further compression through binary quantization. 3. Binary Neural Networks (BNNs) a. What are BNNs A BNN is a type of neural network in which both activations and weights are represented as 1-bit values in all hidden layers, except for the input and output layers. BNNs can be considered as a highly compressed version of CNNs, with the main difference being the numerical precision used in internal computations. BNNs aim to binarize the 32-bit floating-point values typically used in CNNs into 1-bit representations. Instead of performing expensive floating-point multiplications, BNNs use lightweight bitwise XNOR operations. It has been reported that BNNs can achieve up to 32 times better memory savings and 58 times faster convolution operations compared to standard 32-bit CNNs. In BNNs, the sign function is commonly used for binarizing both activations and weights: CERN openlab Report // 2025 9 Binary Neural Networks for FPGAs After binarization, activations I, and weights W will be: I  sign(I) = BI , W  sign(W) = Bw. Figure 4: Convolution Process of Binary Neural Networks [1] . b. Brevitas and Bi-Real Architecture To implement BNNs in this work, the Brevitas library was employed, a PyTorch-based framework designed for quantization-aware training. The architecture followed the Bi-Real Net design, which introduces real-valued shortcut connections in addition to the binary layers. These shortcuts help to preserve information during forward propagation and support more stable gradient flow during training, addressing common issues in BNNs such as information loss and vanishing gradients. This structure allows the network to benefit from the efficiency of binarized operations while maintaining competitive performance. The first and last layers were kept in higher precision, a common strategy in BNN design to reduce accuracy degradation. The resulting model mirrors the original CNN baseline in structure, enabling a fair comparison between full-precision and binary implementations in both accuracy and hardware compatibility [2]. Figure 6: CNN and BNN Bi-Real Net architecture.'