Low Cost FPGA Implementation of Convolutional Neural Network Based Image Classifier

Journal of Embedded & Digital System Design 2025, VOL. 01, NO. 1, 1–11 https://doi.org/10.5281/zenodo.17678700 Low Cost FPGA Implementation of Convolutional Neural Network Based Image Classifier Shirshendu Roy1,Sainath Reddy K2,Harshith GV3,Rakshith R4, and Prajwal M5 1-5Electronics and Communication Department, Dayananda Sagar University, Bengaluru, India Abstract Artificial intelligence and machine learning (AI-ML) algorithms gave a new direction to the problem of image classification. All practical applications are nowadays applying AI-ML algorithms for image classification. Convolutional neural network (CNN) and its varieties rapidly became researcher’s first choice for computer vision related applications. Recently many implementations of hardware accelerators for CNN are reported in literature. The current work exploits the opportunities for improvements and proposes a novel very large scale integrated circuit (VLSI) architecture for classic CNN model for classification of gray-scale images. The proposed architecture is validated using field gate programmable array (FPGA) platform for classification of handwritten digits and hand gestures. The architecture is implemented on both Artix7 and Zynq FPGA board. This work achieves 96% classification accuracy for digits detection and 97% accuracy for gesture images using same CNN model with pre-defined filters in the convolution stage. Proposed architecture consumes less hardware resources compared to state-ofthe-art works by using a single vector multiplication unit (VMU) for both convolution-pooling stage and fully connected network. Architecture supports parallel convolution and pooling operation and achieves processing speed of ≈16 µs per image frame of size 28×28. Also, the architecture is scalable and supports deep learning where more number of convolution-pooling stages may be used. Keywords: Convolutional Neural Network, HandWritten Digit Recognition, Gesture Detection, Machine Learning, Field Programmable Gate Array (FPGA) 1 Introduction Image classification is one of the prominent research problem in the domain machine learning (ML). Few applications can be named as categorization of vehicles [1] for traffic control, hand written digit recognition [2], object detection [3], classification of RADAR images [4] etc. Various algorithms and techniques are reported in literature for efficient classification of images. Out of these ML algorithms, convolution neural network (CNN) is a crucial neural network (NN) for image classification. Over the few years, many researchers have tried to implement the CNN technique on hardware platform. Initially, CNN was implemented on central processing units (CPUs) and then realized using graphics processing units (GPUs). But it has been noticed that reconfigurable hardware like field gate programmable arrays (FPGAs) have more power to accelerate the parallel processing involved in CNN. Gradually, many research works published focusing FPGA implementation of CNN. Few implementations are either ARM controller based or realized using high-level synthesis (HLS). A high-level language based accelerator for convolution layer is reported in [5]. Another Vivado HLS based implementation is reported in [6]. Skynet model for CNN is implemented on ARM processor based FPGA in [7]. A FIFO based accelerator for CNN is presented in PYNQ board based implementation [8]. An ARM controller based accelerator for CNN is reported in [9]. Another work on FPGA based CNN accelerator is reported in [10]. Authors in [11] tried to optimize the FPGA implementation of CNN accelerator by exploiting sparsity in weight matrix and also by using hierarchical memory organization. CNN is implemented on FPGA through Vivado HLS software for traffic light image classification in [12]. Handwritten digits classifier is implemented on FPGA using SIMULINK platform in [13]. A ZCU102 development board based specialized accelerator is reported in [14] that supports parallel execution of convolution layers. An ResNet like structure of CNN is implemented on ZCU102 device for RADAR signal processing in [4] using HLS. Authors in [2] implemented CNN on Intel FPGA for detecting handwritten digits using MNIST dataset and achieved 90% accuracy. Another FPGA implementation of CNN is reported in [15] for pattern recognition. FPGA Implementation of processing element unit in CNN accelerator using Modified Booth multiplier and Wallace tree adder on Uniwig architechture is reported in [16]. Researchers have presented FPGA based CNN module for the recognition of traffic sign in advanced driver assistance system (ADAS) in [1]. CNN is implemented on FPGA for face recognition in [17]. Another FPGA implementation of CNN is reported in [18]. A multi-stage data flow implementation of CNN accelarator for 3-D images for object recognition is presented in [19]. FPGA implemented CNN processor reported in [3] used for unmanned aerial vehicle (UAV) object detection. CNN accelerator is used for environmental sound classification and implemented on FPGA in [20]. A version of MobileNet structure is implemented on FPGA for image classification in [21]. CNN also can be used for pattern detection from images [22]. Authors in [23] tried to reduce the computational comManuscript received 03 September, 2025; accepted 03 November, 2025; Date of publication 21 November, 2025; (Corresponding author: Shirshendu Roy, e-mail: shirshenduro[email protected]. Low Cost FPGA Implementation of Convolutional Neural Network Based Image Classifier 2 plexity using Winograd’s 2-D Minimal filtering algorithm. In [24], authors have demonstrated a stochastic based deep neural network system that has nearly the same accuracy as conventional binary implementations. An CNN accelerator is proposed in [25] where multiplication operations are replaced with shift operations to reduce complexity. A roofline-model-based method to accelerate the performance of FPGA implemented CNN processor is reported in [26] where authors used floating point to represent the data. An efficient FPGA implementation of AlexNet CNN structure is reported in [27] for real time object detection. Here, authors have shown accelerators for both convolution and fully connected layers. Systolic multipliers were used in [28] to improve the performance of matrix multiplications in CNN. ZynqNet CNN architecture is implemented on FPGA to increase the processing speed in [29]. VGG16-SVD model of CNN is implemented on embedded FPGA platform like ZYNQ in [30]. An application specific integrate circuit (ASIC) implementation of reconfigurable processor for deep neural networks (DNN) is reported in [31] which implements VGG-16 and AlexNet architecture of CNN. Even though plenty of works are reported in literature on hardware implementation of CNN based image classification, there are scopes of improvement. The major contributions of this research are •An innovative hardware accelerator for CNN is presented which is very fast and consumes minimal hardware resources. •The proposed hardware accelerator supports any number of convolution-pooling layers and thus supports for DNN based image classification. •A method of sharing hardware for vector inner products in convolution stage as well as in fully connected layers is proposed. •Maximum resource sharing and the proposed serialparallel accelerator for convolution-pooling step makes the proposed architecture efficient in terms of resource utilization and power consumption compared to other works. The manuscript is organized in five sections. The literature review on state-of-art works on hardware implementation of CNN is presented in Section I. The theoretical background behind the CNN technique is discussed in Section II. Section III presents the proposed work in details and all the architectures are illustrated here. Section IV discusses the experimental set-up and proposed design is also analysed in this section. Lastly, conclusive remarks are made in the last section (Section V). 2 Theoretical Background Many models of CNN for image classification are proposed over the years like LeNet, AlexNet, VGGNet, MobileNets etc. A basic LeNet kind of model is implemented in this work which is good for detecting sparse images like handwritten digits and gestures. CNN based image classification is divided into two major blocks which are convolution-pooling network (CPN) and fully connected network (FCN). Overall CNN model structure is shown Fig. 1 and many basic applications use this kind of CNN models. Square image is considered here for simplification of illustration but images can be of any size practically. In the CPN block, there may be many two dimensional convolution stages. In a convolution stage, a 2-D image (I∈ Rn×n) is convoluted with a filter (f) of size λ×λand resulted another image Ic. The function for 2-D convolution is shown in Algorithm 1. The size of filter can vary based on application to application. Common choices are 3×3, 5 ×5, 7 ×7 etc. Each convolution stage is associated with a pooling stage or sub-sampling stage. The convoluted image (Ic) is converted to a sub-sampled image (Ip) by finding maximum, minimum or by performing averaging operation on particular window. Max pooling technique is adopted in this work and a general function is shown in Algorithm 2. The size of this window is famously known as stride (s). Stride of 2 is selected here this means the window size is 2×2. An n×nimage is converted to n 2×n 2after pooling operation. The overall CNN algorithm is shown in Algorithm 3. The CPN block provides a flattened vector (y∈ Rn5×1) to the FCN block. FCN block is constituted of two stages, input layer with n6nodes and output layer with n7nodes. Input layer takes yvector and produces another vector (z1) of size n6×1. Flattened vector yis multiplied by a weight matrix of W1∈ Rn5×n6and added with a bias vector b1∈ Rn6×1. Activation functions are integral part of CNN models. Algorithm 1 Function for 2-D Convolution (Ic= conv(I, f)) Input: Input image I∈ Rn×nand filter kernel f∈ Rλ×λ. Output: Convoluted image Ic∈ R(n−λ−1)×(n−λ−1). 1: for i←1 to (n−λ−1) do 2: for j←1 to (n−λ−1) do 3: tmp ←0 4: for k←1 to λ−1do 5: for l←1 to λ−1do 6: tmp =tmp +I(i+k−1, j +l−1) ·f(k, l) 7: end for 8: end for 9: Ic(i, j) = tmp 10: end for 11: end for Different features are extracted from the images based on the variety of activation functions. Activation functions are applied on output of every layer in the FCN block. CPN block also sometimes uses activation functions for better results. Commonly used activation functions are rectified linear unit (ReLU), sigmoid function, softmax function etc. Proposed work uses ReLU function for having less complexity in hardware implementation. Vector z1from the input layer is passed through a ReLU function to produce another vector r1. 3Journal of Embedded & Digital System Design Convolution1 (4 ×n1×n1) Pooling1 (4 ×n2×n2) Convolution2 (16 ×n3×n3) Pooling2 (16 ×n4×n4) image (n×n) Flattening (n5×1) I/P Layer (n6nodes) O/P Layer (n7nodes) Fully Connected Network (FCN) Convolution and Pooling Network (CPN) Figure 1: Overall model for convolutional neural network for handwritten digit recognition. Similar computation is carried away in the output layer also. Output layer receives the vector r1and produces another vector z2of size n7×1. The vector r1is multiplied with weight matrix W2∈ Rn6×n7and added with bias vector (b2) of size n7×1 to produce output vector z2which is again passed to ReLU function to generate r2vector. Finally, r2vector is passed to a sort function which finds index of the maximum value present in the r2 vector. This index represents the detected class for the image database. Algorithm 2 Function for max pooling (Ip= max pool(Ic, s)) Input: Input image Ic∈ Rn×nand stride number (s). s is even for even nand odd for odd value of n. Output: Image after max pooling Ip∈ R(n/s)×(n/s). for i←1 to (n/s)do for j←1 to (n/s)do tmp ←0 Set rw = ((i−1) ·s+ 1) : (i·s) Set cl = ((i−1) ·s+ 1) : (i·s) Ip(i, j) = max(I(rw :cl, rw :cl)) end for end for 3 Proposed Work The proposed architecture is shown in Fig. 2. and it has three major blocks viz. vector multiplication unit (VMU), CPN block, and FCN block. The VMU block is shared by both CPN and FCN blocks. The input image can be directly fed to the CPN block or can be passed through a pre-processing block which is not shown here. Here, vector pdenotes the pixels belonging to the λ×λwindow selected during convolution. All three blocks are described in three sections below. 3.1 Vector Multiplication Unit A VMU block is proposed in this work which performs vector-multiplication operations involved in the FCN block and also performs multiplication between image pixels in a particular window and filter co-efficients. Algorithm 3 Pseudo code for CNN based image classification. Input: Input image I∈ Rn×n, stride value (s), and filters (f1, f2,· · · , f8). Output: Classified image index (idx). for j←1 to 2 do if j←1then for i←1 to 4 do Ij ci =conv(I, fi) Ij pi =max pool(Ij ci,2) end for else for k←1 to 4 do for l←1 to 4 do Ij ckl =conv(I(j−1) pk , fl+4) Ij pkl =max pool(Ij ckl,2) end for end for end if end for z1=W1·y+b1 r1=ReLU(z1) z2=W2·r2+b2 r2=ReLU(z2) idx =sort(r2) Convolution and Pooling Network Vector Multiplication Unit Fully Connected Network ip1 ip2 ip3 ip4 in image p vp mb out2 idx Figure 2: Overall proposed architecture image classification using CNN. Low Cost FPGA Implementation of Convolutional Neural Network Based Image Classifier 4 IP 16 IP 16 IP 16 IP 16 ip1 ip2 ip3 ip4 a1:16 b1:16 a17:32 b17:32 a33:48 b33:48 a49:64 b49:64 vp Figure 3: Proposed vector multiplication unit. Thus same VMU block, shown in Fig. 3, is shared by CPN and FCN block. This way maximum resource sharing is obtained. The whole VMU block is capable of multiplying two vectors of length 64 and divided into four IP 16 blocks. Each IP 16 block is capable of multiplying two vectors of length 16. The IP 16 blocks are used during the convolution process and the whole VMU block is used during computation of fully connected layers. VMU has total 5 outputs where four inner product outputs are from IP 16 blocks. Latency of the IP 16 blocks is of l1p= 6 clock cycles and total latency (lvmu) of the VMU block is 8 clock cycles. 3.2 Convolution-Pooling Network Proposed architecture for CPN block is shown in Fig. 4. Initially input image is written in the img ram block from the image sensors. Image pixels are serially sent to the window op block for window formation. The pixels from the k×kwindow are sent in parallel to the IP 16 blocks for computing convolution values. The convoluted image pixels are simultaneously sent to the mx pool blocks. Four mx pool blocks are placed corresponding to four IP 16 blocks. Convolution and pooling operations runs in parallel having gape of few clock cycles. The output data samples from the first convolutionpooling stage are written to membank a which is having four memory elements to support four pooling blocks. The ram blocks from membank a are read serially. Data samples from ram1 are read and fed to img ram block again to start the next phase convolution operation. Output of the next phase convolution will again go through IP 16 and mx pooling blocks. Final output data samples of the next convolution stage are written to membank b which is also having four memory elements. Once the convolution operation is completed for data samples stored in ram1, 2nd phase convolution operation is started on samples stored in ram2. This way all the elements of membank a are read. All the outputs in the 2nd convolution-pooling stage are written to membank b. The pooling block is placed just after the IP 16 blocks to reduce the storage requirement. The size of membank a is more compared to size of membank b. Major operations that this block performs are 2-D convolution, pooling and temporary data storage. All these operations are explained below in detail. 3.2.1 Convolution The proposed architecture for 2-D convolution operation is depicted in Fig. 4. The 2-D convolution operation can be divided into two steps, windowing operation and multiplication of window pixels with filters. The multiplication of pixels belonging to particular window and the filter co-efficients are performed by IP 16 blocks. The architecture supports simultaneous 2-D convolution with four λ×λfilters where λ= 3 chosen for this work. The advantage of simultaneous convolution is that same image is not required to be read every time. If the convolutions were separately done, then input image has to be read four times. This way window operation time for image is saved but number of IP 16 blocks are increased. The convolution architecture is mainly based on the architecture of window op block which is shown in Fig. 5. The low-cost architecture reported in [32] is adopted in this work. Register based window operation architecture reported in [17] is not flexible for variable image sizes. This is why memory based architecture is preferred which supports any image size by changing size of the address counters. This block forms the window of λ×λpixels and these pixels are sent to the IP 16 blocks. For convolution, outputs from the input image are parallely computed through four IP 16 blocks. This work uses pre-defined filters [33] where four filters are used in the first stage and four filters are used in the second stage. The first stage filter co-efficients are f1={1,0,−1,1,0,−1,1,0,−1}(1) f2={1,1,1,0,0,0,−1,−1,−1}(2) f3={1,2,1,0,0,0,−1,2,−1}(3) f4={−1,2,−1,0,0,0,1,2,1}(4) The second stage filter co-efficients are f5={−1,−1,−1,2,2,2,−1,−1,−1}(5) f6={−1,2,−1,−1,2,−1,−1,2,−1}(6) f7={2,−1,−1,−1,2,−1,−1,−1,2}(7) f8={−1,−1,2,−1,2,−1,2,−1,−1}(8) The multiplication operation between a filter and an image window is performed by IP 16 blocks. Selection of filters in different stages are performed by a multiplexer banks placed before VMU block. For an n×nimage, (n−1) rows will be stored in the temporary buffer memory. In this work, 3×3 window is used for convolution and IP 16 block has 4 pipeline stages. Convolution operation has total latency of lip +3 clock cycles where lip is the latency of the IP 16 block. Thus total convolution process takes tcnv =n2+lip+ 3 clock cycles for completion. 3.2.2 Pooling A simple architecture for max pooling is proposed in this work and shown in Fig. 6. It uses one temporary memory which is capable of storing one row of image. Only alternate rows of convoluted image are written in the memory. For example, first 1st row is written to the memory. Second row is then directly going to the registers and simultaneously the first row is also read. In the second cycle 3rd row will be stored in the memory and 4th 5Journal of Embedded & Digital System Design window op IP 16 p1 p1 p9 img ram 0 1 in image IP 16 IP 16 IP 16 mx pool mx pool mx pool mx pool ram1 ram5 0 0 1 2 3 reg ram2 ram3 ram4 1 2 3 ram6 ram7 ram8 mb out2 membank a membank b mb out1 Figure 4: Proposed architecture for convolution and pooling in CNN. row tmp row tmp reg reg reg reg reg reg reg reg reg 0 1 0 1 0 1 p1 p2 p5 p4 p7 p8 p9 p6 p3 Figure 5: Windowing architecture for 2-D convolution [32]. reg reg BN reg BN reg max row tmp1 data in Figure 6: Proposed structure for max pooling. row will be fed directly to registers. Pooling block computes maximum of all pixels present in a 2 ×2 window. An basic network (BN) block architecture, shown in Fig. 10, is designed to calculate maximum of two elements. First BN block computes maximum of 1st two elements of 2×2 window and stores in a register. In the next clock cycle, first BN block computes maximum of remaining two elements. Second BN block, compares between previously stored maximum value and newly computed value. The pooling operation is done by serially accessing the rows of convoluted images. For an n×nimage, n/2 columns are required to be stored in temporary memory while n/2 columns are read directly. Thus total tpl =n2+lpl clock cycles are required to complete the pooling process with latency of lpl = (2n+ 2) clock cycles. 3.3 Fully Connected Network The proposed architecture of FCN block is shown in Fig. 7. The serial-parallel architecture supports any number of fully connected layers. Same VMU block is used in this architecture to do the vector-matrix multiplications. The multiplication between input vector and the weight matrix is performed in many phases to have less hardware consumption. Four 2:1 multiplexer banks are placed just before VMU block. The control signal cnv mode selects image pixels and the filter co-efficients. The control signal nxt cnv selects 2nd set filter co-efficients. Big arrows denote vectors in the multiplexer banks. The FCN block receives flattened vector samples from membank b block of convolution and pooling block. Memory elements in membank b block are read serially. Serial data samples are converted to parallel data vector through two register banks. Data samples are written to reg bank1 first and then to reg bank2. Again the remaining samples are written to reg bank1 and then to reg bank2. The control signal phase selects between two reg banks. Gap between two writing cycles is maintained to support the consecutive reading of weight matrix blocks from weight memory block. Other blocks in the FCN block are illustrated below. 3.3.1 Weight Memory The weight matrices are stored in weight mem memory block. The weight matrices are constant and thus only read only memory (ROM) elements are used in this memory block. The multiplication of vectors of bigger sizes are folded by the VMU unit of lesser size. Thus the weight memory has to be organized properly. The organization of the weight mem memory block is shown in Fig. 8. Both W1and W2weight matrices are stored in a single memory block. The organization of the weight mem memory block is shown for handwritten digit recognition problem. Total 64 ROM elements are used here and each ROM can store 1100 words. The shaded area denotes the memory locations filled with zeros. 3.3.2 Accumulator Block Multiplication between a vector and the weight matrix is performed in many phases with the help of accumulator block shown in Fig. 9. The partial inner products are stored in a temporary memory block named mem temp in all phases except in the last phase. The temporary products are read from mem temp block and added with current inner products. Once the final vector-matrix product is obtained, bias values are read Low Cost FPGA Implementation of Convolutional Neural Network Based Image Classifier 6 reg bank2 reg bank1 0 0 weight mem 1 1 1 0 0 1 {f11,· · · f14} {f21,· · · f24} V MU accumulator activation function sort a b p 0 1 mb out2 from membank b mux bnk idx Figure 7: Proposed architecture for the FCN block 1 64 1 120 56 840 960 1080 1090 1100 W2 W1 m1 m8 m9 m10 m11 Figure 8: Proposed arrangement of the weight memory. from mem bias block and added. Accumulator needs one clr signal to clear the register at initial stage and one multiplexer is placed to send zeros in the last phase of accumulation. Here a single mem bias memory holds all the bias vectors. 3.3.3 Activation Function ReLU activation function is used in all the layers of FCN block. This is because simplicity of ReLU function in hardware implementation and accuracy is also within acceptable range. The ReLU function is shown as f(x) = max(0, x) (9) ReLU function returns xif xis greater than zero. A single multiplexer is enough to implement the ReLU function. 3.3.4 Sort Block A sort block, shown in Fig. 10, is placed at the final stage of FCN block. Once the computation is completed for all the layers in FCN block, the serial data samples from the activation function block are fed to the sort block. The indx in passes digit indices from 0 to 10 and must be in sync with the data stream (data in). This block gives the index of the maximum data present in the serial stream. The index (idx) denotes the identified class + reg reg + mem bias reg mem temp 0 1 0 nxt lyr Figure 9: Proposed architecture for the accumulator block. of the images. Major components of the BN block are a comparator and a multiplexer. Indices are registered in the fdc block using the less than (lt) control signal. 3.4 Support for Deep Neural Network The proposed architecture can be easily adopted for DNN based image classification using CNN. In the classification of more complex images, CNN may use more number of convolution and pooling layers. Also, one or more hidden layers may exist in the FCN. The proposed architecture uses two kinds of memory banks membank a and membank b. Present work uses two convolution-pooling layers. Output of first convolution-pooling layer is stored in membank a whereas output of second convolutionpooling layer is stored in membank b memory bank. In case of an additional convolution-pooling layer, convolution and pooling will be applied on data stored on membank b and should be stored in membank a. This 7Journal of Embedded & Digital System Design reg a b COMP n 0 1 reg data in clr fdc 4 indx in lt c BN Figure 10: Proposed architecture for the sort block. means, in odd number of convolution-pooling layer data will be stored in membank a and in even number data will be stored in membank b. A 2:1 multiplexer can switch data transfer to the img ram between mb out1 and mb out2. The FCN block also supports more number of hidden layers. The size of the weight matrix will vary based on the number of layers in the FCN. Based on the given size of VMU, the number of loops in calculation of output will increase. The size of VMU can be increased to reduce number of iterations. To support increased size of VMU, size of reg bank and size of mux bank are required to be increased. Also, data width of the accumulator block is also may needs increment. 4 Experimental Setup and Performance Analysis The proposed architecture for CNN based handwritten digit classifier is validated by taking popular MNIST data base for handwritten digits ranging from 0 to 9. The dimension parameters used for the CPN block of CNN model are n= 28, n1= 26, n2= 14, n3= 12, and n4= 6. In the FCN block, size of the flattened vector is 576×1, 120 nodes were used in the input layer, and the output layer has only 10 nodes corresponding to 10 different digits. Proposed CNN model achieves 96% accuracy in case of digit recognition. A free data base on hand gesture recognition from Kaggle is also used to verify the proposed architecture. Original size of the images is 640 ×240 but images were converted to the size of 28 ×28 for verification. An accuracy of 97.9% is achieved for the case of gesture recognition. Python based software analysis were carried out in this work and Verilog HDL is used to design the architecture in Vivado. An experimental setup for handwritten digit recognition is shown in Fig. 11. Proposed architecture uses 18bit data-width for representing the data samples and 10bits are used for precision. The processing subsystems (PS) part is used for interfacing the USB camera and programmable logic (PL) part used for implementing the CNN part. Detailed analysis of the proposed design is Figure 11: Experimental setup for real-time detection of handwritten digits using proposed architecture implemented on Zynq FPGA. tcnv1cycles Convo 1 Convo 2 Convo 3 Convo 4 Convo 5 Pooling 1 Pooling 2 Pooling 3 Pooling 4 Pooling 5 tgp tgp1 tcnv2 tpl1cycles tpl2 Figure 12: Scheduling of all convolution and pooling operations in different stages of CNN. carried out in the following sub-sections. 4.0.1 Processing Time The estimation of processing time is one of the major metric that should be analysed. Processing time of all the blocks are analysed in this section. Scheduling of the operations like convolution and pooling are performed such a way so that in no time span a block should be in idle mode. The writing of image pixels in the img ram block and first convolution operation can be started simultaneously with a gap of one clock cycle. The scheduling of the different convolution and pooling operations is shown in Fig. 12. The first convolution operation completed in tcnv1clock cycles. First pooling operation can be started just after a gap of tgp1= 2n+lip +3 cycles. Then after tpl1clock cycles first pooling operation can be completed. Second phase convolution operation can not be started immediately as size of the convoluted image after first convolution is less than the input image. Second phase convolution operation can be started after a gap tgp clock cycles and value of this is nearly equal to nclock cycles. Other convolution operations can be started immediately just finishing of the previous convolution operation. Similarly for the second phase pooling operations. The FCN block can only operate when the last convolution operation i.e. Convo 5 in Fig. 12 is completed. Matrix-vector multiplications in FCN block are performed in different phases. For the case of hand written digit recognition, multiplication between W1matrix and flattened vector (y) is performed in 9 phases. Each phase corresponds to multiplication of 120 ×64 matrix and 64 ×1 Low Cost FPGA Implementation of Convolutional Neural Network Based Image Classifier 8 Table 1: Estimation of hardware complexity Blocks Mult Comp Add sub Reg Mux/DeMux IP 16 16 0 15 31 0 V MU 64 0 63 127 0 mux bnk 0 0 0 128 256 accumulator 0 0 2 3 1 sort 0 1 0 3 1 window op 0 0 0 9 3 mx pool 0 2 0 4 2 Others 0 0 0 1 8 Table 2: Estimation of memory elements. Memory Elements Word Per Cycle BRAM Reg Write Read membank a 1 1 4 ×14 ×14 0 membank b 1 1 4 ×12 ×12 0 weight mem - 64 64 ×1100 0 mem temp 1 1 64 0 mem bias −1 586 0 row tmp 1 1 28 0 row tmp1 1 1 28 0 reg bank1 1 64 0 64 reg bank2 1 64 0 64 vector in input layer. The output phase computation is achieved in two phases. The total processing time for input layer is tfcn1= (lvmu +1)+(8·120)+1+64. Here, 64 clock cycles are required to store the output values again back to the reg bank block. Total processing time for the output layer is tfcn2= (lvmu + 1) + (2 ·10) + 2 including the time spend in the sort block. The estimation of the overall processing time can done by the following equation tov =tcnv1+tgp + 4 ×tcnv2+tfcn1+tfcn2(10) Total processing time for handwritten digit recognition problem of detecting a 28 ×28 image is 2706 clock cycles. Taking maximum frequency of 173.91 MHz, the processing time is calculated as tov = 2706 ·5.75ns = 15,560ns. It can be said that the CNN processor proposed in this work takes 15.56 µs to process one 28×28 image of handwritten digits. Approximately the proposed processor can process ≈64khandwritten digits of size 28 ×28 in just 1 second. 4.0.2 Resource Consumption An estimation of resource consumption of the proposed architecture in terms of basic blocks is shown in Table I. This manual estimation of the resources is required to have a clear picture of the overall architecture. It can be seen that maximum 64 multipliers are used in V MU block which is the major block of the architecture. The block with most combinational logic load is the mux bnk. The pipeline registers are inserted in suitable places to keep the maximum combinational delay less than or equal to the delay of a multiplier. Memory consumption overhead is another parameter Table 3: Design performance for the proposed architecture implemented on two different boards. Memory Elements Artix Board Zynq Board Values Util(%) Values Util(%) Slice LUT 3789 5.98 3870 21.99 Slice Reg 3301 2.6 35200 9.38 Occupied Slice 1445 9.12 1502 34.14 RAMB18 115 42.59 115 95.83 DSP48 64 26.67 64 80 Dynamic Power 0.399 W - 0.413 0 Figure 13: Estimation of power of the proposed architecture based on Vivado tool. that decides the performance of an architecture. Estimation of memory consumption of the proposed architecture is shown in Table II for handwritten digit example. The memory blocks weight mem and mem bias are realized using the ROMs. Other memory blocks such as membank a,membank b etc. are realized as dual port memory (DPM) block. The reg bank block is realized entirely using registers to make serial data stream to a parallel data vector. The size of the memory elements in Table II is shown with respect to the example of handwritten digit recognition for image size of 28 ×28. The FPGA implementation performance of the proposed architecture is shown in Table III. Here, two type of FPGAs are used to demonstrate the performance comparison. Artix7 FPGA board (xc7a100tftg256-2) has more resources compared to Zynq system on chip (SoC) board (XC7Z010). Resource consumption on both the boards is almost same but higher maximum frequency is achieved in case of Artix7 FPGA board. This is because of more area available for routing in Artix7. 4.0.3 Power Consumption The architecture for CNN is proposed such a way so that it consumes less area as well as low power. The power consumption of the proposed design is shown in Table II on both kind of FPGAs. The low power consumption of the proposed design is due to two main attributes followed in the design. Firstly, all the memory elements are equipped with controlled enable mechanism. The memory elements were made active when it was required. During other time they were inactive. Sec- 9Journal of Embedded & Digital System Design Table 4: Comparison with existing works on handwritten digit recognition using CNN. Blocks [6] [34] [35] [2] This Work FPGA Board xc7vx485 xc7a100 ZYNQ ZC702 Cyclone 10 xc7a100 Frequency (MHz) 150 300 166 150 173.3 Time (ms) 0.0254 0.041 0.151 0.0176 0.0157 DSP 638 0 95 274 64 Reg 66346 106400 27664 48765 3301 LUT 51125 15769 388361 12588 3789 Accuracy 96.8 90 99 97.57 96 ondly, sharing of resources helped to save extra resources which consumes power. The VMU block is shared by FCN block as well as by the CPN block. A detailed analysis of the power consumption is shown in Fig. 13. 4.0.4 Comparison with Existing Works A substantial collection of works reported in literature on hardware implementation of CNN. Few works focused only on convolution part of CNN while few implemented overall image classification problem using CNN. The current research work also focuses on implementation of the whole CNN based classifier. Proposed architecture is compared with few recent works in Table IV. The proposed work is hardware efficient as well as have lesser processing time compared to the work reported in [6]. Similar statement can be said regarding the work reported in [34] where same FPGA target is used. The ZYNQ based architecture [35] consumes more resources at less processing time compared to the work proposed here. Intel FPGA based implementation [2] has similar processing time but consumes higher resources. Overall, it can be concluded that the proposed design is hardware efficient compared to other works having better processing time. 5 Conclusion A low cost yet faster architecture of CNN is proposed in this work. The proposed architecture is implemented for 2 convolution-pooling layers and two layers in the fully connected network. But this architecture is scalable and supports any number of convolution-pooling layer and hidden layers in fully connected network. Thus image classification problems using DNN also can be solved using this architecture. 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