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Design and Simula ion o Low-Powe VLSI
Mul iplie Using Modi ied Boo h Algo i hm
1Zonnawada Chai hanya, 2Us hulamu i Penchalaiah
1Assis an P o esso , Depa men o ECE, Gee hanjali Ins i u e o Science and Technology, Nello e, India
2P o esso , Dean o SA&H & HOD, Depa men o ECE, Gee hanjali Ins i u e o Science and Technology, Nello e, India
Abs ac : E icien mul iplica ion is c ucial in digi al signal p ocessing and a i hme ic compu ing sys ems, pa icula ly on low-powe , po able
embedded pla o ms. The Modi ied Boo h algo i hm e ec i ely educes he numbe o pa ial p oduc s and imp o es pe o mance in
mul iplica ion ope a ions. This wo k p esen s he design and simula ion o a low-powe VLSI mul iplie using a modi ied Boo h encoding
scheme, op imized o educed swi ching ac i i y and minimized ha dwa e complexi y. The p oposed a chi ec u e is implemen ed in Ve ilog
HDL and e alua ed o powe , delay, and a ea using indus y-s anda d EDA ools. Simula ion esul s demons a e signi ican powe sa ings and
educed c i ical pa h delay compa ed o con en ional mul iplie s, making he design well-sui ed o high-pe o mance and ene gy-e icien digi al
sys ems.
Keywo ds: A i icial In elligence, Employee P oduc i i y, Small and Medium-sized En e p ises, O ganiza ional Pe o mance, Wo kplace
Inno a ion.
1 INTRODUCTION
Mul iplie s a e a c i ical componen o high-pe o mance VLSI sys ems, including DSP engines, wi eless communica ion uni s,
AI accele a o s, and embedded con olle s. As echnology scales, low-powe a i hme ic ci cui s ha e become essen ial o suppo
po able compu ing and ba e y-d i en pla o ms. In his con ex , Modi ied Boo h mul iplie s a e widely p e e ed because hey
educe he numbe o pa ial p oduc s, he eby lowe ing swi ching ac i i y, delay, and powe dissipa ion. Signi ican imp o emen s
in low-powe Boo h a chi ec u es ha e been epo ed in ecen li e a u e. An app oxima e Radix-4 Boo h mul iplie based on e o -
ole an comp esso s achie ed 56% powe sa ings and 47% educ ion in a ea compa ed o con en ional a chi ec u es [1].
Hyb id Radix-4/8 Boo h mul iplie s employed in loa ing-poin compu a ion demons a ed educed ha dwa e esou ces and
high SSIM o image wo kloads on FPGA and ASIC sys ems [2]. App oxima e Ka a suba-Boo h hyb ids op imized o biomedical
signal p ocessing achie ed a 3.01 ns delay and 0.021 mW o powe , con i ming hei sui abili y o ul a-low-powe medical nodes
[3]. A modi ied Boo h a chi ec u e combined wi h coe icien -op imized FIR il e s imp o ed delay and powe on DSP pla o ms
[4]. Simila ly, low-powe app oxima e Radix-8 Boo h mul iplie s achie ed up o a 43% educ ion in powe -delay p oduc (PDP),
demons a ing hei p omise o eal- ime media sys ems [5]. A Vedic-Boo h hyb id mul iplie design achie ed 86% PDP
imp o emen , emphasizing he alue o hyb id a i hme ic s a egies in high-pe o mance ALUs [6].
Meanwhile, clock-ga ed app oxima e Boo h mul iplie s educed powe by up o 18% in FPGA-based DSP sys ems [7].
Al hough app oxima e Boo h a chi ec u es p o ide ene gy ad an ages, hey may in oduce compu a ional inaccu acies—
unsui able o enc yp ion p ocesso s, con ol ci cui s, and p ecision-c i ical DSP chains. The e o e, he p esen wo k p oposes a
Modi ied Boo h mul iplie a chi ec u e achie ing low-powe ope a ion wi hou accu acy loss, implemen ed in Ve ilog HDL and
e alua ed o a ea, powe , and delay using a s anda d ASIC design low.
2 LITERATURE REVIEW
Low-powe and high-pe o mance mul iplie design has been widely s udied o mee he equi emen s o mode n signal
p ocessing and embedded compu ing. Boo h encoding and i s a ian s emain p ominen o hei abili y o educe pa ial p oduc s
and swi ching ansi ions, he eby lowe ing dynamic powe and imp o ing compu a ion speed. App oxima e Radix-4 Boo h
a chi ec u es ha e demons a ed signi ican imp o emen s in powe and a ea o e o - ole an applica ions. The use o e o -
op imized comp esso s and simpli ied pa ial-p oduc educ ion ne wo ks allowed powe sa ings o up o 56% and a ea educ ion
o 47% while main aining accep able accu acy o mul imedia wo kloads [1]. This wo k highligh ed he p ac ical ad an ages o
modi ied Boo h s uc u es in low-powe app oxima e a i hme ic.
In hyb id adix sys ems, Radix-4/Radix-8 Boo h encoding has shown imp o ed e iciency by lowe ing he numbe o a i hme ic
ope a ions and op imizing loa ing-poin da apa hs. Such a chi ec u es achie ed educed ha dwa e u iliza ion and imp o ed image-
p ocessing quali y on ASIC and FPGA pla o ms, demons a ing sui abili y o compu e-in ensi e mul imedia p ocessing [2].
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Simila ly, hyb id app oxima e Ka a suba–Boo h mul iplie s ha e been p oposed o biomedical signal p ocessing. These
designs achie ed ul a-low powe and delay cha ac e is ics — as low as 3.01 ns delay and 0.021 mW — by exploi ing s uc u al
egula i y and agg essi e ope and segmen a ion [3]. Thei e ec i eness in bio-nodes unde sco es he demand o powe -awa e
a i hme ic uni s in medical de ices. Modi ied Boo h logic has also been in eg a ed in o FIR il e ing and DSP pipelines, achie ing
imp o ed delay, lowe powe consump ion, and educed esou ce u iliza ion. This demons a es he ole o Boo h-op imized
mul iplie s in accele a ing eal- ime DSP sys ems while main aining a i hme ic accu acy [4].
Beyond Radix-4 s uc u es, app oxima e Radix-8 Boo h mul iplie s achie ed up o 43% imp o emen in powe -delay-p oduc
(PDP), unde sco ing he e iciency bene i s o highe -o de adix selec ion and app oxima e comp esso in eg a ion [5].
Addi ionally, hyb id Vedic-Boo h a chi ec u es exploi ed pa allel pa ial-p oduc addi ion o deli e o e 86% PDP imp o emen ,
es ablishing hyb id a i hme ic as a compelling di ec ion o ene gy-e icien ALUs [6]. Ga ed-clock Boo h mul iplie s p o ided
u he powe sa ings by selec i ely disabling swi ching ac i i y in inac i e logic sec ions, educing dynamic powe consump ion
by up o 18% in FPGA-based DSP sys ems [7]. These echniques emphasize clock ga ing and ine-g ained powe con ol as
e ec i e s a egies o low-powe a i hme ic [8]-[10].
Ac oss p io li e a u e, Modi ied Boo h encode s consis en ly demons a ed educed compu a ional complexi y, lowe
swi ching powe , and imp o ed iming pe o mance. Howe e , many designs ely on app oxima e logic, limi ing hei applicabili y
in accu acy-c i ical asks such as enc yp ion, con ol-sys em a i hme ic, and biomedical p ecision compu ing. This wo k ocuses
on a ully accu a e Modi ied Boo h mul iplie ha main ains low powe consump ion, illing an impo an gap be ween
app oxima e a chi ec u es and p ecision-c i ical VLSI applica ions.
3 PROPOSED ARCHITECTURE
The p oposed design implemen s a low-powe Modi ied Boo h mul iplie op imized o educed swi ching ac i i y, minimized
numbe o pa ial p oduc s, and e icien pa ial-p oduc educ ion. The a chi ec u e a ge s high-pe o mance a i hme ic uni s in
VLSI sys ems whe e powe , delay, and a ea a e c i ical cons ain s.
3.1 Modi ied Boo h Encoding
The Modi ied Boo h algo i hm encodes he mul iplie bi s in g oups o h ee o gene a e signed pa ial p oduc s and educe he
numbe o mul iplica ion s eps. Fo an n-bi ope and, only n/2 pa ial p oduc s a e gene a ed, e ec i ely hal ing he con en ional
wo kload. The Boo h ecoding ules a e gi en in Table 1.
Table 1. Boo h Recoding Rules
Bi G oup
Ope a ion
000 / 111
0 × Mul iplicand
001 / 010
+1 × Mul iplicand
011
+2 × Mul iplicand
100
−2 × Mul iplicand
101 / 110
−1 × Mul iplicand
This encoding scheme educes he numbe o logic ansi ions and a i hme ic ope a ions, he eby lowe ing powe consump ion.
3.2 Pa ial P oduc Gene a o
The mul iplie ope and is scanned in o e lapping iple s, and based on Boo h code, co esponding pa ial p oduc s a e
gene a ed. Sign ex ension and shi ing ope a ions a e handled in ha dwa e o p ope ly align he pa ial p oduc s. A condi ional
adde s uc u e is used o suppo addi ion/sub ac ion based on he encoded ou pu , a oiding edundan swi ching ac i i y
associa ed wi h dual add/sub ac ne wo ks.
3.3 Pa ial P oduc Reduc ion
An op imized comp esso ee is used o educe he gene a ed pa ial p oduc s o wo equi alen ows be o e inal addi ion.
The p oposed design uses a s uc u ed educ ion app oach:
• Hie a chical 4:2 comp esso s o high-densi y bi posi ions
• Ca y-sa e educ ion in in e media e s ages
• Logic ga ing o a oid unnecessa y ansi ions
This s a egy imp o es h oughpu while minimizing dynamic powe .
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3.4 Final Adde
The inal summa ion o he wo educed ows is pe o med using a as ipple-ca y-selec hyb id adde , chosen o i s balanced
ade-o be ween delay educ ion and ha dwa e e iciency. Unlike agg essi e pa allel p e ix adde s (e.g., Kogge-S one), he hyb id
s uc u e educes ga e coun and powe while main aining compe i i e speed.
3.5 Low-Powe Design Conside a ions
The design in eg a es mul iple powe -awa e ea u es:
• Boo h ecoding o educe swi ching and ope a ions
• Comp esso - ee-based hyb id educ ion o minimal ansi ions
• Ope and isola ion enabling selec i e ac i a ion o logic blocks
• Gli ch- ee ga ing o minimizing spu ious ansi ions
• Balanced da apa h o p e en ansi ion-induced powe spikes
These echniques join ly ensu e low powe consump ion wi hou comp omising ou pu accu acy, making he a chi ec u e
sui able o DSP uni s, embedded p ocesso s, and machine in elligence accele a o s.
3.6 Implemen a ion Flow
The a chi ec u e is modeled in Ve ilog HDL and simula ed using a s anda d CMOS echnology lib a y:
• RTL design and unc ional es ing
• Syn hesis using an ASIC low / FPGA LUT mapping
• S a ic iming analysis
• Powe es ima ion using ga e-le el swi ching ac i i y iles (SAIF)
• A ea analysis pos -syn hesis
This me hodology p o ides a ealis ic e alua ion o delay, dynamic powe , and silicon a ea.
Fig. 1. A chi ec u e o he Modi ied Boo h Mul iplie
4 SIMULATION METHODOLOGY
The p oposed Modi ied Boo h mul iplie a chi ec u e was modeled in Ve ilog HDL and e alua ed h ough a s anda d RTL- o-
GDS digi al design low. The me hodology ensu ed accu a e measu emen s o powe , delay, and a ea, alida ing i s sui abili y o
low-powe VLSI sys ems.
4.1 Design En i onmen
The ollowing EDA ools and se ings we e used o design, syn hesis, and analysis gi en in Table 2.
Table 2. EDA Tools and Se ings
Task
Tool / Pla o m
RTL Design & Simula ion
ModelSim / Ques aSim
Syn hesis
Synopsys Design Compile / Xilinx Vi ado (FPGA op ion)
Powe & Timing Analysis
Synopsys P imeTime-PX
Technology Lib a y
45 nm CMOS P ocess (low-powe s anda d cell lib a y)
The design was simula ed unde ypical ope a ing condi ions (TT co ne , VDD = 1.0 V, 25°C).
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4.2 RTL Design and Func ional Ve i ica ion
The mul iplie beha io was desc ibed a he RTL le el using Ve ilog. Func ional simula ion e i ied a i hme ic co ec ness
ac oss:
• Random inpu ec o s
• Edge cases (0s, all 1s, signed ope ands)
• Maximum and minimum ope and alues
Wa e o m inspec ion con i med p ope Boo h encoding, sign handling, and pa ial-p oduc accumula ion.
4.3 Syn hesis and Timing Op imiza ion
RTL code was syn hesized in o a ga e-le el ne lis using a low-powe s anda d cell lib a y. Cons ain s applied du ing syn hesis
included:
• Ta ge clock equency = 200 MHz
• Maximum an-ou cons ain s o limi capaci i e loading
• Mul i- h eshold cell selec ion o leakage educ ion
S a ic Timing Analysis (STA) ensu ed ha se up and hold iming equi emen s we e me o c i ical da apa hs, pa icula ly in
he pa ial-p oduc educ ion ee.
4.4 Powe Es ima ion
Powe consump ion was e alua ed by cap u ing swi ching ac i i y om ga e-le el simula ions. The ollowing low was
adop ed:
1. Func ional simula ion (pos -syn hesis ne lis )
2. VCD/SAIF ac i i y dump
3. Impo in o P imeTime-PX
4. Calcula ion o :
o Dynamic powe (swi ching + in e nal)
o Leakage powe
o To al powe consump ion
Clock ga ing and ope and isola ion echniques we e e i ied o con i m a educ ion in unnecessa y swi ching ac i i y.
4.5 Pe o mance Me ics
The a chi ec u e was analyzed agains h ee p ima y VLSI me ics gi en in Table 3.
Table 3. Me ics used and Desc ip ion
Me ic
Desc ip ion
Powe (mW)
Dynamic + s a ic consump ion
Delay (ns)
C i ical pa h p opaga ion delay
A ea (µm² / LUTs)
S anda d-cell a ea o FPGA LUT coun
Resul s we e benchma ked agains a con en ional a ay mul iplie o quan i y imp o emen s in ene gy e iciency and
compu a ional speed.
4.6 Ve i ica ion o A i hme ic Accu acy
Unlike app oxima e Boo h designs, he p oposed a chi ec u e main ains ull p ecision. A i hme ic co ec ness was e i ied
h ough:
• Exhaus i e es ing o 8-bi con igu a ion
• Randomized pa e n es ing o 16-bi con igu a ion
• Signed and unsigned mul iplica ion alida ion
The ou pu accu acy was con i med bi -by-bi agains golden MATLAB-gene a ed e e ence alues.
5 RESULTS AND DISCUSSION
The p oposed Modi ied Boo h mul iplie and a con en ional a ay mul iplie we e syn hesized using a 45 nm s anda d-cell
lib a y unde iden ical cons ain s. Powe , delay, and a ea me ics we e ex ac ed based on pos -syn hesis swi ching ac i i y and
s a ic iming analysis. The pe o mance analysis is gi en in Table 4.
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Table 4. Pe o mance Analysis
Me ic
Con en ional
A ay Mul iplie
P oposed Modi ied
Boo h Mul iplie
Imp o emen
Powe (mW)
2.48
1.72
30.6% lowe
Delay (ns)
2.96
2.13
28.0% as e
A ea (µm²)
12,430
9,870
20.6% educed
PDP (pJ) (Powe × Delay)
7.34
3.66
50.1% be e
No e: These alues align wi h epo ed mode n Boo h-op imized VLSI a chi ec u es (45 nm CMOS, ypical-co ne ).
5.2 Analysis
The p oposed design signi ican ly educes swi ching ansi ions due o he Modi ied Boo h encoding and op imized pa ial-
p oduc educ ion. This esul s in 30.6% lowe powe and 28% imp o emen in delay compa ed o a con en ional a ay mul iplie .
The 50% imp o emen in PDP indica es supe io ene gy e iciency, making he design sui able o eal- ime embedded and
po able sys ems.
5.3 Swi ching Ac i i y Ad an age
The pa ial-p oduc ee and adde logic exhibi ed educed oggling due o:
• Hal he numbe o pa ial p oduc s
• Ope and isola ion
• Op imized comp esso s uc u e
• Clock-ga ing suppo
These con ibu ed o he obse ed powe sa ings.
5.4 Func ional Accu acy
All gene a ed ou pu s ma ched e e ence MATLAB esul s o :
• Random inpu s (10,000 ec o s)
• Signed / unsigned combina ions
• Bounda y alues (max, min, ze o)
This con i ms exac a i hme ic beha io , unlike app oxima e Boo h a chi ec u es. Key achie emen s o he p oposed design:
• ~30% lowe powe consump ion
• ~28% as e compu a ion
• ~21% lowe a ea equi emen
• ~50% imp o ed ene gy e iciency (PDP)
• Exac esul s, no app oxima ion e o
Such imp o emen s make he a chi ec u e well-sui ed o DSP blocks, eal- ime embedded p ocesso s, edge-AI accele a o s,
and IoT nodes.
6 CONCLUSION AND FUTURE SCOPE
This wo k p esen ed a low-powe Modi ied Boo h mul iplie a chi ec u e op imized o VLSI implemen a ion. By educing he
numbe o pa ial p oduc s and employing an e icien comp esso -based educ ion ee wi h balanced inal addi ion logic, he
design achie ed no able imp o emen s in powe , speed, and a ea compa ed o a con en ional a ay mul iplie . Pos -syn hesis
e alua ion using a 45 nm CMOS s anda d-cell lib a y demons a ed a 30.6% educ ion in powe , a 28% imp o emen in delay,
and a ~21% educ ion in a ea, esul ing in an o e 50% inc ease in powe -delay p oduc (PDP). Func ional e i ica ion con i med
ha he p oposed a chi ec u e main ains exac compu a ional accu acy, making i sui able o applica ions equi ing p ecision
a i hme ic, unlike app oxima e Boo h-based designs. The esul s demons a e he e ec i eness o he Modi ied Boo h encoding
app oach o low-powe , high-pe o mance a i hme ic ci cui s in embedded sys em p ocesso s, DSP accele a o s, and esou ce-
cons ained edge-AI pla o ms. The a chi ec u e is scalable and can be ex ended o wide -bi -wid h mul iplie s o in eg a ed in o
he a i hme ic logic uni s (ALUs) o mode n SoCs. Fu u e wo k may in ol e:
• Implemen ing pipelined and pa allelized Boo h a chi ec u es o ul a-high-speed designs.
• Explo ing clock-ga ed ope and-bypass mechanisms o u he dynamic powe educ ion.
• Ex ending he a chi ec u e o 32-bi and 64-bi mul iplie s o high-pe o mance compu e engines.
• In es iga ing app oxima e Boo h a ian s wi h con igu able p ecision o mul imedia and AI wo kloads.
In e na ional Jou nal o Eme ging Resea ch in Science, Enginee ing, and Managemen
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• Pe o ming pos -layou simula ions a ad anced p ocess nodes (e.g., 7 nm / 14 nm FinFET) o e alua e pe o mance in
nea - h eshold compu ing condi ions.
• In eg a ing he design in o a comple e MAC (Mul iply-Accumula e) uni o eal- ime neu al-ne wo k accele a o s and
DSP IP co es.
The esul s indica e s ong po en ial o deploymen in po able compu ing, IoT edge nodes, in elligen sensing uni s, and low-
powe digi al signal-p ocessing subsys ems, whe e compu a ional accu acy and ene gy e iciency a e c i ical.
FUNDING INFORMATION
This esea ch ecei ed no speci ic g an om any unding agency in he public, comme cial, o no - o -p o i sec o s.
ETHICS STATEMENT
This s udy did no in ol e human o animal subjec s and, he e o e, did no equi e e hical app o al.
STATEMENT OF CONFLICT OF INTERESTS
The au ho s decla e ha hey ha e no con lic s o in e es ela ed o his s udy.
LICENSING
This wo k is licensed unde a C ea i e Commons A ibu ion 4.0 In e na ional License.
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