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TWIN-RELECT: Twinning o Excellence in Reliable
Elec onics
Ma ko Andjelko ic, Fabian Va gas, Milos K s ic, Luigi Dilillo, Alain Michez,
F ede ic W obel, Da ide Be ozzi, Mikel Lujan, Ch is os Geo gakidis,
Nikolaos Cha zi angelis, e al.
To ci e his e sion:
Ma ko Andjelko ic, Fabian Va gas, Milos K s ic, Luigi Dilillo, Alain Michez, e al.. TWIN-RELECT:
Twinning o Excellence in Reliable Elec onics. Design, Au oma ion and Tes in Eu ope Con e ence,
Ma 2025, Lyon, F ance. �hal-04919286�
1
This is a sel -a chi ed e sion o an o iginal a icle.
This ep in may di e om he o iginal in pagina ion and ypog aphic de ail.
Ti le: TWIN-RELECT: Twinning o Excellence in Reliable Elec onics
Au ho (s): M. Andjelko ic, F. Va gas, M. K s ic, L. Dilillo, A. Michez, F. W obel, D. Be ozzi, M. Lujan, C.
Geo gakidis, N. Cha zi angelis, K. Tsilingi i, N. Zaza is, G. I. Palia ou is, P. Tsoumanis, C. So i iou
Documen e sion: P e-p in e sion (Final d a )
Please ci e he o iginal e sion:
M. Andjelko ic, F. Va gas, M. K s ic, L. Dilillo, A. Michez, F. W obel, D. Be ozzi, M. Lujan, C. Geo gakidis, N.
Cha zi angelis, K. Tsilingi i, N. Zaza is, G. I. Palia ou is, P. Tsoumanis, C. So i iou, ”TWIN-RELECT: Twinning o
Excellence in Reliable Elec onics, ”2025 Design, Au oma ion & Tes in Eu ope Con e ence & Exhibi ion (DATE),
2024.
This ma e ial is p o ec ed by copy igh and o he in ellec ual p ope y igh s, and duplica ion o sale o all o pa o
any o he eposi o y collec ions is no pe mi ed, excep ha ma e ial may be duplica ed by you o you esea ch use
o educa ional pu poses in elec onic o p in o m. You mus ob ain pe mission o any o he use. Elec onic o p in
copies may no be o e ed, whe he o sale o o he wise o anyone who is no an au ho ized use .
TWIN-RELECT: Twinning o Excellence in
Reliable Elec onics
Ma ko Andjelko ic1), Fabian Va gas1), Milos K s ic1,7), Luigi Dilillo2-4), Alain Michez2-4), F ede ic W obel2-4), Da ide Be ozzi5), Mikel Lujan5),
Ch is os Geo gakidis6), Nikolaos Cha zi angelis6), Ka e ina Tsilingi i6), Nikolaos Zaza is6), Geo gios Ioanis Palia ou is6),
Pelopidas Tsoumanis6), Ch is os So i iou6)
1) IHP - Leibniz-Ins i u ü inno a i e Mik oelek onik, F ank u (Ode ), Ge many
2) CNRS - Cen e Na ional de la Reche che Scien i ique, Mon pellie , F ance
3) Ins i u d’Élec onique e des Sys èmes (IES), Mon pellie , F ance
4) Uni e si y o Mon pellie , Mon pellie , F ance
5) Uni e si y o Manches e , Manches e , Uni ed Kingdom
6) Uni e si y o Thessaly, Volos, G eece
7) Uni e si y o Po sdam, Po sdam, Ge many
{andjelko ic, a gas, k s ic}@ihp-mic oelec onics.com
{luigi.dilillo, alain.michez, ede ic.w obel}@ umon pellie .
{da ide.be ozzi, mikel.lujan}@manches e .ac.uk
{cgeo gakidis, saika e ini, chnikolaos, znikolaos-g, gepalia , pe souma, chso i iou}@u h.g
Abs ac —Reliable elec onics plays a majo ole in shaping ou daily li es, being a key enable o c i ical applica ions,
such as space missions, a ionics, au omo i e, medicine, banking, au o-ma ed indus y, wi eless communica ion ne wo ks,
e c. Howe e , design o highly eliable elec onic sys ems emains a challenge wi h he ad ances in semiconduc o
echnology and inc ease in in eg a ed ci cui (IC) complexi y. In his wo k, we in oduce he Ho izon Eu ope Twinning
p ojec TWIN-RELECT, aimed a s eng hening he scien i ic expe ise in designing eliable in eg a ed ci cui s. The pape
p esen s he gene al p ojec concep and objec i es, and main di ec ions o he join esea ch ac i i ies. The p ima y
scien i ic goal is o con ibu e o he de elopmen o no el, mo e e icien , Eu opean Elec onic Design Au oma ion (EDA)
ool-chain o design o eliable chips.
Keywo ds—Reliable in eg a ed ci cui s, EDA ools, ansien aul s, pe manen aul s
I. INTRODUCTION
High- eliabili y elec onic sys ems a e essen ial in sa e y- and mission-c i ical applica ions, whe e any mal unc ion
o ailu e may cause ca as ophic consequences, such as loss o li es o un eco e able damage. These sys ems mus
mee s ingen pe o mance and du abili y s anda ds o ensu e con inuous, aul - ee ope a ion unde all exploi a ion
condi ions. Typical applica ions o eliable elec onics a e in c i ical sec o s like space, a ionics, au omo i e sys ems,
and banking. Reliable elec onic sys ems a e also used in adiology and adio he apy, whe e p ecision and
dependabili y di ec ly impac pa ien s’ hea h. Fu he mo e, eliable elec onics is employed in high-ene gy physics
esea ch expe imen s, nuclea powe plan s, wi eless communica ion ne wo ks, and au oma ed indus ial
en i onmen s, whe e any ailu e could dis up ope a ions o lead o cos ly down imes.
Mode n semiconduc o echnologies enable o de elop highly complex in eg a ed ci cui s (ICs) ha combine digi al
and analog esou ces wi h di e se unc ionali ies. Howe e , eliabili y challenges o ICs inc ease wi h e e y new
echnology gene a ion. Many applica ions equi e eliable ope a ion du ing a pe iod o 15-30 yea s, and in some cases
(e.g., space missions and deep-sea explo a ion) main enance is di icul o impossible. Technological ad ancemen s
impose he need o no el design solu ions o eliable ICs. In addi ion, he e is an inc easing need o e icien Elec onic
Design Au oma ion (EDA) o Compu e -Aided Design (CAD) ools and me hodologies o eliable elec onic sys ems.
Acco ding o he Eu opean Chips Ac [1], Eu ope’s independence and so e eign y in ad anced semiconduc o
echnologies is he key d i e o he economic de elopmen o Eu ope in he o hcoming decades. In ha ega d, he e
is a need o ad anced design echnologies o add ess he challenges o modelling and simula ion o eliabili y,
deg ada ion e ec s and p ocess a iabili y. Achie ing he highes possible eliabili y and a long li e ime o au onomous
sys ems will be key o economic success, keeping a balance be ween cos and pe o mance. To mee he needs o
eme ging applica ions, u u e connec i i y sys ems need o o e ex emely high capaci y, ex eme co e age, ex emely
low la ency and high eliabili y, all a low ene gy and low cos . To achie e hese goals, i is impo an o inc ease
Eu opean compe ences in he design o eliable elec onic sys ems.
The global ma ke o eliable elec onics exhibi s a s eady g ow h o e he pas yea s, and a simila end is p ojec ed
o he ollowing decade. Acco ding o T anspa ency Ma ke Resea ch [2], he high- eliabili y semiconduc o ma ke
was alued o USD 6.4 billion in 2021, wi h he p ojec ed ise o USD 10.1 billion by he end o 2031. A signi ican pa
o he eliabili y ma ke is sha ed by adia ion ha dened elec onics. The global adia ion ha dened elec onics ma ke
was alued a USD 1.5 billion in 2022, and is p ojec ed o each USD 2.1 billion by 2031. Rise in he usage o sa elli es
in elecommunica ions, b oadcas ing, and da a communica ions is an icipa ed o inc ease he adia ion ha dened ma ke
size in he nex ew yea s. An impo an pa o eliabili y elec onics ma ke a e he EDA ools. The op EDA companies
spend mo e han USD 1 billion annually on R&D cos . A he momen , US companies con ol o e 70% o he global
EDA ools ma ke . This p esen s an oppo uni y o join o ces wi hin he Eu opean EDA communi y and collabo a e on
suppo ing Eu opean g ow h in a sec o whe e Eu ope has e y weak p esence.
In his wo k, we in oduce he concep o a no el ool-chain o design o eliable ICs. The p oposed concep is
explo ed in he EU- unded mul i-pa ne p ojec TWIN-RELECT. The es o he pape is o ganized as ollows. Sec ion
II in oduces he scien i ic backg ound and majo limi a ions o he s a e-o - he-a solu ions o design o eliable ICs.
Sec ion III p esen s he TWIN-RELECT p ojec . The esea ch pa o he p ojec is elabo a ed in Sec ion IV.
II. SCIENTIFIC BACKGROUND: DESIGN METHODOLOGIES AND TOOLS FOR RELIABLE INTEGRATED CIRCUITS
Wi h he scaling o CMOS echnologies, ICs a e becoming inc easingly suscep ible o ansien and pe manen
aul s, and ha end is no e iden only o ICs used in sa e y- and mission-c i ical applica ions, bu also o hose
employed in mains eam elec onics. Fo example, “In 2020, AMD public-shed a epo wi h e idence ha , a ha ime,
he mos ad anced chips we e abou 5.5 imes less eliable han he p e ious gene a ion o a simila p oduc ” [3].
Simila ly, “In 2021, esea che s a bo h Facebook and Google published s udies desc ibing compu e ha dwa e ailu es
whose causes ha e no been easy o iden i y. The p oblem, hey a gued, was no in he so wa e - i was somewhe e
in he compu e ha dwa e made by a ious companies” [3].
One o he mos c i ical eliabili y h ea s o mode n ICs a e so e o s, also known as Single E en Upse s (SEUs).
So e o s ep esen bi - lips in s o age elemen s ( egis e s and memo ies). They may be caused when high-ene gy
pa icles (hea y ions, p o ons, neu ons) s ike di ec ly s o age elemen s, o when hese pa icles hi a combina ional
ci cui and cause ol age gli ches, known as Single E en T ansien s (SETs), which may hen p opaga e h ough he
ci cui and be cap u ed by s o age elemen s. So e o s may be also caused by Elec omagne ic In e e ence (EMI)
and c oss alk. In space applica ions, o e 80% o all adia ion-induced e o s in elec onic sys ems ha e been ela ed
o so e o s [4]. On he o he hand, pe manen deg ada ion o ci cui ’s pe o mance occu s due o g adual ansis o
aging, caused by Ho Ca ie Injec ion (HCI) and Bias and Tempe a u e Ins abili y (BTI) e ec s, o by he adia ion-
induced To al Ionizing Dose (TID) e ec . Due o ansis o scaling and inc ease in elec ical ield s eng h, aging due o
HCI and BTI e ec s has become a se ious eliabili y conce n in sub-45 nm echnologies [5]. O he sou ces o pe manen
aul s include manu ac u ing de ec s and elec omig a ion. In a eal applica ion, an elec onic sys em may be subjec ed
o a simul aneous impac o mul iple aul sou ces [6], and he sys em’s esponse o aul s depends on a wide ange o
design, echnology, and ope a ing pa ame e s.
Complex ICs may inco po a e a wide a ie y o unc ional uni s, such as gene al-pu pose p ocesso s, digi al signal
p ocesso s, memo y blocks, a i icial in elligence (AI) accele a o s, communica ion modules, pe iphe al uni s, e c. Such
complex ICs a e known as Sys ems-on-Chip (SoCs). A ypical concep ual design o a SoC is illus a ed in Figu e 1. The
aul e ec s in SoCs may di e signi ican ly depending on he unc ional uni whe e hey occu . The e o e, design o
eliable SoCs equi es a comp ehensi e me hodology o assessmen o aul mechanisms and e ec s ac oss mul iple
le els o abs ac ion, i.e. om he de ice le el up o he sys em le el, conside ing di e en ha dwa e a chi ec u es.
Reliabili y should be conside ed om he beginning o IC design p ocess. Analysis o eliabili y e ec s du ing he
design phase is pe o med wi h compu e -aided simula ion lows. Simula ion-based analysis may be conduc ed a all
le els o abs ac ion, p o ided accu a e models o eliabili y e ec s a e a ailable. Se e al comme cial so wa e ools o
simula ion o eliabili y e ec s exis . In addi ion, a lo o esea ch wo k on modeling and cha ac e iza ion o eliabili y
e ec s has been done, and nume ous solu ions ha e been published. Howe e , bo h comme cial and esea ch
solu ions ha e limi a ions.
Figu e 1: Gene al a chi ec u e o an in elligen SoC
The c oss-laye me hodologies o analysis o combined impac o mul iple aul e ec s a e sca ce. As aul injec ion
simula ions a e e y ime-consuming o complex designs, a ious analy ical me hods and models ha e been p oposed
o simpli y and speed up he analysis p ocess [7-13]. Howe e , he epo ed eliabili y analysis lows ha e se e al c i ical
limi a ions. Fi s , mos published app oaches do no add ess he combined impac o mul iple aul ypes. Second, he e
is no solu ion o design o la ge-scale eliable p ac ical ci cui s, i.e. wi h sizes anging be ween 500k ansis o s o many
millions o ansis o s. In addi ion, exis ing solu ions lack he suppo o bo h ga e and in e connec delays in he
a o emen ioned analysis. I is well-known ha he impac o in e connec ion becomes mo e c i ical wi h echnology
scaling. Semi-cus om EDA lows, comme cial o open-sou ce, use a ious modelling echniques o conside
in e connec delays, bu no om a aul p opaga ion pe spec i e. Las , bu no leas , he ou h key issue which is
lacking in he s a e o he a , is combining he las wo inno a ions, i.e. implemen ing a semi-cus om, s anda d-cell and
in e connec awa e ool low and me hodology, which inco po a es he capabili y o imp o e ci cui aul ole ance, by
pe o ming bo h s uc u al and physical changes, and assessing he measu e o imp o emen s. In he pas yea s, he
use o a i icial in elligence (AI)-based me hods o ci cui eliabili y analysis has been in es iga ed ex ensi ely. I has
been demons a ed ha AI models ained on da ase s ob ained om simula ions can p o ide as and e y accu a e
p edic ions o aging and so e o e ec s in indi idual de ices as well as in complex ci cui s [14 - 19]. While he AI-
based eliabili y analysis me hods ha e shown e y p omising esul s, hey ha e no p o ided solu ions o he
a o emen ioned limi a ions o he s a e-o - he-a app oaches. Fu he mo e, he use o AI models equi es e y la ge
da ase s o aining, which imposes he need o conduc exhaus i e aul injec ion simula ions on a la ge se o es
designs.
Al hough se e al comme cial ools o eliabili y assessmen exis , hei unc ionali y is limi ed. The Incisi e
Func ional Sa e y Simula o (IFSS) o Cadence Inc. [20] suppo s ansien and pe manen aul analysis, bu does no
conside eal physical mechanisms and canno ake in o accoun key pa ame e s such as supply ol age o
empe a u e. The SoCFIT ool o IROC Inc. [21] does p o ide de ailed analysis including physical e ec s, bu i is
applicable only o adia ion-induced so e o s. The e exis s cu en ly no comme cial ool o epo ed esea ch esul
which suppo s bo h eliabili y analysis and design o eliabili y. In addi ion, he e is a lack o EDA ools o analysis o
he eliabili y o AI-based sys ems, which ha e gained inc eased popula i y in he las yea s.
III. TWIN-RELECT PROJECT: GENERAL CONCEPT
TWIN-RELECT is he Ho izon Eu ope Twinning p ojec , unning om Oc obe 2024 o Augus 2027. The main goal
o Twinning p ojec s is o inc ease he scien i ic and inno a ion capaci ies o a Widening pa ne (a esea ch ins i u ion
om a de eloping Eu opean coun y) h ough collabo a ion wi h a leas wo ad anced pa ne s, whe e he Widening
pa ne se es as he p ojec coo dina o . The TWIN-RELECT p ojec coo dina o is he Uni e si y o Thessaly om
G eece, and he ad anced pa ne s a e IHP om Ge many, CNRS om F ance, Uni e si y o Mon pellie om F ance
(a ilia ed o CNRS), and Uni e si y o Manches e om he UK.
The main opic o he p ojec is Design o Reliable Elec onic Sys ems. The p ojec me hodology combines he know-
ledge and bes p ac ices o he ad anced pa ne s IHP, CNRS, Uni e si y o Mon pellie and Uni e si y o Manches e
o enhance he scien i ic and esea ch managemen capaci ies o he Uni e si y o Thessaly. To his end, he o e all
me hodology is based on i e pilla s: (i) a join explo a o y esea ch p ojec , (ii) enhancemen o scien i ic capaci y, (iii)
enhancemen o esea ch managemen and adminis a ion capaci y, (i ) enhancemen o ne wo king capaci y, and ( )
es ablishmen o a amewo k o sus ainable and long- e m collabo a ion. Each pilla consis s o a se o ac ions ha
will be implemen ed in he o m o a dedica ed wo k package. The wo k plan is o ganized in o se en wo k packages
(WPs), as illus a ed in Figu e 2. Fi e WPs (WP1 - WP5) add ess he i e pilla s o he p oposed me hodology. WP6
deals wi h dissemina ion, exploi a ion and communica ion, while WP7 is ela ed o p ojec managemen .
Figu e 2: Rela ion be ween TWIN-RELECT WPs
The scien i ic s a egy will add ess he limi a ions o he s a e-o - he-a p esen ed in Sec ion II h ough h ee opics
ele an o he design o eliable ICs: (i) eliabili y analysis and modeling, (ii) design echniques o eliable sys ems,
and (iii) eliabili y es ing and quali ica ion. The scien i ic s a egy is illus a ed in Figu e 3. In each opic we will add ess
all ele an aspec s om echnology le el up o sys em le el. Ad anced pa ne s will con ibu e o all h ee main opics
by p o iding complemen a y know-how. The expe ise o ad anced pa ne s will signi ican ly widen he compe ences
o he Uni e si y o Thessaly in mul iple aspec s ela ed o eliable elec onics, hus es ablishing he ounda ion o
ans o ming he Uni e si y o Thessaly in o a Cen e o Excellence o Reliable Elec onic Sys ems.
IV. JOINT RESEARCH: TOWARDS A COMPREHENSIVE TOOL-FLOW FOR DESIGN OF RELIABLE INTEGRATED CIRCUITS
Gi en he limi a ions o he cu en s a e-o - he-a , ma ke s a us and Eu opean s a egic policies ou lined in he
p e ious sec ions, he e is an u gen need o accu a e eliabili y models and EDA ools capable o ime-e icien
analysis and complex eliable elec onic sys ems design. In ha ega d, a signi ican goal o he TWIN-RELECT p ojec
is o pe o m join esea ch owa ds a new c oss-laye low o e icien analysis and design o eliable in eg a ed ci cui s.
The join esea ch aims o exploi he s ong expe ise o he Uni e si y o Thessaly in he ield o EDA algo i hms, ools
and me hodologies, and he p o en expe ise o ad anced pa ne s in design o eliable elec onic sys ems.
Figu e 4 illus a es he concep o he p oposed ool- low o he simula ion o eliabili y e ec s in in eg a ed ci cui s
and he design o eliable in eg a ed ci cui s. The p oposed ool- low is based on an EDA iming engine ope a ing on
he p inciples o S a ic Timing Analysis (STA), de eloped by he Uni e si y o Thessaly. Recen join publica ion o
Uni e si y o Thessaly and IHP has demons a ed he un ime bene i s o STA-based SET analysis [22]. In addi ion, he
Uni e si y o Thessaly has al eady de eloped se e al echnologies o suppo he design o eliable ci cui s and sys ems
by applying placemen -awa e algo i hms. Howe e , he cu en STA-based analysis app oach explo ed a he Uni e si y
o Thessaly lacks suppo o ealis ic physical models o ansien and pe manen aul s. In addi ion, i cu en ly does
no suppo he i e a i e ci cui eliabili y op imiza ion. Thus, in his esea ch p ojec , he Uni e si y o Thessaly will
collabo a e wi h ad anced pa ne s o enhance he capabili ies o he STA-based low. Ad anced pa ne s will assis in
modelling o aul e ec s and cha ac e iza ion o aul ole ance echniques, as well as in de ini ion o eliabili y e alua ion
me ics, all o which will se e as key inpu s o he STA-based ool low.
The esea ch p ojec will be suppo ed by he pa ne s’ ongoing p ojec s ela ed o he p oposed esea ch opic. Ou
esea ch me hodology will be based on he combina ion o c oss-laye simula ion o aul e ec s, om de ice up o
sys em le el, and expe imen al analysis wi h adia ion es s. The me hodology is aimed a s udying a wide ange o
echnologies, bo h hose abo e 100 nm, which a e s ill e y ele an o some applica ions like space o au omo i e, as
well as ad anced scaled echnologies. The esea ch will be composed o six main asks whose ou comes will cons i u e
he basis o he ool- low illus a ed in Figu e 4:
a) De ini ion o speci ica ions o he ool, and selec ion o es designs and echnologies,
b) Cha ac e iza ion o aul mechanisms in de ices, ci cui s and sys ems, and de ini ion o aul models o di e en
p ocesses and di e en ypes o logic s uc u es,
c) Analysis o aul - ole ance echniques and de ini ion o me ics o e alua ion o he aul ole ance,
d) Es ablishmen o STA-based simula ion engine o join analysis o ansien and pe manen aul s,
e) Es ablishmen o STA-based op imiza ion engine o eliabili y imp o emen h ough i e a i e applica ion o aul
ole ance echniques,
) In eg a ion o all echniques in o a single ool- low and es ing o he ool wi h selec ed benchma k ci cui s.
Figu e 3: TWIN-RELECT scien i ic concep
Figu e 4: TWIN-RELECT ool- low o design o eliable in eg a ed ci cui s
A. De ini ion o Tool Speci ica ions and Selec ion o Tes Designs and Technologies
As a i s s ep, gene al speci ica ions o he ool- low and a se o benchma k ci cui s o ool alida ion will be
de ined. The speci ica ions will include he de ini ion o inpu and ou pu da a o he EDA ool and he o ma o his
da a. In gene al, inpu pa ame e s will include (i) a ci cui speci ica ion in de ice, ansis o , ne lis (VHDL/Ve ilog) le el,
o e en Ve ilog RTL le el, (ii) ci cui ope a ing condi ions (inpu logic ec o s o s a e p obabili y, supply ol age,
empe a u e, e c.), and (iii) a se o aul models and eliabili y scena ios ex ac ed om simula ions and eliabili y
expe imen s. The ool- low ou pu s will include: (i) assessmen o he obus ness o he es ci cui , (ii) iden i ica ion o
he mos sensi i e logic elemen s in he es ci cui , (iii) adia ion-ha dened a ian o he es ci cui ob ained by
modi ying he ci cui wi h app op ia e ha dwa e edundancy echniques. Analysis me ics will be ob ained conside ing
di e en adia ion scena ios.
Fo es ing he ool- low, a se o benchma k ci cui s o a ious complexi ies will be selec ed. We aim o use he
ci cui s om eal designs. The ollowing ypes o es ci cui s will be conside ed: (i) AI-based ha dwa e uni s, such as
deep lea ning accele a o s and spiking neu al ne wo k accele a o s, (ii) p ocessing a chi ec u es, e.g. based on RISC-
V, including mul i-co e p ocessing pla o ms, (iii) cus om mic ocon olle o space applica ions, (i ) wi eless
communica ion modules such as baseband p ocesso s.
The es designs will be implemen ed in a ious echnologies, wi h he aim o assess also he impac echnology on
he o e all aul - ole ance. In ha ega d, as baseline echnologies we will use IHP’s 130 and 250 nm echnologies,
whe eby he P ocess Design Ki (PDK) o 130 nm echnology is a ailable as open sou ce PDK [23]. In addi ion, we will
analyze scaled echnologies below 30 nm.
B. Cha ac e iza ion and Modeling o Faul E ec s Ac oss Mul iple Abs ac ion Laye s
A majo p e equisi e o accu a e aul ole ance analysis is o ha e accu a e aul models. To his end, we aim o
de elop accu a e aul models conside ing di e en echnology nodes. This ask will be di ided in o h ee sub- asks.
Cha ac e iza ion and modeling o aul e ec s h ough de ice (TCAD) simula ions
Since all aul s o igina e om a single de ice ( ansis o ), i is impo an , as a i s s ep, o analyze he aul e ec s
on de ice le el. The cha ac e iza ion will co e SEUs, SETs and TID e ec s. Fo his pu pose, we will ely on i adia ion
es s and cus om de ice-le el simula ions wi h ECORCE [24]. ECORCE is a TCAD-like simula ion ool de eloped by
CNRS and he Uni e si y o Mon pellie .
The cha ac e iza ion will s a wi h assessmen o de ice sensi i i y h ough simula ions. The simula ions will be
done o indi idual ansis o s in a pa icula echnology, as well as o s anda d logic cells. TCAD models o ansis o s
and logic cells will be de eloped. A e wa ds, i adia ion es campaigns will be conduc ed. The expe imen al esul s will
be used o imp o e he p edic ion and simula ion ools wi h ac ual da a in e ms o sensi i i y and aul mechanisms.
The ou pu s o his ask will be essen ial inpu s o he ga e- and cell-le el analysis, including he in o ma ion such as
ansien cu en , deposi ed and collec ed cha ge, c i ical cha ge, e c.
Cha ac e iza ion and modeling o aul e ec s h ough elec ical simula ions
The so e o and aging e ec s in s anda d cells will be s udied using comme cial SPICE simula o and P edicSEE
ool [25] de eloped by CNRS and he Uni e si y o Mon pellie . P edicSEE is a Mon e Ca lo simula ion ool o
calcula ing he c oss-sec ion o s anda d logic cells and small ci cui s, o a ious echnologies and adia ion ypes.
SPICE simula ions will be used o de e mine he sensi i i y o each ga e in e ms o c i ical cha ge ( o SET and SEU),
SET pulse wid h, and delay a ia ion due o aging. As inpu s o SPICE simula ions, he TCAD simula ion esul s
ob ained in p e ious ask will be used. Ex ensi e SPICE simula ions will be conduc ed o assess he sensi i i y o each
ga e unde so e o and aging e ec s, as well as he combined impac o so e o s and aging, conside ing he impac
o design and ope a ing pa ame e s ( ansis o size, empe a u e, supply ol age, e c.).
Cha ac e iza ion and modeling o aul e ec s in applica ion-speci ic and cus om-designed cells
Complex digi al ICs may no be composed only o s anda d cells, bu may also consis o some special-pu pose o
cus om-designed cells. Fo example, such cells may be equi ed o special-pu pose ha dwa e modules such as AI
accele a o s a ge ing he accele a ed in e ence o bo h a i icial and spiking neu al ne wo ks. In ha ega d, we will
assess he obus ness o asynch onous a bi e s o clockless ne wo ks-on-chip by means o no el me hodologies and
ool lows capable o consis en SET/SEU gene a ion and p opaga ion a di e en abs ac ion laye s, especially
elec ical and ga e-le el simula ions, so ha he scope o he analysis can be ex ended om he indi idual a bi e
componen s o he e ec s a a chi ec u al building blocks which include hem.
C. Cha ac e iza ion o Faul -Tole ance Techniques and De i-ni ion o E alua ion Me ics
In his ask, s anda d aul ole ance mechanisms will be cha ac e ized in e ms o hei sensi i i y o aul s and hei
impac on aul sensi i i y educ ion when applied o a gi en ci cui . In addi ion, app op ia e me ics o assessing he
aul ole ance o a ci cui will be de ined.
Cha ac e iza ion o aul ole ance echniques
Va ious SET, SEU and aging mi iga ion echniques, bo h a ga e and ci cui le els, will be s udied h ough elec ical
and logic simula ions. P e ious s udies ha e shown ha he e is no a single echnique ha can p o ide op imal aul
ole ance, bu he solu ion is in he combina ion o mul iple echniques. Faul mi iga ion echniques may di e
signi ican ly in e ms o hei impac on ci cui aul ole ance and o e all a ea, delay and powe o e head. The e o e,
he cha ac e iza ion o indi idual mi iga ion echniques would ease he selec ion o an op imal aul ole ance scheme
o a gi en design.
De ini ion o eliabili y me ics
To iden i y he mos aul -sensi i e elemen s (ga es o sub-ci cui s) o a gi en design, i is necessa y o use
app op ia e e alua ion me ics. A wide ange o me ics al eady exis , such as so e o a e, c oss-sec ion, ailu es in
ime (FIT), mean ime o ailu e (MTTF), e c. Howe e , hese me ics do no conside he speci ici y o di e en designs
and aul ypes, and hey do no ake in o conside a ion aul - ole ance echniques. We aim o in es iga e h ee classes
o me ics: (i) me ics which de ine he aul sensi i i y o each ga e in a ci cui , (ii) me ics which de ine he sensi i i y
o he whole design, and (iii) cos me ics which e alua e he e ec o aul ole ance echniques ( a io be ween
imp o emen in aul ole ance and o e heads in e ms o a ea, delay and powe ).
D. STA-based Faul Tole ance Analysis
The analysis o he aul ole ance o a a ge ci cui will be composed o wo phases: (i) analysis o aul gene a ion
e ec s wi hin indi idual cells in he ci cui , and (ii) analysis o aul p opaga ion h ough he ci cui .
Fo he analysis o aul gene a ion, h ee app oaches will be conside ed: (i) s o age o simula ion da a in look-up
ables, (ii) de i a ion o analy ical models om simula ion da a, and (iii) use o simula ion da a o ain AI-based models
o aul gene a ion p edic ion. We will assess he bene i s and limi a ions o each app oach.
Fo he analysis o aul p opaga ion, he exis ing STA simula ion engine om he Uni e si y o Thessaly will be
ex ended in o de o enable he simula ion o bo h ansien (SET and SEU) aul s and pe manen (aging) aul s. STA is
an indus y-adop ed al e na i e o SPICE simula ion, allowing o a as eliabili y analysis wi h accep able loss o
accu acy. The exis ing ool is capable o suppo ing Ve y La ge-Scale In eg a ion (VLSI) ci cui s, and i ollows EDA
indus y s anda ds, suppo ing ile o ma s like Lib a y Exchange Fo ma (LEF), Libe y Fo ma (LIB), Ga e-le el Ne lis ,
Design Exchange Fo ma (DEF) and mo e. The algo i hms o bo h p obabilis ic ec o less and a a ge ed ec o -based
aul sensi i i y analysis will be de eloped. The i s s ep will be o ex end he ool o SET analysis, by conside ing bo h
he SET gene a ion phase and he SET p opaga ion phase. A e wa ds, he ool will be upda ed o suppo he analysis
o SEU and aging a ec s. Fo SET and SEU analysis, ealis ic adia ion p o iles will be employed.
E. STA-based Design Op imiza ion
Based on he pe o med aul analysis wi h he STA simula ion engine, he design may be op imized o inc ease i s
obus ness o ansien and pe manen aul s, while conside ing he ci cui pe o mance, powe and a ea cons ain s.
The STA-based op imiza ion algo i hm will be applied o modi y he design ne lis by inse ing app op ia e aul ole ance
mechanisms. Based on he analysis o di e en aul ole ance echniques, a se o he mos sui able echniques will be
in eg a ed in o he SET op imiza ion low. The op imiza ion algo i hm will inse he aul ole ance solu ions in he design
and compu e he change in ci cui ’s sensi i i y o aul s. I he equi ed aul ole ance is no achie ed, he op imiza ion
will be pe o med un il he equi ed h eshold is eached.
F. Flow In eg a ion and Valida ion
The inal phase will be o in eg a e he de eloped models and analysis lows in o a comp ehensi e EDA ool chain
o eliable elec onics design, and o es he low on selec ed benchma k ci cui s. Fo in eg a ing all solu ions, we will
de elop cus om sc ip s, which will allow au oma ing he en i e analysis and op imiza ion p ocess. All benchma k designs
will be e alua ed based on de ined me ics. The pe o mance will be assessed in e ms o he analysis un ime, and he
esul o analysis will be compa ed wi h expe imen al esul s ob ained om o he p ojec s whe e he a ge ci cui s ha e
been used. We will also compa e he un ime o he de eloped EDA ool wi h he comme cial IFSS ool.
V. CONCLUSION
In his pape , he EU- unded Ho izon Eu ope Twinning p ojec TWIN-RELECT is p esen ed. The key aim o TWIN-
RELECT is o ad ance he scien i ic know-how in ela ion o design o eliable in eg a ed ci cui s, and pa icula ly he
EDA ools o design o eliable in eg a ed ci cui s. The pape in oduces main scien i ic opics be explo ed in he p ojec ,
and p esen s he gene al concep o he join esea ch.
Besides enhancing he know-how o he coo dina ing ins i u ion and ad anced pa ne s, he p ojec also aims o
enhance he o e all capaci y o EU in chip design, based on he s a egy se ou in he Eu opean Chips Ac . To his
end, a e sion o de eloped ool wi h limi ed unc ionali ies may be eleased o ee use o academic pu poses.
ACKNOWLEDGEMENT
This wo k has been done in he amewo k o EU- unded Ho izon Eu ope Twinning p ojec TWIN-RELECT, unde
he G an Ag eemen No. 101160314.
REFERENCES
[1] Eu opean Chips Ac . A ailable a : h ps://commission.eu opa.eu/s a egy-and-policy/p io i ies-2019-2024/eu ope- i -digi al-age/eu opean-
chips-ac _en
[2] High Reliabili y Semiconduc o Ma ke . A ailable a : h ps://www. anspa encyma ke esea ch.com/high- eliabili y-semiconduc o s-ma ke .h ml
[3] Reliabili y Risk A ise as Chip Technology Ad ances. A ailable a : h ps://epsnews.com/2023/10/25/ eliabili y- isks-a ise-as-chip- echnology-
ad ances/
[4] R. Eco e , “O e iew o In-O bi Radia ion Induced Spacec a Anomalies,” IEEE T ansac ions on Nuclea Science, ol. 60, 2013.
[5] H. Am ouch, V. M. an San en, T. Ebi, V. Wenzel, J. Henkel, “Towa ds In e dependencies o Aging Mechanisms,” in P oc. In . Con e ence on
Compu e -Aided Design (ICCAD), 2014.
[6] P. Goe l e al., “Combined Ionizing Radia ion and Elec omagne ic In e e ence Tes P ocedu e o Achie e Reliable In eg a ed Ci cui s,”
Mic oelec onics Reliabili y, ol. 100-101, 2019.
[7] A. K i ikakou e al., “Flodam: C oss-Laye Reliabili y Analysis Flow o Complex Ha dwa e Designs,” in P oc. Design, Au oma ion and Tes in
Eu ope Con e ence (DATE), 2022.
[8] R. Wang e al., “C oss-Laye Design o Reliabili y in Ad anced Technology Nodes: An EDA Pe spec i e,” in P oc. In . Con e ence on Solid-
S a e and In eg a ed Ci cui Technology (ICSICT), 2022.
[9] D. Alexand escu e al., “Enabling C oss-Laye Reliabili y and Func ional Sa e y Assessmen h ough ML-Based Compac Models,” in P oc. In .
Symposium on Online Tes ing and Robus Sys em Design (IOLTS), 2020.
[10] A. Vale o e al., “C oss-Laye Reliabili y E alua ion, Mo ing om he Ha dwa e A chi ec u e o he Sys em Le el,” Mic op ocesso s and
Mic osys ems, ol. 39, 2015.
[11] B. Fa ahani e al., “A C oss-Laye SER Analysis in he P esence o PVTA Va ia ions,” Mic oelec onics Reliabili y, ol. 55, 2015.
[12] V. Hua d e al., “A Bo om-Up App oach o Sys em-on-Chip Reliabili y,” Mic oelec onics Reliabili y, ol. 51, 2011.
[13] Y. Cao e al., “C oss-Laye Modeling and Simula ion o Ci cui Reliabili y,” IEEE T ansac ions on Compu e -Aided Design o In eg a ed Ci cui s
and Sys ems, ol. 33, 2014.
[14] F. Klemme, H. Am ouch, “Machine Lea ning o On- he-Fly Reliabili y-Awa e Cell Lib a y Cha ac e iza ion,” IEEE T ansac ions on Ci cui s and
Sys ems – I: Regula Pape s, ol. 68, 2021.
[15] F. R. de Rosa e al., “Using Machine Lea ning Techniques o E alua e Mul ico e So E o Reliabili y,” IEEE T ansac ions on Ci cui s and
Sys ems I: Regula Pape s, ol. 66, 2019.
[16] M. Hashimo o e al., “So E o Ra e Es ima ion wi h TCAD and Machine Lea ning,” in P oc. In . Con e ence on Simula ion o Semiconduc o
P ocesses and De ices (SISPAD), 2017.
[17] C. Xu e al., “Machine Lea ning Reg ession-Based Single-E en T ansien Modeling Me hod o Ci cui -Le el Simula ion,” IEEE T ansac ions
on Elec on De ices, ol. 68, 2021.
