In e na ional Jou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.2, June 2011
DOI : 10.5121/ lsic.2011.2202 16
A NOVEL APPROACH FOR LOWER POWER
DESIGN IN TURBO CODING SYSTEM
Dayadi.Lakshmaiah
1
D .M.V.Sub amanyam
2
D .K.Sa haya P asad
3
1
Asso.p o esso o ECE Depa men , S ee Da ha Enginee ing and Science, Hyde abad,
India.
[email p o ec ed] , [email p o ec ed]
2
P incipal and P o esso o ECE Depa men , San hi Ram Enginee ing College, Nandyal,
India.
[email p o ec ed]
3
P o esso o ECE Depa men and Rec o , JNTU Kakinada, Kakinada, India.
[email p o ec ed]
Abs ac
: Low Powe is an ex emely impo an issue o u u e mobile communica ion sys ems; The
ocus o his pape is o implemen a u bo codes o low powe solu ions. The e ec on pe o mance due o
a ia ion in pa ame e s like ame leng h, numbe o i e a ions, ype o encoding scheme and ype o he
in e lea e in he p esence o addi i e whi e Gaussian noise is s udied wi h he loa ing poin model. In
o de o ob ain he e ec o quan iza ion and wo d leng h a ia ion, a ixed poin model o he applica ion
is also de eloped.. The applica ion pe o mance measu e, namely bi -e o a e (BER) is used as a design
cons ain while op imizing o powe and a ea co e age. Low powe Op imiza ion is Pe o med on
Implemen a ion le els by he use o Vol age scaling. Wi h hose Techniques we can educed he powe
98.5%and A ea(LUT) is 57% and speed g ade is Inc eased .This ype o Powe manege is p oposed and
implemen ed based on he iming de ails o he u bo decode in he VHDL model.
Keywo ds:
low powe consump ion, Tu bo Encode , Tu bo Decode , Powe Oop imiza ion,
A eaOp imiza ion.
I INTRODUCTION
Applica ion speci ic design is a p ocess o al e na i e design e alua ions and e ined im-
plemen a ions a a ious abs ac ion le els o p o ide e icien and cos e ec i e solu ions. Tu bo
codes we e p esen ed in 1993, by Be ou e al. [20] and since hen hese codes ha e ecei ed a lo o
in e es om he esea ch communi y as hey o e be e pe o mance hanany o he o he codes a
e y low signal o noise a io. Tu bo codes achie e nea Shannonlimi e o co ec ion pe o mance
wi h ela i ely simple componen codes.
E icien me hodology o he applica ion speci ic design educes he ime and e o spen du ing
design space explo a ion. The u bo code applica ion om he a ea o wi elesscommunica ions is
chosen as he key applica ion o which an applica ion speci ic designme hodology is de eloped. The
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unc ionali y and speci ic cha ac e is ics o he applica iona e needed o ca y ou he design space
explo a ion. The applica ion cha ac e is ics s udieda e, he impac on he pe o mance o he u bo
codes wi h a ia ion in he size o he inpu message ( ame-leng h), ype o he in e lea e and he
numbe o decoding i e a ions.Tu bo coding is a o wa d e o co ec ion (FEC) scheme.
I e a i e decoding is he key ea u e o u bo codes. [1-15] Tu bo codes consis o conca ena ion
o wo con olu ion codes. Tu bo codes gi e be e pe o mance a low SNRs (signal o noise
a io) .In e es ingly, he name Tu bo was gi en o his codes because o he cyclic eedback
mechanism (as in Tu bo machines) o he decode s in an i e a i e manne . The algo i hmic
speci ica ions and he pe o mance cha ac e iza ion o he u bo codes. Fo m a p e- equisi e s udy
o de elop a low powe solu ion. Func ional analysis o u bo decode wi h simpli ied
compu a ion me ic o sa e on powe as well as he a chi ec u al ea u es like bi -wid h a e
closely ela ed o he applica ion pa ame e like bi -e o a e (BER).
II SYSTEM LEVEL MODELING
Sys em le el modeling is he phase o design aimed a a chi ec u e explo a ion be o e heac ual
HDL implemen a ion. The a ailabili y o sys em le el modeling and implemen a ion echniques
helps us o ensu e unc ional co ec ness as well as explo e he design space.The memo y access
pa e ns in he applica ion a e s udied. The da a lowanalysis as well as synch oniza ion
equi emen be ween he di e en modules o m he basis o iden i ying pa allelism in he
algo i hm. This d i es he ha dwa e solu ion o he u bo encode and decode design a sys em
le el in he design me hodology. Iden i ying he access pa e n o he compu a ionally in ensi e
ou ines, i is p oposed o use FIFO/LIFO bu e s o s o e he in e media e esul s in he ou s a e
u bo decode .To es he implemen a ion co ec ness, he u bo encode and one ou s a e u bo
decode is syn hesized on o Xilinx ISE simula o s.
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Figu e 1: The u bo coding sys em
1.Gene a e he message o be ansmi ed h ough he channel, which is a bina y da a o ame size
N. Gene a ing his message o be ansmi ed h ough he AWGN channel is done using a andom
numbe gene a o .
2. The wo encode s, depic ed in igu e 4.1 encode he message in o a bi s eam and ansmi i
h ough he channel. To he encode 1, he inpu is he message o be ansmi ed and o he
second, i is he in e lea ed message using symme ic in e lea e o size N. The encoded da a is
conca ena ed and mapped o he (1, 0) channel symbols on o an an ipodal baseband signal (+1, -
1), p oducing ansmi ed channel symbols.
3. Add AWGN noise o hese ansmi ed channel symbols o ob ain he noisy ecei e inpu .
4. Pe o m MAP decoding o six i e a ions o e ie e he message ha is ansmi ed. Bi e o
a e is compu ed o ob ain he pe o mance o he u bo decode o a yingsignal- o-noise a ios.
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Tu bo encode
Tu bo coding sys em consis s o he u bo encode and he u bo decode . The desc ip ion o he
ou s a e and eigh s a e (3GPP).
Fou s a e u bo encode
The gene al s uc u e o u bo encode a chi ec u e consis s o wo Recu si e
Sys ema icCon olu ional (RSC) encode s Encode 1 and Encode 2. The cons i uen codes a e
RSCsbecause hey combine he p ope ies o non-sys ema ic codes and sys ema ic codes.In he
encode a chi ec u e displayed in he wo RSCs a e iden ical. The N bi da a block is i s encoded
by Encode 1. The same da a block is also in e lea ed and encoded by Encode 2. The main
pu pose o he in e lea e is o andomize bu s e o pa e ns so ha i can be co ec ly decoded.
I also helps o inc ease he minimum dis ance o he u bo code . Inpu da a blocks o a u bo
encode consis o he use da a and possible ex a da a being appended o he use da a be o e
u bo encoding.The encode consis s o a shi egis e and adde s . The s uc u eo he RSC
encode is ixed o he design because enabling a ying encode s uc u es would signi ican ly
inc ease he complexi y o he decode by equi ing o adap o he new ellis s uc u e and
compu a ion o he di e en me ics in he indi idual decode s. The inpu bi s a e ed in o he le
end o he egis e and o each new inpu bi wo ou pu bi s a e ansmi ed o e he channel.
These bi s depend no only on he p esen inpu bi , bu also on he wo p e ious inpu bi s, s o ed
in he shi egis e .
Tu bo Decode
In u bo decode he i e a i e decoding p ocess o he u bo decode is desc ibed. The maximum
a pos e io i algo i hm (MAP) is used in he u bo decode . The e a e h ee ypes o algo i hms
used in u bo decode namely MAP, Max-Log-MAP and Log-MAP. The MAPalgo i hm is a
o wa d-backwa d ecu sion algo i hm, which minimizes he p obabili y o bi e o , has a high
compu a ional complexi y and nume ical ins abili y. The solu ion o hese p oblems is o ope a e
in he log-domain. One ad an age o ope a ing in log-domain is ha mul iplica ion becomes
addi ion. Addi ion howe e is no s aigh o wa d. Addi ion is a maximiza ion unc ion plus a
co ec ion e m in he log domain. The Max-Log- MAP algo i hm app oxima es addi ion solely as
maximiza ion. Max-Log-MAP algo i hm in u bo decode is used in ou wo k.
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The block diag am o he u bo decode is shown inabo e Figu e. The e a e wo decode s
co esponding o he wo encode s. The inpu s o he i s decode a e he obse ed sys ema icbi s,
he pa i y bi s eam om he i s encode and he de in e lea ed ex insic in o ma ion om he
second decode . The inpu s o he second decode a e he in e lea ed sys ema ic bi s eam, he
obse ed pa i y bi s eam om he second RSC and he in e lea ed ex insic in o ma ion om
he i s decode . The main ask o he i e a i e decoding p ocedu e, in each componen decode
is an algo i hm ha compu es he a pos e io i p obabili y (APP) o he in o ma ion symbols
which is he eliabili y alue o each in o ma ion symbol.
1) B anch me ic compu a ion
Tu bo decoding he i s compu a ional block is he b anch me iccompu a ion. The b anch
me ics is compu ed based on he knowledge o inpu and ou pu associa ed wi h he b anch
du ing he ansi ion om one s a e o ano he
Eq. 1
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2) Fo wa d me ic compu a ion
The o wa d me ic is he nex compu a ion in he algo i hm, which ep esen s he p obabili y o a
s a e a ime k, gi en he p obabili ies o s a es a p e ious ime ins ance.
Eq. 2
Whe e he summa ion is o e all he s a e ansi ions, which is o be compu ed a each node a a
ime ins ance k in he o wa d di ec ion a e sing h ough he ellis and is compu ed o s a es
00, 01, 10 and 11.
3) Backwa d me ic uni
The backwa d s a e p obabili y being in each s a e o he ellis a each ime k, gi en he knowledge
o all he u u e ecei ed symbols, is ecu si ely calcula ed and s o ed The backwa d me ic is
compu ed using equa ion 3 in he backwa d di ec ion,
Eq. 3
Whe e he s a e ansi ion is om s’, β. is compu ed o s a es 00, 01, 10 and 11 in a 4 s a e
decode . In an 8 s a e decode - 3GPP e sion is compu ed o s a es 000, 001,010, 011, 100, 101,
110 and 111.
4) Log likelihood a io (l )
Log likelihood a io ll is he ou pu o he u bo decode . This ou pu ll o each symbol a ime
k is calcula ed as
Eq. 4
The sign o he numbe co esponds o he ha d decision while he magni ude gi es a eliabili y
es ima e
.
5) Ex insic uni
Compu e he ex insic in o ma ion ha is o be ed o he nex decode in he i e a ion sequence. This
is he ll minus he inpu p obabili y es ima e. Ex insic in o ma ion ex [k-1] is ob ained om he
log likelihood a io ll [k-1] by sub ac ing he weigh ed channel sys ema ic bi s and he
in o ma ion ed om he o he decode .
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III. DESIGN MODULES
In applica ion speci ic designs, impac o a chi ec u al pa ame e s on he powe consump ion and
a ea is signi ican . Wi h inc easing demand o low powe ba e y d i en elec onic sys ems, powe
e icien design is p esen ly an ac i e esea ch a ea. Ba e ies con ibu e a signi ican ac ion o he
o al olume and weigh o he po able sys em. Ap plica ions like digi al cellula phones, modems
and ideo comp ession a e compu e and memo y in ensi e. The basic componen s in hese a e he
inpu -ou pu uni s, on-chip mem o y, o chip memo y and he cen al p ocessing uni .
Powe dissipa ion is highly dependen on he swi ching ac i i y, load capaci ance, equency o
ope a ion and supply ol age. Fu he design pa ame e s like memo y size and bi wid h in luence he
powe consump ion signi ican ly.
The powe dissipa ion o he applica ion design needs o be lowe ed using sui able a chi ec u al
op imiza ions. In his p ojec wo k a digi al design o log MAP coding o u bo encoding/decoding
is de eloped o such po able de ices.
C) FSM Con olle Uni
The op-le el con olle , whose pu pose is o ac i a e he modules in p ope o de , manages he
u bo decoding p ocess. The u bo decode which cons i u es o he wo decode s is i e a i e in
na u e. The simula ions ha e o be pe o med o six i e a ions. Hence a op-le el ini e s a e
machine (FSM) con olle uni is essen ial. A FSM consis s o a se o s a es, a s a s a e and a
ansi ion signal o mo e om he cu en s a e o he nex s a e (in u bo decode om one i e a ion
o he nex i e a ion). The FSM design appea s explici ly in he u bo decode design sys em o
he con ol and he sequencing o he i e a ions. A he da a low le el, i e a ion con ol and he da a
compu a ion o he decode sys em a e sepa a ed hen he desc ip ion o he FSM has a close
co espondence o he ypical beha io o he algo i hm.
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IV.SIMULATION RESULTS
The design is i s modeled in VHDL and hen syn hesized using Leona do ools. XPowe b ings
an ex a-le el o design assu ance o he low-powe de ice analysis. Accu a e powe es ima ion
du ing p og ammable design is done wi h XPowe . XPowe eads in ei he p e- ou ed o pos -
ou ed design da a and p o ides accu a e de ice powe es ima ion ei he by ne , o o he o e all
de ice. Resul s a e p o ided ei he in epo o g aphic o ma . The VHDL designs we e
simula ed and only syn hesized. The es ima es a e o 0.18 m echnology. The ol age ha is used
in ou es ima ion is 2.5V. The e is a acili y o se he inpu capaci ance and equency o
ope a ion o which he design powe es ima ion is o be done. The e is a p o ision o gi e a speci ic
swi ching ac i i y o he design powe es ima ion. The es ima e o 20 and 50 ac i i y ac o is
ound.
XPowe calcula es he powe as a summa ion o he powe consumed by each componen in he
design. The powe consumed is he p oduc o capaci ance, squa e o he ol age, ac i i y ac o
and equency o ope a ion and is epo ed in mW.
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Figu e:2 (A)Tu bo encode and Decode Top module Powe epo
Figu e:2 (B)Tu bo encode and Decode Top module Powe epo wi h da e
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Au ho s
Dayadi.Lakshmaiah is cu en ly wo king as an Associa e p o esso o Elec onics &
Communica ions Enginee ing.S eeDa ha Enginee ing and Science, Hyde abad,
And aP adesh (S a e), India. He Recei ed B.Tech Deg ee in ECE F om Na ional
Ins i u e o Technology, Wa angal (RECW),India and M.Tech (DSCE) Deg ee
F om JNTUni e si y , Anan apu Andh aP adesh. India Now He is Pu suing Ph.D
in Low Powe VLSI a JNTUni e si y ,Kakinada, Andh aP adesh, India.
D .M.V.Sub amanyam P o esso o ECE is cu en ly wo king as a P incipal o In
San hi am Enginee ing College Nandyal, And aP edesh, India. He has 20 yea o
Expe ience in Teaching. He au ho ed STLD, Compu e Ne wo ks and Basic
Elec onics and Mic op ocesso & Mic ocon olle In e acing and Applica ion. He
published mo e han 26 Technical pape s and Na ional and In e na ional Jou nals
and Con e eces, He has In e na ional Edi o ial Membe o he In e na ional jou nal
“In o ma ion Technology”His A ea o in e es is Adhoc Wi eless Ne wo ks,
Cellula and Mobile Communica ions. He is anEdi o ial and Technical Membe o
Th ee In e na ional Jou nals and Two Na ional Jou nals. He has Recei ed B.Tech &
M.Tech and Deg ee in ECE om JNTU, Ph.D (Adhocwi e less Ne wo k) Deg ee
om JNTUH Hyde abad Andh a P adesh India.
D . K. Sa haya P asad P o esso o ECE is cu en ly wo king as a Rec o o JNTUK,
Kakinada. He has mo e han 30 yea s o expe ience in eaching and 20 yea s o R &
D. He is an expe in Digi al Signal P ocessing. He has Guided o 10Ph.D’s and
guiding 10Ph.Dschola s. He au ho ed Elec onic De ices and Ci cui s ex book. He
held di e en posi ions in his ca ee like Head o heDepa men , ice p incipal, and
p incipal o JNTU Enginee ing College (JNTUK). He published mo e han 30
echnical pape s in na ionaland In e na ional Jou nals and con e ences. He also
ecei ed bes Teache Awa d om Go o Andh a P adesh in 2010. He is Recei ed
B.Tech Deg ee in ECE om JNTUA Anan apu , M.E(Communica ion Sys ems)
Deg ee om Uni e si y o Mad as, and Ph.D (signal P ocessing) Deg ee om he
Indian Ins i u e o Technology Mad as, India.
