Specifications of the new DELPHI LTS-CB (PAND2 - F6907)

Index. March 15, 1996 46 4.6.3 Power consumption. Table 37: Power consumption. Voltage Current Fuse +5 V 3 A 10 A -5.2 V 10 A 15 A -2 V 5 A 10 A -15 V 0.5 A 2 A Index. March 15, 1996 45 Table 36: Trigger Control Line NOTE: The old Pandora connectors N5, N6, N10 are suppressed, N8 is replaced by a single twisted pairs connector. New connector C2 Old connector N9 pins (+/-) signal I/O signal I/O 1,20 GBL O GBL O 2,21 FE_RDY O FE_RDY O 3,22 GND - GND - 4,23 - - - - 5,24 LABEL(1) I T_O I 6,25 LABEL(0) I COS_ENB I 7,26 T2_YES I T2_YES I 8,27 T2_NO I T2_NO I 9,28 T1_YES I T1_YES I 10,29 T1_NO I T1_NO I 11,30 e+pick-up I TEST 12,31 epick-up I COSMIC 13,32 CLK_BCO I CLK_BCO I 14,33 WNG_BCO I WNG_BCO I 15,34 GND - GND - 16,35 RF3 I RF3 I 17,36 GND - GND - 18,37 - - RF2 I 19 GND - - - Index. March 15, 1996 44 Table 35: NEI_DONE Attention: The pins polarity is inverted. New connector C6 Old connector N4 pins (+/-) signal I/O pins (-/+) signal I/O 1,2 NEI_DONE(0) I 1,2 NEI_DONE(0) I 3,4 NEI_DONE(1) I 3,4 NEI_DONE(1) I 5,6 NEI_DONE(2) I 5,6 NEI_DONE(2) I 7,8 NEI_DONE(3) I 7,8 NEI_DONE(3) I 9,10 NEI_DONE(4) I 9,10 NEI_DONE(4) I 11,12 NEI_DONE(5) I 11,12 NEI_DONE(5) I 13,14 NEI_DONE(6) I 13,14 NEI_DONE(6) I 15,16 NEI_DONE(7) I 15,16 NEI_DONE(7) I 17,18 NEI_DONE(8) I 17,18 NEI_DONE(8) I 19,20 NEI_DONE(9) I 19,20 NEI_DONE(9) I 21,22 NEI_DONE(10) I 21,22 NEI_DONE(10) I 23,14 NEI_DONE(11) I 23,14 NEI_DONE(11) I 25,26 NEI_DONE(12) I 25,26 NEI_DONE(12) I 27,28 NEI_DONE(13) I 27,28 NEI_DONE(13) I 29,30 NEI_DONE(14) I 29,30 NEI_DONE(14) I 31,32 NEI_DONE(15) I 31,32 NEI_DONE(15) I 33,34 GND - 33,34 GND - Index. March 15, 1996 43 Table 34: Accounting # New connector C5 Old connector N7 pins (+/-) signal I/O signal I/O 1,2 ACC#(0) O ACC#(0) O 3,4 ACC#(1) O ACC#(1) O 5,6 ACC#(2) O ACC#(2) O 7,8 ACC#(3) O ACC#(3) O 9,10 GND - ACC#(4) O 11,12 ACC#(5) O 13,14 ACC#(6) O 15,16 ACC#(7) O 17,18 GND - Index. March 15, 1996 42 Table 32: TCL (Trigger Control Lines) Table 33: LTCL (Local Trigger Control Lines) New connector C4 Old connector N2 pins (+ /-) signal I/O signal I/O 1,2 GND - TRIG_ENB O 3,4 T1_NO O T1_NO O 5,6 T1_YES O T1_YES O 7,8 T2_NO O T2_NO O 9,10 T2_YES O T2_YES O New connector C3 Old connector N3 pins (+ /-) signal I/O signal I/O 1,2 GND - GOOT_T2 O 3,4 TRIG_ENB O T1_NO_I I 5,6 T1_NO_I I T1_YES_I I 7,8 T1_YES_I I T2_NO_I I 9,10 T2_NO_I I T2_YES_I I 11,12 T2_YES_I I 13,14 GND - Index. March 15, 1996 41 • Interleaved cosmic mode. • Freeze on error. * 16. Ext_Start_Trigger must be synchronous. * 17. Former T2_Yes is now called FEF. * 18. Internal Rf generator. 4.6.2 Connectors differences Table 31: WNG’s and CLK’s New connector C1 Old connector N1 pins (+ /-) signal I/O signal I/O 13 GND - - - 12,25 WNG0 O GND - 11,24 WNG1 O WNG0 O 10,23 WNG2 O WNG1 O 9,22 WNG3 O WNG2 O 8,21 WNG4 O WNG3 O 7,20 GND - CLK1 O 6,19 CLK0 O CLK2 O 5,18 GND - CLK3 O 4,17 CLK1 O - - 3,16 GND - - - 2,15 CLK2 O - - 1,14 GND - - - Index. March 15, 1996 40 4.6 Old and New LTS Differences. 4.6.1 Basic differences The following is a list of differences between the new (Pand2) and the old Pandora. 1. FB Power requirements: Pand2 needs: +5, -2, -5.2, -15 DC volt. The -15 volt is used to stabilize the power distribution within the module. * 2. Front panel connectivity. Detailed comparison is done in section 4.6.2. * 3. CSR register definition: The new CSR implementation is different from the old Pandora. Section 4.1 gives details of the new CSR map and bit assignment. * 4. Hand shake block transfer (MS=1) to CSR space is only allowed for the T1/T2 look-up table (CSR C000-0010). The incrementing register is CSR C000-000F. No DMA transfer is allowed from FIP. 5. In response to a Stop, Pand2 ends the ongoing cycle with the trigger protocol then stops. Reset forces the State Machine to “wait for start seq” regardless to the trigger protocol. * 6. Signal protocol (T1,... T2,...) is strictly enforced due to the presence of the “State Machine”. In particular a T2 decision preceding a T1 decision has no effect. 7. There is no cosmic or time-out scaler. 8. Clocks and warnings are reset at T1_NO, T2_NO or NEI_DONE. 9. Free running clocks are always present, therefore there is no programmable delay before “Start”. Free running clock can be individually disabled (see paragraph 2 for details). 10. All clocks are 50% duty cycle. 11. Pand2 has a 4-bit hardware account # and an internal 8-bit counter incremented by T2_YES. 12. Bad quality of external signal i.e. RF3, C_BCO, W_BCO can cause the PLL to disynchronize. In the old Pandora there would be no observable immediate warning, the effect would be observed later on in the quality of the data! 13. Pand2 has four external trigger input, none has programmable delay. 14. Jitter free operation requires the external trigger to be phase locked to W_BCO, see section 2.1.1 for details. 15. Discarded features: • Internal logic analyzer. • Switch mode operation. Index. March 15, 1996 39 FIGURE 9. Protocol with readout FIP. FIGURE 10. Protocol with local-trigger box. fef nei_done read out w_bco t2 yes fe_rdy ~3.5ms trigger enable t1no t2yes/no idem as protocol with zeus start_sequence ∆t T1NO T2YES/NO trigger enable start_sequence ∆t idem as protocol with zeus Index. March 15, 1996 38 4.5 Timing diagrams. FIGURE 8. Protocol with Zeus. w_bco t1 no t1 yes t2 no t2 yes fe_rdy w_bco t1 no t1 yes t2 no t2 yes fe_rdy w_bco t1 no t1 yes t2 no t2 yes fe_rdy readout T1NO T1YES -T2NO T1YEST2YES 8µs 8µs 8µs 44µs 3.5ms 44µs Index. March 15, 1996 31 below. Only the values of M =5, 29, and 145 are possible for all bunches. Since it is desirable that the output clock frequency be “usable” (i.e. be a harmonic of bco frequency and thus have constant phase to bco time) independent of machine operation mode, M has to be one of these three values. We choose the largest value of M (i.e. 145 since this determines the step (809 KHz) by which we can program the output clock frequency. The value of M is jumpered on the board TABLE 28. Possible values of M for each kb The condition on the previous factor N/2P = integer, will simply put a constraint on the programmable values of N and P (i.e. N must be a multiple of 2P). The obtainable frequencies are given in the list of paragraph 4.3.1. Other N and P values are possible even if N/2P is not an integer, only h has to be integer. However these values are not recommended because they may produce a bad behavior of the output clock depending on the kb value. A list of these frequencies is given in 4.3.2. 4.4 Possible output frequencies for M=145. 4.4.1 Frequencies that are harmonics of the bco frequency (any kb). In this case N is a multiple of 2P . The following list contains 169 frequencies. Note: a given frequency can be obtained with different sets of (N,P) values (e.g (50,0) produces the same result as (100,1)). Only the solution with the highest N is given in this list, since the PLL has optimal working point with high N values. TABLE 29. Harmonics of the BCO freq. Freq. [MHz] period [ns] N P Freq. [MHz] period [ns] N P 5.6676 176.4405 56 3 6.4774 154.3839 64 3 7.2870 137.2312 72 3 8.0967 123.5071 80 3 8.9064 112.2784 88 3 9.7160 102.9226 96 3 10.5258 95.0049 104 3 11.3354 88.2193 112 3 Bunches M 4 2 3 5 6 9 15 18 29 30 45 58 87 145 8 3 5 9 15 29 45 87 145 12 2 3 5 6 10 15 29 30 58 87 145 18 2 4 5 10 20 29 58 145 36 2 5 10 29 58 145 Index. March 15, 1996 30 4.3 Constraints on generated frequencies. Only certain values for M, N, and P give a correct synchronization of the generated clocks with respect to the LEP machine cycle. The following considerations apply: 1. Due to the PLLs the clocks are fractions of RF /3 (fig.7). Thus: clock = N* (Rf / 3) / (M * 2P); 2. If the clocks have to be harmonics of the bco frequency, then: clock = h * bco_freq with h integer, where: bco_freq = (RF * kb) / 31320 with: RF = 352254170 Hz, kb = number of bunches in LEP and 31320 = 23 * 33 * 5 * 29 (the harmonic number or the number of RF oscillations per revolution period in LEP). FIGURE 7. Basic Block diagram of frequency generation circuit. This results in the following constraint on M, N and P: N *( 23 * 33 * 5 * 29) / (3 * kb * M * 2P)= h an integer (formula 1) This condition is certainly met when both factors: N / 2P and (23 * 33 * 5 * 29) / (3 * kb * M) are integers. Consider the second factor for the different possibilities of bunches in LEP, i.e. kb=4, 8, 12, 18, 36. The list of possible values of M for each kb are given in the table /M / N phase comp filter vco RF/3 RF3 * N/(M*2P) /2P Index. March 15, 1996 29 4.2.3 CSR register to Time (WNG4). CSR C000_000A bits <14..0> = LEcounter bits <30..16> = TEcounter Note: This formula is valid for LE and TE counters greater then zero. 4.2.4 Time to CSR register (WNG4). CSR C000_000A bits <14..0> = LEcounter bits <30..16> = TEcounter Note: This formula is valid for LE/TE counter greater then zero. LEdelay LEoffset 29 LEcounter( ) TimeStep+= TEdelay TEoffset 29 LEcounter TEcounter+( ) TimeStep+= LEcounter floor LEdelay LEoffset– 29TimeStep --------------------------------------------------     = TEcounter floor TEdelay TEoffset– 29TimeStep -------------------------------------------------- LEcounter–     = Index. March 15, 1996 28 4.2.1 CSR register to Time (WNG0, WNG1, WNG2,WNG3, CLK0, CLK1,CLK2). WNG0 / WNG1 / WNG2 / WNG3 (CSR C000_0000 to C000_0003) bits <2..0> = LEphase [A..E] bits <13..3> = LEcounter bits <18..16> = TEphase [A..E] bits <29..19> = TEcounter CLK0 / CLK1 / CLK2 / Trig_Enable(CSR C000_0004 to C000_0006, C000_000E) bits <2..0> = LEphase [A..E] bits <13..3> = LEcounter 4.2.2 Time to CSR register (WNG0, WNG1, WNG2,WNG3, CLK0, CLK1,CLK2). WNG0 / WNG1 / WNG2 / WNG3 (CSR C000_0000 to C000_0003) bits <2..0> = LEphase [A..E] bits <13..3> = LEcounter bits <18..16> = TEphase [A..E] bits <29..19> = TEcounter CLK0 / CLK1 / CLK2 / Trig_Enable(CSR C000_0004 to C000_0006, C000_000E) bits <2..0> = LEphase [A..E] bits <13..3> = LEcounter LEdelay LEoffset 5LEcounter LEphase+( ) TimeStep+= TEdelay TEoffset 5LEcounter 5TEcounter TEphase+ +( ) TimeStep += LEcounter floor LEdelay LEoffset– 5TimeStep --------------------------------------------------     = LEphase floor 5LEdelay LEoffset– 5TimeStep -------------------------------------------------- LEcounter–         = TEcounter floor TEdelay TEoffset– 5TimeStep -------------------------------------------------- LEcounter–     = TEphase floor 5TEdelay TEoffset– 5TimeStep -------------------------------------------------- TEcounter–LEcounter–         = Index. March 15, 1996 27 TABLE 26. NTA • monitoring; start seq, T1_Y, T1_N, T2_N, T2_Y, start fef, e+, e-, c_bco, w_bco. 4.2 Timing formulas Definitions: •LE = Leading Edge, TE = Trailing Edge •LEoffset and TEoffset are the minimal delay •TimeStep = 8.51658 ns (1/rf3) •floor(x) returns the greatest integral value less than or equal to x. This corresponds to IEEE rounding Table 27: Signal offsets. NOTE: Values in Table 27 are average values for the 32 Pandoras. The actual values (in nsec) for each Pandora can be found (after “ONLSETUP Trigger”) in: PAND2$DIR:PAND_OFFESTS.DAT Data are formatted according to: Pandora# (I3) Warnings LEs (5E16.7) Warnings TEs (5E16.7) Clock LEs (3E16.7) bit read meaning write meaning <31,30,4..0> nta bits set nta bits Signal LE Offset (ns) TE Offset (ns) WNG0 326.0 420.5 WNG1 326.0 420.5 WNG2 326.0 420.5 WNG3 326.0 420.5 WNG4 803.0 1058.0 CLK0 350.0 CLK1 350.5 CLK2 350.5 Trig_Enable 301.0 Index. March 15, 1996 26 See section 4.2 for details on the correspondence CSR content delay value. Note: rf3/5 = 42ns period. b2,b1,b0 Phase select 0,0,0 A 0,0,1 B 0,1,0 C 0,1,1 D 1,x,x E TABLE 22. CSR C000_000F; current look up table address (loadable up counter) Note: When loading the look up table using a fastbus block transfer, the start address for both T1 and T2 look up table, corresponds to the T1 look-up table pointer only. TABLE 23. CSR C000_0010; (4kx2 SRAM) TABLE 24. CSR C000_0011 TO C000_0018; scalers (in the following order): c_bco, gated c_bco, start seq, T1_Y, T1_N, T2_N, T2_Y, fe_rdy; Attention: every scaler counter reacts directly to the signal on the corresponding input line, i.e. spikes will be counted. TABLE 25. CSR C000_0019; Account number Phase SelectCounts (42 nsec) bit read meaning write meaning <11..0> T1 look up table pointer/Fastbus address set T1 look up table pointer/ Fastbus address <27..16> T2 look up table pointer set T2 look up table pointer bit read meaning write meaning <1..0> t2 & t1 look up table contents select t2 & t1 look up table contents bit read meaning write meaning <31..0> read value none bit read meaning write meaning <23..16> read value select acc# value Index. March 15, 1996 25 Nei_done delay = 7.93 µs+ 15.808 µs*value<7..0> int_oscill_period= 31.616 µs+ 15.808 µs * Σ bi * 2 2(i-16); where: bi = 0 if bit i is off 1 if bit i is on i= 25...16 Note: rf3/(29*64) = 15.808 µs. Note: Nei_Done delays counters starts counting from T2-Yes leading edge TABLE 17. CSR C000_000A; wng4 parameters See section 4.2 for details on the correspondence CSR content delay value. Note: value 0 for the delay of both LE and TE is not supported TABLE 18. CSR C000_000B; nei_done mask TABLE 19. CSR C000_000C; external start trigger mask TABLE 20. CSR C000_000D; t2 label latch TABLE 21. CSR C000_000E; internal trigger enable delay bit read meaning write meaning <14..0> present leading edge delay select leading edge delay <15> wng-enable status 0=enable wng, 1=disable wng <30...16> present trailing edge delay select trailing edge delay <31> trailing edge disabled 0=enable, 1=disable Counts (247 nsec) Note: rf3/29 = 247 ns period. bit read meaning write meaning <15..0> present value of mask select mask value <31..16> current status of inputs none bit read meaning write meaning <3..0> present mask value select mask bit read meaning write meaning <3..0> latched t2 label none bit read meaning write meaning <2..0> present leading edge phase selection select leading edge phase <12..3> present leading edge delay select leading edge delay Index. March 15, 1996 24 The first three bits of the clock counters, are used to select one of the five rf3 phases. This allows a fine tuning of the edges in steps of 8.516 ns (rf3). See section 4.2 for details on the correspondence CSR content delay value. C000_0004; clk0 b2,b1,b0 Phase select C000_0005; clk1 0,0,0 A C000_0006; clk2 0,0,1 B 0,1,0 C Note: rf3/5 = 42ns period. 0,1,1 D 1,x,x E Note: in the case of freerunning clocks, both the phase selection (bit <2..0> and the start delay (bits<13..3> must be equally loaded on all the clocks. In particular the values 0 are suggested. TABLE 14. CSR C000_0007; clock frequencies N values = BitInvert[Nbit - 1] TABLE 15. CSR C000_0008; internal T1 and T2 delay T1 delay = 356 ns + 247 ns*value<11..0> T2 delay = 359 ns + 247 ns*value<30..16> Note: rf3/29 = 247ns period. NOTE: T1 delay = 0 and T2 delay = 0 must not be used. TABLE 16. CSR C000_0009; nei_done delay & internal start oscillator Phase SelectCounts (42 nsec) bit read meaning write meaning <7..0> present Nbit for clk0 select Nbit for clk0 <9,8> present P for clk0 select P for clk0 <17..10> present Nbit for clk1 select Nbit for clk1 <19,18> present P for clk1 select P for clk1 <27..20> present Nbit for clk2 select Nbit for clk2 <29,28> present P for clk2 select P for clk2 bit read meaning write meaning <11..0> present internal T1 delay select internal T1 delay <30..16> present internal T2 delay select internal T2 delay bit read meaning write meaning <7..0> internal nei_done delay set internal nei_done delay <25..16> internal start oscill period set oscillator period Index. March 15, 1996 23 TABLE 11. state machine status; {S4,S3,S2,S1} TABLE 12. CSR C000_0000 TO C000_0003; warning parameters The first three bits of the warning counters are used to select one of the five rf3 phases. This allows a fine tuning of the edges in steps of 8.516 ns (rf3). See section 4.2 for details on the correspondence CSR content delay value. C000_0000; wng0 b2,b1,b0 Phase select C000_0001; wng1 0,0,0 A C000_0002; wng2 0,0,1 B C000_0003; wng3 0,1,0 C 0,1,1 D Note: rf3/5 = 42ns period. 1,x,x E TABLE 13. CSR C000_0004 TO C000_0006; clock parameters Pulse count = BitInvert[value<31..16> - 1] value state 1 means ‘waiting for start_sequence’ 2 means ‘waiting for t1yes or t1no’ 4 means ‘waiting for t2yes or t2no’ 8 means waiting for nei_done’ bit read meaning write meaning <2..0> present leading edge phase selection select leading edge phase <12..3> present leading edge delay set leading edge delay <15> wng-enable status 0=enable wng, 1=disable wng <18..16> present trailing edge phase selection select trailing edge phase <28..19> present trailing edge delay set trailing edge delay <31> trailing edge enable/disable 0=enable, 1=disable Phase SelectCounts (42 nsec) bit read meaning write meaning <2..0> present leading edge phase selection select leading edge phase <13..3> present start-delay select start-delay <14> 0=freerunning,1=burst 0=freerunning, 1=burst <15> clk-enable status 0=enable clk, 1=disable clk <31..16> present pulse count select pulse count Index. March 15, 1996 22 4.0 Appendices. 4.1 CSR map and bit assignment. TABLE 9. CSR0; mode control TABLE 10. CSR 1; source selection, PLL status bits read meaning write meaning (bit value) <2> stop/running (0/1) set in run mode <6> none reset scalers <12> waiting for csr nei_done none <13> local/global line status (0/1) set global line (1 = global) <18> none set in stop mode (1) <28> none set csr nei_done (1) <29> none reset global line (0) <31..16> Device ID (6907) none <30> none reset state machine (0) bit read meaning write meaning <1,0> selected start-sequence source select start_sequence source <3,2> selected t1 source select t1source <5,4> selected t2 source select t2 source <7,6> selected nei_done source select nei_done source <8> PLL0 lock status (unlock = 0) none <9> PLL1 lock status (unlock = 0) none <10> PLL2 lock status (unlock = 0) none <11> selected rf3 source 0 = internal rf3 / 1= external rf3 <15..12> state bits S4..S1 of State Machine none <21..16> Pandora Serial Number none <23,22> BCO code set BCO code ‘0’ for 4 bunches ’1’ for 8 bunches ‘2’ for 12 bunches ‘3’ for 18 bunches. <31> Selected rf3 status (‘1’ if present) none Index. March 15, 1996 15 3. The rf block groups together all the high frequency sections of the Pandora, i.e.: the internal rf3 and c_bco generator (it also generates the internal w_bco) and the three PLLs along with their burst generators. 3.2 RF part. 3.2.1 Phase locked loop. Each of the PLL daughter board can generate independently clocks with programmed frequency. This choice of implementation is one of the major differences between the new Pandora and the old one. In our implementation the PLL produces frequencies from 5 MHz to about 140 MHz (rf3 is 117.418 MHz). It also allows a finer stepping of the output clock frequencies (i.e. 809 KHz). Figure 4 shows the block diagram of the PLL. FIGURE 4. Phase lock loop and burst generator. Fvcm: output frequency from VCM (Voltage Controlled Multivibrator, range 40 to 140 MHz). Fout: output frequency after division by 2P (P=0,1,2,3). 3.2.2 Warning circuit. Two counters per warning (fig.5) generate the initial dead time (time during which the warning is held OFF, i.e. between “start delay” and “end of start delay”) and the RF/3 / 145 /2 VCM /2 /N (50....175) Fvcm Switches CSR CSR Fout enable CLK free running /2 p Filter Phase comp PLL lock status Burst generator start burst reset reset by c_bco Index. March 15, 1996 14 3.0 Implementation notes. 3.1 Block diagram. Fig3. illustrates in more detail the implementation chosen for the new Pandora. The whole unit can be logically broken down into three blocks: 1. the Fastbus coupler & CSR’s block, 2. the control machine block, 3. the rf block. FIGURE 3. Block diagram. 1. The operating configuration of the Pandora, as well as the internal status, can be controlled via the Fastbus coupler and CSR blocks. The Fastbus also provides the logical interface between the RF and the CONTROL MACHINE sub-units. 2. The control machine contains the state machine that personalizes the use of the Pandora, as well as the generation of the warnings and the delays of the CLK bursts. The state machine also provides the protocol for interfacing the Pandora to Zeus, the FIP and the local trigger box. Wngs & RF COUPLER CNTRL MACHINE FASTBUS rf3 c_bco w_bco t1/t2(gbl and loc) ext_start ext_confirm nei_done trigger_enable fef fe_rdy global CLKs WNGs c_bco CSRs Int rf3 & c_bco Delays State machine PLLs & Bursts start_burst FASTBUS 3 3 5 Index. March 15, 1996 13 •block transfer the data to csr C000_0010 (read or write). An SS2 response will indicate when the end address of the memory has been reached. CSR C000_000F will auto increment on each transfer and will contain at the end of transfer the last memory address accessed. Random data read/write is also possible, but this will not auto increment the address (CSR C000_000F) Possible uses: • if one wants to run the DAQ system locally in a mode where on every start_sequence a readout should occur (t2-yes). This is possible by programming all 1-values in this lookup table and selecting this as a t1/t2 source. • one can locally control t1 and t2 trigger rates accurately for DAQ tests. •by loading a random pattern, random t1/t2 trigger sequences can be generated locally. 2.6 Removed features. With respect to the current Pandora the following features are dropped: 1. internal logic analyzer 2. switchmode operation 3. interleaved cosmic 4. freeze on error 5. programmable delay on external start triggers. Index. March 15, 1996 12 csr1<23,22>. The code will select 4,8,12 or 18 bunch mode for the code values 0,1,2,3. 2.4 Fastbus access. Only CSR space is implemented, there is no Fastbus data space (DSR). A full map is given in 4.1 where the meaning of the different bit fields is given. Permitted Fastbus data cycles are secondary address read/write, random read/write and handshake block transfer read/write (i.e. MS=1)2. Only geographical addressing and general broadcast to CSR are supported for primary addressing. Block transfer is only possible to register C000_0010. In the run mode only csr 0 and csr C000_0019 can be written to. Writing to other registers is only permitted if the unit is in stop mode. Reading the registers is always possible in any mode. SS=6 is produced in case of: • a random data access after a bad NTA was loaded • an unsupported MS-code during data access • unauthorized write access to a csr when the module is in run • a block transfer access to an NTA value different from csr C000_0010 SS=7 is produced when a bad value is loaded in the NTA register. SS=2 is produced during block transfer, when csr C000_000F reaches a memory address >= 4096. 2.5 Programmable lookup table. One can use a built-in 4K x 2 bit memory as a table to look up programmed t1/ t2 decision sequences. If bit0 is ‘1’ this will produce a t1yes, if ‘0’ a t1no. Similarly, bit1 will produce a t2yes if ‘1’ or a t2no if ‘0’. T1 and T2 have two independent pointers. During local run the T1 pointer increments at every new start sequence, the T2 pointer increments at every new T1 yes. Register C000_000f contains the memory location that is accessed on the first start_sequence. This register also contains the location which was last accessed during run. In run the memory is used as a circular memory (when reaching the end of memory, the pointers are reset to the start of memory). To load the lookup table memory one has to proceed as follows; •load csr C000_000F with the start address in memory (usually 0, but one can start anywhere). 2. IEEE standard FASTBUS 960-1989 and revision IEEE standard FASTBUS 1177-1989 Index. March 15, 1996 11 2.2.5 Remark on different modes. There are no hardware constraints on the possibility to combine different sources for all the signals used by the State Machine (see Fig.2). Some valid combinations that reproduce typical operating modes are given in table 2. TABLE 2. Some operating modes 1except w_bco 2except csr bit 3LUT filled with all “1s” to produce always T1yes and T2yes 4if no ext_conf trigger within the T1_delay, a T1no is generated 2.2.6 Remark on different statuses When the Run bit is set, the state machine can cycle provided the correct trigger protocol is present. When the Stop bit is set, the Pandora terminates the current cycle and stops. Reset bit 30 only resets the state machine to “waiting-for-start-sequence”. The reset is not done automatically by stopping the Pandora. Global bit produced by the pandora is used in the protocol with Zeus, the C2 connector carries a copy of this bit. The global bit status is independently of the Pandora run/stop status. 2.3 Other internal features. Internal rf3 generation (crystal oscillator with frequency of 117.418 MHz) can be selected by clearing csr1<11>. This allows the Pandora to function in the absence of external rf3. When internal rf3 is selected, c_bco and w_bco signals are also generated internally. The internal w_bco is the internal c_bco gated by the internal fe_rdy. It is also possible to select the number of bunches using a 2 bit code in Typical operating modes Pandora selections start-sequence t1yes t1no t2yes t2no nei_done global w_bco gbl gbl gbl gbl any2 local-normal c_bco loc loc loc loc any local-random any1progr progr progr progr any local-start ext_st_trig progr3progr3progr3progr3any local-confirm any1ext_conf trigger default4always yes N.A. any Index. March 15, 1996 10 2.2.2 Sources for start_sequence. The start_sequence is selected with csr1<1,0>. The corresponding 2 bit values are shown below in parentheses 1. warning bco (1,0) 2. clock bco (1,1) 3. external start trigger (0,0) 4. internal oscillator (0,1). This oscillator is programmable (csr C000_0009<25:16>, range 5.525 sec., step 15.808 µs (rf3/29 * 1/64)). This oscillator permits the emulation of the detector dead time. The start_seq is always initiated by the w_bco following the rising edge of the oscillator. 2.2.3 Sources for T1 and T2. The selection of the T1 and T2 sources is done by using csr1<3,2> (for T1) and csr1<5,4> (for T2). The corresponding 2 bit values are shown below in parentheses. 1. global T1 and T2 (1,0) 2. local external T1 and T2 (1,1) 3. internal programmed table (0,0) (see section 2.5) 4. external confirm trigger (0,1) Timings: When T1 and T2 are internally generated; T1 is derived from start_sequence after a programmable delay (csr C000_0008<11:0> range 1.01 ms, step rf3/29 (247 ns), min delay 359 ns). T2 is also derived from start_sequence after a programmable delay (csr C000_0008<30:16>, range 8.094 ms, step rf3/29 (247 ns), min delay 412 ns). Attention: The minimum delay value that the user may put into the csr is 1; if the value is 0 no output is produced. 2.2.4 Sources for nei_done. The selection of the nei_done source is done by using csr1<7,6>.The corresponding 2 bit values are shown below in parentheses: 1. (1,0) selects the pattern of 16 externals inputs, controlled by the contents of csr C000-000B (Nei_Done mask) 2. (1,1) selects the internal source derived from start_sequence after a programmable delay (csr C000_0009, range 4.05 ms, step 15.808 µs (rf3/29 * 1/64), min delay 24 µs) 3. (0,0) allows the control of the live time by software. When csr0<12> contains the value ‘1’ the module waits for a nei_done signal. Writing a ‘1’ in bit<28> of csr0 produces this nei_done and clears the bit<12>. The module finishes the cycle and is then again sensitive to new triggers. Index. March 15, 1996 9 2.2 Definition of control state machine. 2.2.1 Basic sequence. Pandora has one basic sequence of states as drawn schematically in fig.2. The transitions between states are governed by signals that can be selected from a list of possible sources. Different combinations of these sources give different modes of operation (local, global, etc.). FIGURE 2. basic trigger sequence. By resetting the module (csr0 <30>) the machine resets to the state ‘initialize’ and ‘wait-for-start-sequence’. wait for start-sequence wait-for-t1 wait-for-t2 trigger-fef wait-nei_done initialize clk-bco ext-start-trigger int-oscillator gbl_t1yes loc_t1yes int-progr-t1yes ext-confirm-trigger ext nei_done int-nei_done csr-nei_done nei_done wng-bco gbl_t1no loc_t1no int-progr-t1no gbl_t2yes loc_t2yes int-progr-t2yes always yes gbl_t2no loc_t2no int-progr-t2no start sequence t1yes t1no t2yes t2no int-t1no (time out) csr1<3:2> csr1<3:2> csr1<1:0> csr1<7:6> csr1<5:4> csr1<5:4> 2 0 1 3 2 0 1 3 2 0 1 3 2 0 1 3 2 0 1 3 2 0 1 3 Index. March 15, 1996 8 TABLE 1. Electrical signal description name I/O number type remarks w_bco I 1 diff ecl c_bco I 1 diff ecl global O 1 diff ecl gbl_t1no I 1 diff ecl gbl_t1yes I 1 diff ecl gbl_t2no I 1 diff ecl gbl_t2yes I 1 diff ecl fe_rdy O 1 diff ecl rf3 I 1 diff ecl t2label I 2 diff ecl 4 bit bus but only 2 LSB’s e+/eI 2 diff ecl 2 bit bus loc_t1no I 1 diff ecl loc_t1yes I 1 diff ecl loc_t2no I 1 diff ecl loc_t2yes I 1 diff ecl trigger_enable O 1 diff ecl t1no O 1 diff ecl selected gbl. or loc. t1yes O 1 diff ecl selected gbl. or loc. t2no O 1 diff ecl selected gbl. or loc. t2yes O 1 diff ecl selected gbl. or loc. fef O 1 NIM nei_done I 16 16 diff ecl plus 2 NIM’s masked & ORed together ORed with diff ecl input warnings O 5 diff ecl 5 bit bus (last one special) clocks O 3 diff ecl 3 bit bus ext_start_trigger I 4 diff ecl and NIM’s masked and ORed together ext_confirm_trigger I 1 diff ecl and NIM monitoring O 17 NIM’s various test signals acc number O 4 diff ecl 4 bit bus Index. March 15, 1996 7 •warnings 0 - 3: each warning has a programmable start-delay (csr C000_0000 to C000_0003, range 80 µs, step 8.5 ns, min-delay 326.0 ns) and programmable width (csr C000_0000 to C000_0003, range 80 µs, step 8,5 ns, min-delay 94.5 ns); the delays are started by the selected start-sequence source. They are reset by the selected t1-no, t2-no or nei_done. Each warning can be individually disabled by csr C000_000<15> to C000_003<15>. •warning 4: This special warning has a programmable start-delay (csr C000_000A, range 300 µs, step rf3/29 (247 ns), min-delay 803.0ns) and programmable width (csr C000_000A, range 220µs, step rf3/29 (247 ns), min-delay 253.0ns); the delays are started by the selected start-sequence source. They are reset by the selected t1-no, t2-no or nei_done. The warning 4 can be disabled by csr C000_00A<15>. •clocks: each clock can be either free running or burst (csr C000_0004<14> to C000_0006<14>). In this latter case they have a programmable start delay (csr C000_0004<13:0> to C000_0006<13:0>, range 80 µs, step rf3 (8.5 ns), min-delay 350.0ns) and a programmable number up-to 216 counts (csr C000_0004<31:16> to C000_0006<31:16>). The frequencies that can be generated are given by the following formula: f = N/(M*2P)* (RF3) with M=145 and for N=50,...185 and P=0,1,2,3 •This gives frequencies in a range from 149,809MHz (6.67 ns) down to 5.06 MHz (197.59 ns) (see annexes 4.2 and 4.3). N must always be a multiple of 2P to keep a constant phase relation to c_bco (i.e. to keep the correct synchronization with LEP). •A list and more details are found in 4.3 •Each clock can be individually disabled by csr C000_0004<15> to C000_0006<15> •t2label: on every gbl_t2-yes Zeus will generate a 4 bit label. Pandora will latch its 2 LSB’s in the right most position of csr C000_000D<3:0>. This feature will be available when Zeus and the Zeus fan-outs are updated. •e+ and e-: these are the discriminated pick-up signals. Pandora receives them on the TCL connector and makes them available on the front panel for precise triggering. This feature will be available when Zeus and the ZEUS fan-outs are updated. Index. March 15, 1996 6 •loc_t1-yes: positive first level trigger result. Pandora reacts to its leading edge and will change the current state to ‘wait-for-t2’. Digitizing continues (i.e. the clock and warning signals are not stopped). •loc_t2-no: negative second level trigger result; Pandora reacts to its leading edge and will immediately reset the current state to ‘wait-for-start-sequence’. All clock and warning signals are reset (except the free running clocks). •loc_t2-yes: positive second level trigger result; Pandora reacts to its leading edge and will change the current state to ‘trigger-front-end-freeing’. Digitizing continues (i.e. the clock and warning signals are not stopped). •trigger enable: this signal is asserted after a programmable delay (csr C000_000E, range 80 µs, step rf3 (8.5 ns), min-delay 301.0 ns) started by the selected start-ofsequence source and deasserted after receiving the selected t1-no or any selected t2. •fef: it is asserted immediately after receiving the selected t2-yes source and deasserted when Pandora receives the selected nei_done. •nei_done: next event identification done signals; 16 inputs to which a programmable don’t-care-mask (csr C000_000B<15:0>) is applied. When all expected inputs are present for more than 50 ns (to avoid spurious glitches) Pandora changes state to ‘reinitialise’. All clock and warning signals are reset (except the free running clocks). Inputs <00> and <01> are an ORed combination between the differential ECL and NIM inputs. The current logical state of these inputs can be read in csr C000_000B<31:16>. •external_start_trigger: 4 input signals with selective enable mask (csr C000_000C). The four external start trigger inputs (NIM and the corresponding ECL are ORed) are ORed after masking. Note that the external start trigger must be synchronous with c_bco, i.e. the pulse must have a constant delay (any allowed, in particular 0) with respect to c_bco1. •external-confirm-trigger: this signal acts as a loc_t1-yes. After a start_seq the pandora continues to digitize if the external confirm trigger is asserted within a time window specified in csr C000_0008 (internal T1 delay). If the external confirm trigger is not asserted, the Pandora generates an internal t1-no and changes state to “waiting start seq”. •monitoring: Important signals (such as: 5 x wng’s, 3 x clk’s, w_bco, c_bco, e+/epick ups, t1_y/n, t2_y/n, fe_rdy) are available on the front panel as NIM. LED’s provide quick visual display of Fastbus access, run mode, global bit, sel. int rf3, sel. ext c_bco, 3 x PLL lock status. More information on the Pandora state is given through CSR’s, see section 4.1. •acc number: This is an internal register (csr C000_0019<23:16>) incremented by selected T2_yes. The 4 LSBs are available on the front panel connector C5, and can be read/written by fastbus. 1. Operatively the delay from c_bco to the ext_start must be programmed (in units of rf3 = 8.51 nsec.) in bit <13..0> of csr C000-0004 (clock0), csr C000-0005 (clock1), csr C000-0006 (clock2).