Tutorial on TCAD simulation of Ferroelectric Schottky Barrier Field Effect Transistor (Fe-SBFET)

Tutorial TCAD simulation of Fe-SBFET Marie Skłodowska-Curie Actions (MSCA) EASIFeT - Grant agreement ID: 101108023 Researcher: Chiara Rossi Supervisor: David Esseni Department: DPIA – University of Udine Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 2 Summary This tutorial describes the TCAD workflow developed for the simulation of the Ferroelectric Schottky Barrier Field Effect Transistor (Fe-SBFET). The document contains a description of the approaches and models used in the 2D and 3D TCAD setups, adapted to different device design options. The models have been calibrated to experimental measurements of structures fabricated by collaborators at the Institute of Solid State Electronics in TU Wien. Simulation results and comparison between different models and simulation approaches are presented. TCAD simulations have been performed with Synopsys Sentaurus TCAD 1 . Table of Content Summary .................................................................................................................................... 2 1. Introduction ........................................................................................................................ 3 2. TCAD simulation flow: structures and models for device simulations ............................. 4 a. Simulation of ferroelectric layer ........................................................................................ 4 b. Simulation of Schottky junctions ....................................................................................... 9 c. Simulation of Fe-SBFET .................................................................................................. 13 3. Simulation results ............................................................................................................. 17 4. Calibration to experimental measurements ...................................................................... 29 A. Appendix .......................................................................................................................... 34 1 https://www.synopsys.com/manufacturing/tcad/device-simulation.html Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 3 1. Introduction The Fe-SBFET is based on the ferroelectric polarization-induced modulation of the Schottky barrier at the junction between source and drain metal and the semiconductor region. In particular, the tunnelling at the Schottky barrier is modulated by the polarization-induced band bending in the semiconductor layer. This device can be fabricated using two different design options, shown in Fig. 1. In a first option (Fig. 1.a), the ferroelectric layer is present only on top of the Schottky junctions at source and drain. In this case, the ferroelectric polarization can only affect the Schottky barriers, while it does not modulate the carrier concentration in the middle of the channel. The program gates placed on top of the ferroelectric layers are only used to set the polarization state and an additional gate electrode is needed to turn on the FET and read the drain current, which is influenced by the ferroelectric polarization. This gate can be an additional front gate or a back gate, as depicted in Fig. 1.a. Here we will consider a back gate, a) b) Figure 1. Two different design options for the Fe-SBFET: a) the ferroelectric layer lies only on top of the source and drain Schottky junctions; b) the ferroelectric layer extends also on top of the semiconductor channel region. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 4 as this structure has an easier fabrication process and for which experimental realization are more easily found in literature 2 . The second option (Fig. 1.b) employs a ferroelectric layer on top of both the source/drain Schottky junctions and the FET channel. This device is similar to a conventional FeFET, but with Schottky contacts placed below the ferroelectric layer such that they can be modulated. Fabricated Fe-SBFETs using this design have been also reported in literature 3 . In this device we have both the polarization-induced Schottky barrier modulation and the polarizationinduced modulation of carrier concentration in the channel. Even though a back gate can be used to perform specific synaptic functionalities, for a simple memristor only a single gate is needed in this case for both setting the polarization and reading the drain current. Different TCAD simulation setups have been developed to simulate these two device options in 2D and 3D. This tutorial is more focused on the first design in Fig. 1.a. 2. TCAD simulation flow: structures and models for device simulations Before describing the TCAD simulation workflows of the full devices including both the ferroelectric layer and the Schottky junctions, individual modeling of the two sub-blocks is detailed. The tutorial will first address the modeling and simulation of polarization switching in ferroelectric layers, then it will address Schottky junctions modeling and finally it will present simulations of the full devices. a. Simulation of ferroelectric layer Within the Sentaurus TCAD simulator, two different models are available to simulate the behaviour of the ferroelectric materials: one is based on the Preisach model and one is based on the Ginzburg–Landau–Khalatnikov equation. A Preisach-based model is a phenomenological model that describes a macroscopic hysteretic system composed by a superposition of simple hysteresis units, where each unit has a rectangular hysteresis loop4. Fig. I shows a ferroelectric thin film capacitor represented as a system of parallelly connected, non-interacting units with rectangular hysteresis: the switching charge θ, and the coercive voltages α and β, for each unit can be different, resulting in a smooth total hysteresis loop (Fig. I.c). In Preisach-based models for ferroelectric hysteresis, the polarization ( 𝑃) versus electric field ( 𝐹) relation is modelled using a hyperbolic tangent function because it is a simple form, it has the correct physical properties, and provides a 2 F. Xi et al., Adv. Electron. Mater. 2023, 9, 2201155, DOI: 10.1002/aelm.202201155; D. Nazzari D, et al., ACS Appl Mater Interfaces. 2025 Feb 19;17(7):10784-10791, doi: 10.1021/acsami.4c16400 3 F. Xi et al., ACS Appl. Mater. Interfaces, 13, 27, p. 32005, 2021; F. Xi et al., IEEE JEDS, vol. 10, pp. 569, 2022; V. Sessi et al., in Proc IEEE-NANO 2018, p.1; V. Sessi, et al., Adv. Electron. Mater., 6, p. 1901244, 2020. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 5 reasonably good agreement with experiments for most ferroelectric thin film capacitors 4 . The equation used by Sentaurus Device is the following 5 : 𝑃=𝑐&∙𝑃!∙tanh , 𝑤∙ ( 𝐹±𝐹" )0 +𝑃#$$ where 𝑤= 1 2𝐹"ln𝑃!+𝑃% 𝑃!−𝑃% and 𝑃! is the saturation polarization, 𝑃% is the remanent polarization (see Fig. 2), 𝐹" is the coercive field, 𝑃#$$ and 𝑐 are used to account for the polarization history of the material. The model features also minor loop nesting. Sentaurus Device memorizes turning points, i.e. points in the 𝑃 – & 𝐹 diagram where the sweep direction of the electric field 𝐹 changes from increasing to decreasing or viceversa, as they are encountered during a simulation. The memory always contains the points defining the two curves of the saturation loop (with 𝑐 = 1 and 𝑃#$$ = 0), i.e. (¥,Ps) and (–¥,–Ps). All other pairs of turning points result in 𝑐 < 1 and 𝑃#$$ ≠ 0 and define a 4 B. Jiang et al., Computationally Efficient Ferroelectric Capacitor Model for Circuit Simulation, 1997 Symposium on VLSl Technology Digest of Technical Papers , p.141 5 Sentaurus Device of Synopsys TCAD, User Guide, V-2023.12 Figure I – (a) Ferroelectric thin film capacitor represented as an hysteretic system composed by a superposition of hysteresis units with rectangular hysteresis (b). α β and θ for each unit can be different resulting in smooth hysteresis loop (c). a) b) Figure II – a) Polarization and electric field in a ferroelectric capacitor. b) Polarization – electric field curve simulated by Sentaurus TCAD using the Preisach-based model. The points on the polarization curve are reached in the sequence a, b, c, d, e, f, g, f, h, i, k, i, e, c. The diagram also illustrates the feature of minor loop nesting. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 6 pair of curves forming minor loops (see Fig. 2.b). Sentaurus Device also features transient simulations by employing auxiliary polarization and auxiliary electric field2. The parameters of the Preisach-based model, i.e. 𝐹" , 𝑃! and 𝑃% have been calibrated to describe the experimental polarization versus electric field curve of the HZO capacitors (simple HZO layer between two metal electrodes) fabricated and measured in TUWien. The results are shown in Fig. III. It reports experimental data about the charge on the capacitor plate (Q), which is the quantity actually measured and the polarization, which was computed according to: 𝑄=𝑃+&𝜀&𝜀'(𝐹 where 𝜀'( is the dielectric background constant of the ferroelectric material. For HZO, it is in between 25 and 35 6 ; within this range, the parameter is often used as a fitting parameter. For the curve in Fig. 3, a value of 35 was selected because subtracting 𝜀&𝜀'(𝐹 to 𝑄 a flat polarization curve is found for very high (absolute) values of electric field: this is consistent with the Preisach-based model. In simulations, the charge and polarization quantities can be independently printed out and extracted. The simulations of the HZO capacitor were performed in Sentaurus Device using the parameters 𝐹"=&1&MV/cm , 𝑃!=23 μC/cm2 and 𝑃%= &21.5& μC/cm2. The model provides a very good agreement with experimental results. The model employing the Ginzburg–Landau–Khalatnikov equation 7 , 8 is based on the Landau theory for ferroelectric materials. In the Landau theory, the ferroelectric material is described 6 J. Muller, et al., ”Ferroelectric Hafnium Oxide Based Materials and Devices: Assessment of Current Status and Future Prospects”, ECS J. Solid State Sci. Technol., vol. 4, no. 30, 2015. 7 M. E. Lines, et al,. “Principles and Applications of Ferroelectric and Related Materials”, Clarendon Press, Oxford 1977 8 P. Lenarczyk, et al., “Physical Modeling of Ferroelectric Field-Effect Transistors in the Negative Capacitance Regime”, International Conference on Simulation of Semiconductor Processes and Devices 2016 Figure III – Measured (symbols) and simulated (solid lines) charge (Q) and polarization (P) of a parallel plate HZO capacitor, showing very good agreement between experiments and the Preisach-based model. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 7 through a proper thermodynamic free energy 9 . In Sentarus TCAD, the free energy of a ferroelectric material occupying a region is written as 10 : 𝐺= BC 𝛼)𝑃) *+𝛽)𝑃) ++𝛾)𝑃) ,+𝑔)- H 𝜕𝑃) 𝜕𝑥K *−𝐸)𝑃)+𝜀&𝜀% 2𝐸)𝐸) M .&𝑑Ω . / The first three terms represent the Landau free energy functional (energy stored due to polarization) and the fourth term accounts for the energy caused by nonuniform polarization and represents the energetic cost of forming domain walls. In the Ginzburg–Landau– Khalatnikov framework, the governing equation of polarization evolution can be obtained as a gradient flow associated with the free energy functional10: 𝜌𝑑𝑃) 𝑑𝑡 +∇0!𝐺=0 From the two equations above, the following is found: 𝜌𝑑𝑃) 𝑑𝑡 +2𝛼)𝑃)+4𝛽)𝑃) 1+6𝛾)𝑃) 2−2𝑔)- 𝜕*𝑃) 𝜕𝑥- *−𝐸)=0 where 𝑃) and 𝐸) denote the Cartesian components (i,j = x, y, z) of the polarization vector and the electric field vector, respectively. Following a common practice, we assume that HZO shows a polarization aligned along the applied electric field direction (see Fig. II.a). Thus, we use only one Cartesian component. The Landau coefficients a, b, g have been calibrated to fit the polarization versus electric field measurements of the HZO capacitor already shown above. The results of TCAD simulations, compared to experimental data are shown in Fig. IV. It has to be noted that in this case the dielectric background constant of the ferroelectric material used to compute the polarization from the measured charge data was 26. This value, used also in the corresponding simulations, was chosen so as to obtain a small slope in the polarization curve at high (absolute) electric field: in fact, by using the Ginzburg–Landau–Khalatnikov equation, the polarization is not as completely flat for field values larger than the coercive field, but it features a small increase with electric field. The simulated results have been obtained using the following parameters: a&=&-3.22·1010&cm/F," b&=&-2.34·1019$ cm5/(FC2)," g=8.39·1028$ cm3/(FC4)." The simulated curves present a sharp polarization switching when the electric field reaches the coercive field. This is due to the fact that the ferroelectric layer was described using a single region with constant a, b, g!parameters, leading to the same coercive field for the entire ferroelectric layer. It has to be noted that in this picture the ferroelectric layer can still divide in different ferroelectric domains, for example when the ferroelectric layer sits on a dielectric layer and an inhomogeneous electric field triggers the formation of ferroelectric domains. However, this picture featuring a single coercive field cannot accurately reproduce the fairly gradual switching seen in experiments, which is given by the fact that HfO2-based ferroelectric materials are polycrystalline, where each grain may have a somewhat different polarization reversal, namely different coercive fields and remanent polarization. TEM and SEM images 9 K. Majumdar, et al., “Revisiting the Theory of Ferroelectric Negative Capacitance,” IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2043–2049, May 2016. doi: 10.1109/TED. 2016.2544813 10 Sentaurus Device of Synopsys TCAD, User Guide, V-2023.12 Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 8 evidence grains that have a fairly uniform polarization, meaning that each polycrystalline grain corresponds to a ferroelectric domain 11 , 12 , 13 . It is also assumed that the polarization in one grain does not influence the polarization in the adjacent grains, so that the different grains are coupled only by the electrostatics. It is thus possible to model a ferroelectric layer featuring multidomains by dividing the region in ferroelectric boxes connected by non-ferroelectric spacers 14 , as illustrated in Fig. V. Each box represents a ferroelectric domain, in which the polarization is constant: this is obtained by penalizing the formation of domain walls inside each box, i.e. by setting the parameter 𝑔)- to a high value. Similarly to the Preisach theory, each domain can be assigned a different coercive field (by changing the a, b, g parameters of the domain) in order to obtain a smooth transition between the two polarization states in the polarization versus electric field curve. The results of the simulations done using such a strategy are reported in Fig. VI. The a, b, g parameters have been obtained to have a Gaussian distribution of coercive fields with a mean of 1&MV/cm and a standard deviation of 0.4 &MV/cm . The simulated polarization versus electric field shows a very good agreement with the experimental data. 11 H. Mulaosmanovic et al., ”Switching Kinetics in Nanoscale Hafnium Oxide Based Ferroelectric Field-Effect Transistors”, ACS Appl. Mater. Interfaces, 9, 3792-3798, 2017 12 M. H. Park et al., ”Surface and grain boundary energy as the key enabler of ferroelectricity in nanoscale hafnia-zirconia: a comparison of model and experiment”, Nanoscale, 9, 9973, 2017 13 F. P. G. Fengler et al., ”Domain Pinning: Comparison of Hafnia and PZT Based Ferroelectrics”, Adv. Electron. Mater., 3, 1600505, 2017 14 D. Lizzit, et al., “Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects” ESSDERC 2022 - IEEE European Solid-State Device Research Conference (ESSDERC) Figure IV - Measured (symbols) and simulated (solid lines) charge (Q) and polarization (P) of a parallel plate HZO capacitor. Simulations are done employing the Ginzburg–Landau–Khalatnikov equation (and one single region with uniform a, b, g parameters). Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 9 b. Simulation of Schottky junctions In Sentaurus Device it is possible to simulate a Schottky barrier by imposing a specific boundary condition at a metal/semiconductor interface or at an electrode contacting a Figure V – Ferroelectric layer divided in ferroelectric boxes connected by non-ferroelectric spacers: such structure is constructed and simulated in TCAD to describe the polycrystalline nature of HfO2-based ferroelectric material and to represent the smooth transition in the polarization – electric field curve measured experimentally. Figure VI - Measured (symbols) and simulated (solid lines) charge (Q) and polarization (P) of a parallel plate HZO capacitor. Simulations are done employing the Ginzburg–Landau–Khalatnikov equation and dividing the ferroelectric layer in multidomains with different a, b, g parameters. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 16 electrons and holes as in this case, the Schottky contact resistance has a large impact on the onstate current of the transistor and the drain current can be modulated by several order of magnitude. Preliminary simulations have been carried out to study the behavior of the Schottky junctions and the polarization-induced modulation of their barrier. Results of such preliminary simulations are reported in Appendix A. Table I. Material and thicknesses of regions in simulated Fe-SBFETs. Material Layer thickness Ferroelectric (FE) Hf0.5 Zr0.5O2 (HZO) - ferroelectric orthorhombic phase 8.5 nm Non-FE oxide Hf0.5 Zr0.5O2 (HZO) – non ferroelectric phase 8.5 nm Interface oxide SiO2 0.9 nm Semiconductor Silicon 20 nm Back Oxide SiO2 50 nm Table II. Parameters used for interface traps at the HZO-SiO2 interface. Acceptor-type traps Donor-type traps Center of Gaussian energy distribution 1.85 eV below the conduction band of HZO 3.17 eV below conduction band of HZO Standard deviation of Gaussian energy distribution 0.04 eV 0.04 eV Concentration 1014 cm-2 1014 cm-2 Electron/hole effective mass 0.8 m0 0.8 m0 Trap volume 10-12 μm3 10-12 μm3 Results of simulations of Fe-SBFETs are reported in the next section. Transient simulations have been performed in Sentaurus TCAD. The structure is biased by applying time-varying voltages at the electrodes. A work function of 4.5 eV is used for the program gates or front gate and back gate, whereas a Schottky barrier of 0.6 eV is chosen for the source and drain electrodes, as detailed above. The ferroelectric polarization is first set by applying a write voltage pulse, after a first reset pulse used to start from a known polarization state. The reset and write pulses are applied at the program gates or at the single gate electrode, depending on the type of structure under test. During the reset and write, the back gate, drain and source electrodes are kept at 0 V. After the write pulse, the drain current of the Fe-SBFET is read by applying a linear sweep at the gate voltage, or back gate voltage for the structures employing program gates and back gate. During the read operation, the drain-source voltage is kept at 0.5 V. In particular, the drain contact is biased at 0.25 V and the source contact is biased at -0.25 V, following the bias scheme used in this work 29 . 29 D. Nazzari D, et al., ACS Appl Mater Interfaces. 2025 Feb 19;17(7):10784-10791, doi: 10.1021/acsami.4c16400 Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 17 3. Simulation results This section will present the simulation results of the different TCAD setups regarding the structure in Fig. 1a, i.e the one with the ferroelectric only on top of the Schottky junctions, with a back gate to perform the read operation. The structure is firstly biased using the bias scheme in Fig. 3 to set the polarization state. The voltage pulses are applied at the program gates and the drain, source and back electrodes are kept at 0 V. Then, a linear voltage sweep to the back gate is applied while applying 0.25 V to the drain and -0.25 V to the source, as explained in the previous section (the program gates are at 0 V). First of all, the results obtained using the 2D TCAD setup with Preisach-based model are reported. The average polarization as a function of time during the reset and the set pulse is reported in Fig. 4 (the polarization is aligned along the x-direction in Fig. 2). Increasing the pulse height from 0.5 V to 5 V, it is possible to obtain a gradual modulation of the polarization in a wide range of values. The polarization in Fig. 4 is the average polarization in the whole ferroelectric HZO layer. Fig. 5.a shows that, as expected, the polarization in the HZO region above the source Schottky junction is the same as the polarization in the HZO region above the drain Schottky junction. Fig. 5.b reports the charge trapped at the interface between HZO and SiO2, calculated considering the charge of both electrons and holes trapped at the interface. The traps are charged during the gate voltage pulses. The positive trapped charge, given by the occupation of the donor-type traps, helps to stabilize the negative polarization when the program gate voltage goes back to zero after the reset pulse. The negative trapped charge, given by the occupation of the acceptor-type traps, stabilizes the positive polarization after the write pulse. The trapped charge partially compensates the polarization and the resulting attenuated polarization modulates the Schottky junctions at source and drain, in particular the barrier width and so the tunneling through the barrier, thus modulating the drain current in the Fe-SBFET. The drain current as a function of the back gate voltage is plotted in Fig. 6 for different write voltage pulse heights. For write voltages that result in a negative polarization, the Fe-SBFET behaves as a p-type FET and the drain current is high for negative back gate voltages. The polarization in fact induces a band bending in the semiconductor region close to the Schottky contacts that favors the tunneling of holes and blocks electrons. For increasing write voltages, the polarization increases and eventually becomes positive. Plots of the band diagram highlighting polarization-induced band bending are reported in Appendix A. When the polarization is almost 0, namely for a write voltage of Figure 4. Average ferroelectric polarization as a function of time during reset and write operations (2D setup, Preisach-based model). Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 18 1.5 V, the Fe-SBFET has always a low current as the Schottky barrier is not modulated, and so neither the tunneling of holes nor the tunneling of electrons can be enhanced. For positive a) b) Figure 5. a) Ferroelectric polarization of the HZO regions on top of the source and drain Schottky contact as a function of time during reset and write operations (2D setup, Preisach-based model); b) Charge in the traps at the interface between HZO and SiO2. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 19 polarization values, the Fe-SBFET behaves as an n-type FET and the drain current increases increasing the write voltage and so the positive polarization value. Fig. 7 reports the comparison of the results obtained with the 2D and 3D TCAD setup, using the Preisach-based model. As it can be seen in Fig. 7.a, the average polarization in the HZO layer obtained performing 2D simulations is the same as the one obtained with 3D simulations (width of 20 nm). As a consequence, also the drain current versus back gate voltage curves are very similar in the 2D and 3D case. This outcome was expected and it is related to the use of the Preisach-based model. In fact, the latter model corresponds to a macroscopic hysteretic system composed by a superposition of simple hysteresis units, so it already considers an averaged value of the polarization over several ferroelectric domains. In the Preisach-based model, the polarization depends on the electric field and on the polarization history of the material. Thus, since the 3D structure is homogeneous along the z-axis, the same polarization as in the 2D case is found for the same applied voltages. However, the simulation time of the 3D case is much longer, about 20 to 50 times longer than the 2D case. Figure 6. Drain current of the Fe-SBFET as a function of the back gate voltage for different write voltage pulse heights. The read operation is performed with a back gate voltage sweep, with program gates at 0 V, drain at 0.25 V and source at -0.25 V, after the end of the write operation (2D setup, Preisach-based model). Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 20 The results obtained with the 2D TCAD setup employing the Landau-based model are reported in Fig. 8 and Fig. 9. The structure is simulated in two fashions, featuring either ferroelectric domains with a boundary between two domains placed in correspondence of the Schottky a) b) Figure 7. Comparison between 2D and 3D setup using the Preisach-based model: a) average polarization as a function of time during reset and set time; b) read operation: drain current as a function of the back gate voltage. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 21 junction (structure a) or with a single ferroelectric domain placed on top of the Schottky junction (structure b). The domains have a lateral size of 7 to 10 nm, in the range of experimentally reported values 30 . For this reason, in a 2D structure only very few domains can be inserted in the ferroelectric region (3 or 4 in each ferroelectric region, see Fig. 8). The result is a very limited multidomain gradual switching of the polarization that can have only few levels, due to the insufficient number of domains. This type of simulated structure is thus not representative of the fabricated devices, where a higher number of domains are usually found due to the extension of the device in the third dimension, which is considered homogeneous in 2D simulations. Nevertheless, structures featuring very few ferroelectric domains have been experimentally observed in highly scaled FeFETs 31 . In addition, in the Fe-SBFET with the ferroelectric layer only on top of the Schottky junctions, the ferroelectric region that can modulate the Schottky barrier is only the part of the ferroelectric close to the junction lying on top of the semiconductor. In structure a, the drain current is thus affected only by two domains while in structure b four domains can affect the read-out current (see FE domains in red in Fig. 8, top panels). As it can be seen in Fig. 8, for structure a we thus have four possible configurations corresponding to the two relevant domains having both a positive polarization, both a negative polarization, or finally having opposite polarizations. In simulations, by changing the pulse height from 0.5 V to 2 V, three different configurations have been obtained, as it can be seen in Fig. 8, middle panel. Consequently, only three different drain current versus back gate voltage characteristics have been found, reported in Fig. 9.a, even though five different pulse heights have been tested. For pulse heights of 0.5 V and 0.75 V, the relevant domains have negative polarization in both cases, and so the same p-type drain current versus back gate voltage is found. The same applies for pulse heights of 1.5 V and 2 V, but with positive polarization and an n-type read-out characteristic. For the pulse height of 1 V, the negative polarization at source favors the tunneling of holes and the positive polarization at drain favors the tunneling of electrons, hence, the Fe-SBFET has a high value of current for both positive and negative back gate voltage due to this ambipolar behavior. In structure b we would have more configurations given the four domains involved. However, in the read-out operation (see Fig. 9.b) we see that we could obtain only two types of drain current versus back gate voltage characteristics: n-type or always off. The n-type is obtained when all the four domains are positive. In all the other cases there is one of the two domains on the source side having negative polarization, thus blocking the tunneling of electrons, and one of the two domains on the drain side with positive polarization, thus blocking the tunneling of holes. Different domains with different distribution of coercive voltages could result in different polarization patterns and the p-type of ambipolar characteristics could be obtained. However, also in this case very few levels in the drain current can be obtained, as the two adjacent domains either have the same polarization, so the same effect, or opposite polarization, where one effect contrast the other. For these reasons, the 2D simulations employing the Landau-based model have limited application for modeling of fabricated Fe-SBFETs and will not be further used. 30 H. Mulaosmanovic, J. Ocker, S. Müller, U. Schroeder, J. Müller, P. Polakowski et al., “Switching Kinetics in Nanoscale Hafnium Oxide Based Ferroelectric Field-Effect Transistors”, ACS Applied Materials & Interfaces, vol. 9, no. 4, 2017. 31 H. Mulaosmanovic, E. T. Breyer, S. Dünkel, S. Beyer, T. Mikolajick, and S. Slesazeck, ‘‘Ferroelectric fieldeffect transistors based on HfO2: a review,’’ Nanotechnology, vol. 32, no. 50, p. 502002, 2021. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 22 Structure a Structure b Figure 8. Polarization after write pulses with different heights in two structures with different positioning of the FE domains with respect to the Schottky junctions (2D setup, Landau-based model). Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 23 The Landau-based model can be more effectively implemented in 3D simulations, so to obtain a high enough number of ferroelectric domains. Simulations using the 3D TCAD setup employing the Landau-based model have been carried out using the same bias scheme discussed before. Fig. 10 reports the polarization obtained in the HZO layer after the write pulse, using different pulse heights. As done for the 2D structure, also in the 3D case the simulations are performed for two slightly different structures featuring a different alignment between the Schottky junction and the ferroelectric domains boundaries. a) b) Figure 9. Drain current as a function of back gate voltage read out after the end of the write pulse at different voltage heights: a) for the structure a in Fig. 8 and b) for the structure b in Fig. 8 (2D setup, Landau-based model). Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 24 It can be seen how the gradual switching, and so a multilevel operation, can be obtained by dividing the ferroelectric layer in several independent homogeneous domains with a Gaussian distribution of coercive fields. By increasing the voltage of the write pulses, the number of Figure 10. Polarization of the ferroelectric domains in the HZO layer after write pulses at different heights (3D setup, Landau-based model). The structure a and the structure b differ in the alignment between the Schottky junction and the ferroelectric domains boundaries. Figure 11. Average polarization in the HZO region during reset and write pulses at different heights (3D setup, Landau-based model) in structure a and structure b (see Fig. 10). Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 25 domains that switches from a negative polarization (obtained after the reset pulse) to a positive polarization increases. Even though the total number of domains is higher with respect to the Figure 13. Current density for a back gate voltage of – 5 V (3D setup, Landau-based model). Figure 12. Drain current versus back gate voltage: read operation after write pulses at different heights for structure a and b (3D setup, Landau-based model). Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 32 Figure 20. Simulated characteristics without any traps at the Si/back oxide interface and without fixed charge in the non-ferroelectric HZO (dashed line) and with acceptor-type traps and donor-type traps at the Si/back oxide interface (solid line). The parameters of traps used in simulations are reported in Table III. a) b) Figure 21. Simulated characteristics with acceptor-type traps and donor-type traps at the Si/back oxide interface: a) with and without fixed charges at the Si/back oxide interface (-1012 cm-2) and b) with fixed charges at the Si/back oxide interface and with and without fixed charges in the bulk of the non-ferroelectric HZO (-1.2×1018 cm-3). The parameters of traps used in simulations are reported in Table III. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 33 Table III. Calibrated parameters of traps used to fit experimental transfer characteristics. Traps at the HZO-SiO2 interface Acceptor-type traps Donor-type traps Center of Gaussian energy distribution 1.85 eV below the conduction band of HZO 3.17 eV below conduction band of HZO Standard deviation of Gaussian energy distribution 0.04 eV 0.04 eV Concentration 8 × 1014 cm-2 1014 cm-2 Traps at the Si/back oxide interface Acceptor-type traps Donor-type traps Type of energy distribution uniform uniform Energy range 0-0.5 eV below the conduction band of silicon 0-0.6 eV above the valence band of silicon Concentration 2.25 × 1012 cm-2 7.2 × 1012 cm-2 Fixed charge -1012 cm-2 Traps in the bulk of the non-ferroelectric HZO Fixed charge -1.2×1018 cm-3 Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 34 A. Appendix Preliminary simulations have been carried out to study the behavior of the Schottky junctions and the polarization-induced modulation of their barrier. The simulated structure is shown in Fig. A1. For this study, the Preisach-based model has been selected for the ferroelectric layer due to computational reasons. A concentration of 1•1014 cm−2 has been used for acceptors and holes at HZO/SiO2 interface. Such traps exchange electrons and holes via a non-local tunneling mechanisms across the SiO2, accounting for both elastic and multi-phonon assisted tunneling (SiO2 tunneling electron/hole effective mass of 0.8 m0 and a trap volume of 10-12 μm3). Simulations have been performed by applying voltage pulses at the program gate (the two gates on top of the Schottky junctions are short circuited together), more specifically a reset pulse at a fixed voltage ( ± 5 V) and a set pulse at different heights. The source, drain and back gate contact are at 0 V, if not specified differently. Figure A1 – Simulated Fe-SBFET structure. Figure A2 – Simulated polarization in the HZO ferroelectric layer (averaged) as a function of time, for different set pulse voltages, using the pulsing scheme described in Fig. 14. The reset pulse height is – 5 V. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 35 Simulated results of the average polarization in the HZO ferroelectric region as a function of time are reported in Fig. A2, using a negative reset pulse (- 5V) and for different set pulse height. It can be seen how partial polarization switching is obtained for pulses at different voltages. It has to be noted that the polarization is not constant in the entire ferroelectric region, as shown in Fig. A3: the ferroelectric layer sandwiched between two metal contacts has a higher polarization with respect to the region placed on top of the semiconductor, where part of the electrostatic potential drops in the semiconductor. Fig. A4 compares the average polarization in the ferroelectric layer to the average polarization in the ferroelectric region on top of the metal source contact and the average polarization of the region on the semiconductor. Fig. A5(a.b.c.) shows the simulated conduction and valence band along the cutline C1, in the silicon layer just below the top gate, shown in Fig. A5.a. The band diagrams are plotted for the structure after the reset pulse at – 5 V (at gate voltage of 0 V) and after the set pulse at 5 V (at gate voltage of 0 V). It can be seen that, after the reset pulse inducing a negative polarization, the Schottky barrier has a shape which favors tunneling of holes and blocks tunneling of electrons: namely the Fe-SBFET works as a p-type FET. After the set pulse the polarization is positive, instead, and the band bending is such that tunneling of electrons is allowed: namely Figure A3 – Results of the simulated polarization, showing the higher value of the stabilized polarization in the HZO region above the metal contact. Simulations refer to the structure at a gate voltage equal to 0 V (as for drain, source, back gate voltage), after the reset pulse and a set pulse of 3 V (left) and 5 V (right). Figure A4 - Simulated polarization in different region of the HZO ferroelectric layer (above the metal contact, above the semiconductor region, averaged in the full ferroelectric HZO region) as a function of time, for different set pulse voltages, using the pulsing scheme described in Fig. 14. The reset pulse height is – 5V. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 36 the Fe-SBFET works as an n-type FET. Fig. A6 shows the band diagram after set pulses at different heights (always computed at gate voltage of 0 V): the width of the Schottky barrier becomes smaller with increasing pulse height, thus tunneling of electrons becomes more effective. The resulting drain current, for a gate voltage of 0 V, back gate voltage of 4 V and drain-source voltage of 0.5 V, as a function of set pulse voltage is plotted in Fig. A7. It can be a) b) Figure A5.a – Conduction band Ec and valence band Ev (b) along the cutline C1 (a) in the silicon layer. Magenta and blue refer to the structure after the reset pulse (gate voltage of 0 V), whereas red and green refers to the structure after reset and set pulse at 5 V (gate voltage of 0 V). Drain-source voltage is set to 0 V and back gate voltage is set to 0 V. Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 37 seen that, by varying the set pulse between 1 V and 5 V, it is possible to obtain a variation of 6 order of magnitude in the drain current, which is consistent with experimental results33,35. FigureA5.b – Conduction band Ec and valence band Ev along the cutline C1 (Fig. A5.a) in the silicon layer after reset (a) and set (b). Drain-source voltage is set to 0.5 V and back gate voltage is set to 0 V. V program gate vs time Reset -5 V V program gate vs time Reset -5 V Set 5 V a) b) Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 38 Figure A5.c – Conduction band Ec and valence band Ev along the cutline C1 (Fig. A5.a) in the silicon layer after reset (a) and set (b). Drain-source voltage is set to 0.5 V and back gate voltage is set to 5 V. V program gate vs time Reset -5 V V program gate vs time Reset -5 V Set 5 V a) b) Tutorial: TCAD simulation of Fe-SBFET EASIFeT - ID: 101108023 Marie Skłodowska-Curie Actions (MSCA) 39 Figure A6 - Conduction band Ec and valence band Ev along the cutline C1 (Fig. A5.a) in the silicon layer (gate voltage of 0 V) for different set pulse heights, i.e. different polarization states in the ferroelectric HZO layer. Figure A7 – Simulated drain current (computed at gate voltage = 0V, back gate voltage = 4 V, drainsource voltage = 0.5 V) as a function of set pulse voltage (applied after reset pulse at -5 V).