Static and Dynamic Characterization of a Solid-State Multi-Terminal Selector Switch

Static and Dynamic Characterization of a Solid-State Multi-Terminal Selector Switch Theofilos Moraitis Department of Electrical and Computer Engineering University of Patras Patras, Greece [email protected] Georgios Kampitsis Department of Electrical and Computer Engineering University of Patras Patras, Greece [email protected] Abstract—To meet the ever-increasing demand for energy dense, compact and lightweight power inverters, a fundamentally different approach must be taken in energy conversion. Inspired by the signal-level digital to analog conversion, the goal of this work is to introduce and demonstrate a solid-state multi-terminal selector switch, capable of switching between different voltages via a single reference electrode, practically minimizing the signal and power isolation requirements that plague today’s multi-level inverter structures and thus opening the road for truly N-level capable and scalable power converters. Index Terms—4-quadrant switches, bidirectional switches, dynamic characterization, solid-state relays, static characterization I. INTRODUCTION As the world is marching towards decarbonization and climate neutrality [1], the need for efficient, compact and lightweight power converters is ever growing: these power electronics converters serve as the backbone of energy conversion in both the increasingly electrified transportation sector, as well as the power generation sector from renewable energy sources. In combination with the already established presence of power electronics converters in the industrial sector (i.e., motor drives), it is evident that the evolution of these sectors is inherently intertwined with the advancements in power electronics infrastructure. In modern power electronics converters, and especially inverters, it is well known that the major bottleneck in terms of both power density and compactness, is the need for large and heavy energy storage elements, most notably magnetics, to filter out the high frequency harmonics generated by the switching converter. To minimize the size of the aforementioned filters, a traditional strategy is to raise the switching frequency of the semiconductor devices used in such converters, with the drawback of lower efficiency due to the higher switching losses. In an attempt to lower these losses, wide band-gap (WBG) semiconductors, such as gallium nitride (GaN) high-electron mobility transistors (HEMTs) and silicon carbide (SiC) MOSFETs and Schottky diodes, have Funded by the European Union (ERC grant: ENRICH, Grant Agreement 101115709, DOI 10.3030/101115709). Views and opinions expressed are however, those of the authors only and do not necessarily reflect those of the European Union or the European Research Council. Neither the European Union nor the granting authority can be held responsible for them. been utilized. These devices exhibit lower conduction and switching losses than their silicon (Si) counterparts [2]–[4], thus enabling operation at much higher frequencies. Nevertheless, hot-swapping WBG semiconductors can only have a marginal gain in the miniaturization of the overall system: the relationship between the switching frequency and the magnetics’ size is not constant, exhibiting large diminishing returns above a certain frequency, typically in the range of a few hundred kHz. [5]. Furthermore, hot-swapping WBG semiconductors in conventional converter structures can cause excess electromagnetic interference (EMI): since these devices switch much faster than Si, the dv/dt and di/dt during the switching transients can noticeably increase the EMI emissions [6], [7]. In turn, larger filters are required to comply with commercial standards, leading to a reduction in the power density of the system. The conventional solution to the aforementioned challenge is the utilization of multilevel inverter (MLI) topologies, such as those shown in Fig. 1. With these structures, less filtering is required, as the desired sinusoidal output voltage is approximated better due to the existence of more than two voltage levels. Additionally, there is a potential efficiency gain when compared to the traditional H-bridge inverters: not only are the switching losses lower due to the divided DC bus voltage, but also the ability to use lower-voltage rated device means that the conduction losses can also be reduced [8]–[10]. a b c a b c (a) (b) Fig. 1. Three-level 3Φ MLI structures (a) flying capacitor and (b) neutralpoint clamped. 650 V 80 mΩ GaN HEMT G.P. Gate Driver Fig. 2. Size comparison between a GaN HEMT and a conventional gate driver circuit (external). However, conventional MLI topologies are limited in terms of the power density that can be achieved, due to the steep power and signal isolation requirements in order increase the output voltage levels. In the cases of both the flying capacitor and neutral point clamped structures, displayed in Fig. 1 (a) and (b) respectively, there is a need for 10 separate gate references (as shown with orange dots: 4 per phase and 10 in total for a 3Φ system, since the DCis a common node for all phase legs) to produce a 3-level voltage output. Since the gate driver circuitry can span area and volume multiple times that of the power semiconductors themselves, as is showcased in Fig. 2, it is evident that there is a ceiling in terms of output voltage levels, due to the impracticality of the implementation. To achieve true N-level output voltage generation without massive requirements in signal and power isolation, a different approach to DC/AC power conversion is necessary. Inspired by the signal level digital to analog converters (DAC), shown in Fig. 3 (a), the envisioned structure can switch between multiple voltage levels with a solid-state, multi-terminal selector switch (MTSS), via a single reference electrode. This approach is visualized in 3 (b), while the proposed implementation for the MTSS device in this paper is shown in Fig. 3 (c). It is comprised of an n-channel device, a p-channel device (in this case, MOSFETs), as well as two diodes in series with the FETs. The nand p-channel branches are responsible for the Res. Ladder R R R R R R Rcal. DAC Reg. Digital I/O in. volt. ref. vn B Bvn-1 vn-2 v2 v1 v0 vac MTSS (a) (b) GΝ GP Di (c) S Dp DnMn Mp Fig. 3. (a) Signal level DAC, (b) DAC-inspired MLI concept and (c) proposed configuration for the MTSS. forward and reverse conduction, respectively. To the best of the authors’ knowledge, this bidirectional switch topology has only appeared in [11], where the focus was to monolithically integrate the n-branch. Therefore, the purpose of this paper is to evaluate the proposed MTSS, in terms of its static and dynamic characteristics, in order to showcase its potential utilization in power electronics converters. The paper is structured as follows. Section II discusses in detail the MTSS operating principles and gate driving scheme. Section III features the experimental demonstration of the proposed switch, which is done via static and dynamic characterization, as well as through a power electronics application (AC chopping). Finally, the paper is concluded in Section IV, with a quick summary of the work presented, as well as an outline for its future expansion. II. MTSS OPERATION PRINCIPLES The detailed structure of the MTSS concept, including the voltages across its control and power terminals, is shown in Fig. 4 (a), while its proposed, condensed schematic symbol is displayed in Fig. 4 (b). As can be seen from Fig. 4 (c), if a positive gate pulse is applied to the gate of the n-channel FET, the device acts as a diode, with its ”anode” connected to the ”drain” of the device, whilst its ”cathode” acts as the ”source”. If a negative gate pulse is applied to the gate of the pchannel FET, the diode is then reversed. It is worth noting that both the FETs are enhancement-mode transistors: a positive and negative gate bias have to be applied in order for the nchannel and p-channel devices to conduct, respectively. If the two FETs are turned on simultaneously, then the device acts as a true bidirectional switch. The unique characteristic of this realization is that both gate signals are referenced to a single potential, which is not the case for other two-gate four-quadrant switches, such as reverse blocking IGBTs [12], bidirectional GaN HEMTs [13] or common-drain FETs [14]. Finally, unlike conventional single gate bidirectional switches, such as the common-source FETs [15] or the switch embedded diode bridge [16], the reference electrode is not floating for each switch. Instead, multiple MTSS devices can be controlled via the same reference potential, thus eliminating the large signal and power isolation requirements. DS Gp Gn vGpS vGnS vDS (a) GnGp S D (b) vGnS > 0 (c) vGpS = 0 vGnS = 0 vGpS < 0 vGnS > 0 vGpS < 0 Dp Dn Mp Mn Fig. 4. (a) Detailed schematic symbol for the proposed MTSS device, (b) condensed symbol of the MTSS and (c) MTSS operation for various gatesource voltages. Regarding the practical gate driving of the MTSS, two options are available, the first being to electrically connect the gates of the n-channel and p-channel FETs. With this method, only a single driver IC is required to turn on and off the MTSS. This is possible due to the fact the maximum gatesource voltage, vGS, is typically ±20 V for both categories of FETs. The second, and recommended gate driving option is to keep the gate terminals of the FETs separate. Not only does this allow for a more flexible control of the bidirectional switch, but also greatly reduces the gate driving power losses. It is well known that an estimation for the gate driving losses of a FET can be calculated as shown in (1): PD=QG·VDD ·fsw (1) Where QGis the total gate charge, VDD is the voltage supply of the driver, and fsw is the switching frequency. By keeping the two gates separate, the driving voltage VDD, is half the voltage required to drive both gates at once, since the supply would be unipolar instead of bipolar. More importantly, by electrically connecting the gates, the total gate charge of the device would be the sum of the gate charges of the n-channel and p-channel FETs. Therefore, the transients of the device would slow down, causing an increase in switching losses. Thus, it is recommended to keep the gates of the p-channel and n-channel FETs separate for the best switching performance. III. EXPERIMENTAL VERIFICATION This section describes the static and dynamic characterization setups, as well as their respective experimental results. The static characterization includes I−Voutput characteristics, as well as the leakage current. The dynamic characterization provides hard switching information for the device, such as rise trand fall tftimes, turn-on Eon and turn-off Eoff losses as well as voltage dv/dt and current di/dt slew rates. The section is concluded with a demonstration of the proposed switch in a power electronics application, namely AC chopping. To host the proposed MTSS device, a custom host-PCB was developed, the schematic and implementation of which are shown in Fig. 5 (a) and (b), respectively. The top-side of the PCB hosts the primary semiconductor devices, the driving D (a) (b) D S Rg,on Rg,offRg,offRg,off -12V +12V S N PGD GP GN GD S GD GN GP Fig. 5. (a) Detailed schematic of the MTSS host-PCB and (b) the implementation. circuitry, including a split-output gate driver IC, the turn-off and turn-on resistors and the decoupling capacitors for the supply voltages, as well as MMCX connectors for high-fidelity voltage measurements. The backside consists of an exposedcopper surface, allowing for elevated temperature testing of the MTSS via a custom-hot plate, which can be screwed in place. The surrounding devices of the MTSS are bypassed for the static characterization and are only used for the extraction of the dynamic characteristics. A list of the primary components with their respective key parameters is available in Table I. A. Static Characterization The static characterization setup is shown in Fig. 6. It is based on a B1505A power device analyzer / curve tracer from Keysight, alongside its ultra-high current (UHC) expander. The testing was conducted via an intermediary board, between the MTSS module and the UHC expander, due to its unconventional footprint. The full spectrum of the static tests conducted on the MTSS device is shown in Fig. 7. It is comprised of two tests: firstly, the drain-source equivalent breakdown voltage, depicted in Fig. 7 (a), and the I-V output curve of the device, depicted in Fig. 7 (b) and (c). Since the breakdown drain source (BVDSS) experiment essentially tests the n-channel and p-channel FET breakdown voltage, it is expected the leakage current starts rising over ±200 V. Indeed, that is exactly what is observed in Fig. 7 (a). At the rated FET voltage of +200 V, the n-branch of the MTSS exhibits a leakage current of just 10 µA. At -200 V, the p-branch is slightly leakier, at just over 100 µA. The second test is performed to extract the I-V output characteristics of the device for case temperatures of Tc=25 ◦C and Tc=105 ◦C, shown in Fig. 7 (b) and (c), respectively. The device temperature was raised via an external heating plate, screwed on the back side of the MTSS host-PCB, until TABLE I MTSS HOST PCB PRIMARY COMPONENT LIST Component Mfr. Part Number Key Characteristics N-channel FET STB30NF20L 200 V, 30 A (Tc=25 ◦C) P-channel FET IXTA26P20P 200 V, 26 A (Tc=25 ◦C) Si Schottky Diode VB30200C-E3/4W 200 V, 30 A (Tc=25 ◦C) Gate Driver IC UCC27511DBVR 4 A/8 A peak source/sink Force Connections Sense Connections B1505A Main Frame UHC Expander Fig. 6. Static characterization setup, comprised of the B1505A power device analyzer and the UHC expander. Voltage [V] (a) -300 -100 100 300 Leakage Current [μA] -600 -300 0 300 600 Voltage [V] (b) -10 -5 0 5 10 Current [A] -50 -25 0 25 50 4.6 4.8 5 43 44 45 -6.6 -6.3 -6 -32 -30 -28 Voltage [V] (c) -10 -5 0 5 10 Current [A] -50 -25 0 25 50 5.1 5.4 5.7 34 35 36 -7.2 -7 -6.8 -24 -23 -22 ±3 V ±4 V ±5 V ±6 V ±7 V ±8 V ±9 V ±10 V p-branch p-branch n-branch n-branch Fig. 7. Complete static characterization (a) drain-source voltage breakdown, (b) I-V output characteristics for Tc= 25 ◦Cand (c) I-V output characteristics for Tc= 105 ◦C. thermal equilibrium was reached. Whereas the test conducted in 25 ◦Cgives a best-case scenario for the forward conduction voltage drop, the 105 ◦Ctest gives a more realistic result, as the power semiconductors in converters rarely operate at such low temperatures. For both the I-V curves, the primary drainsource voltage sweep was limited to 10 V, while the secondary sweep, that being the gate-source voltage, started at ±3 V, and ended at ±10 V, with a step of ±1V. The power pulse width was set to 50 µs, in order to prevent device self-heating during the test procedure. From the resulting curves in Fig. 7 (b) and (c), it can be observed that the conduction characteristics are asymmetrical, even at larger VGS values, despite the devices having similar voltage and current ratings. This is due to the fact that the electron mobility in silicon is larger than the mobility of the holes, which affects the RDS,on. This is also evident in the datasheet of the transistors [17], [18]. Nevertheless, it can be observed that the relationship between the current and the voltage is quasi-ohmic in both first and third quadrants: the diode forward voltage drop is relatively small at only 0.65 V at IF= 15 A [18], and therefore it is the on-state resistance that contributes to the total forward voltage drop at higher currents. As a final note, the combined results of Fig. 7 (a) - (c) successfully showcase the utilization of the proposed MTSS device as a true bidirectional switch (bidirectionally blocking and conducting). B. Dynamic Characterization The next step in evaluating the MTSS device, is to extract its dynamic characteristics. For this purpose, a dynamic evaluation platform was designed, the schematic of which is shown in Fig. 8 (a). This platform is capable of double pulse, overcurrent and short-circuit testing. In this work, only the double pulse testing is reported. The core of the dynamic evaluation setup is a bidirectional half bridge: the capacitor bank, CB, is comprised of 16 polypropylene capacitors with a total capacitance of 75 µF. The lower switch of the bridge is the MTSS, while the upper device is a diode. For the best possible switching behavior, a SiC 600 V, 15 A Schottky diode is used in this work. The implementation of the dynamic characterization setup is shown in Fig. 8 (b). Testing the n-branch of the MTSS device is simply performing a standard double-pulse test, as shown in Fig. 8 (c). Testing the p-branch, however, requires reversing the input voltage, and therefore the diode as well, as shown in Fig. 8 (d). The testing parameters were set to ±160 V, at ±10 A. The load air core inductance was set at 110 µH. The n-channel and p-channel FETs were driven with +12 V/0 V and -12 V/ 0 V for the turn-on and turn-off gate voltages, respectively, with turn-on and turn-off external gate resistors of 5.1 Ω, in all cases. The duration of the first pulse t1was 7 µs, to prevent device self-heating. Finally, the dead time between the two pulses was set just over 4 µs. A B SW CB MTSS Upper Switch input CB output HS switch + – CB in on off – + CB ip on off (a) (b) (c) (d) Fig. 8. Schematic (a) and implementation (b) of the dynamic evaluation board, n-branch (c) and p-branch (d) configurations. t [us] (b) 0 0.2 0.4 0.6 0.8 0 40 80 120 160 0 3 6 9 12 t [us] (a) 0 0.2 0.4 0.6 0.8 VDS [V] 0 40 80 120 160 0 3 6 9 12 t [us] (f) 0 0.2 0.4 0.6 0.8 0 40 80 120 160 0 3 6 9 12 t [us] (e) 0 0.2 0.4 0.6 0.8 VDS [V] 0 40 80 120 160 0 3 6 9 12 t [us] (d) 0 0.2 0.4 0.6 0.8 -160 -120 -80 -40 0 ID [A] -12 -9 -6 -3 0 t [us] (c) 0 0.2 0.4 0.6 0.8 -160 -120 -80 -40 0 -12 -9 -6 -3 0 t [us] (h) 0 0.2 0.4 0.6 0.8 -160 -120 -80 -40 0 ID [A] -12 -9 -6 -3 0 t [us] (g) 0 0.2 0.4 0.6 0.8 -160 -120 -80 -40 0 -12 -9 -6 -3 0 p-branch turn-offp-branch turn-on n-branch turn-offn-branch turn-offn-branch turn-on n-branch turn-on p-branch turn-on p-branch turn-off Fig. 9. MTSS inductive turn-on and turn-off transients for 25 ◦C(a)-(d) and for 105 ◦C(e) - (h). The performed double pulse testing is shown in Fig. 9. The tests were performed for temperatures of Tc=25 ◦Cand Tc =105 ◦C, via a temperature controlled hotplate. The voltage measurement was done via a 200 MHz passive probe, connected to the MTSS host-PCB via an MMCX connector. The current measurement was performed via a 30 MHz Rogowski coil, in order to avoid the additional inductance of a current shunt. Even though this current measurement method provides lower bandwidth, there’s no additional external inductance added to the power loop, which can cause excess ringing [19]. The oscilloscope used had a bandwidth of 200 MHz, and a 12-bit ADC unit. As a final note, before the double pulse testing was conducted the two channels hosting the voltage and current measurements were de-skewed via a low inductance resistor, connected in the place of the load inductor, to accurately measure the switching energies of the device. The voltage and current ringing present in the turn-off and turn-on waveforms are caused by two primary reasons: first and foremost, the DUT is a discrete device proof-of-concept realization. Thus increased parasitics are to be expected. Secondly, due to the flexibility of the evaluation board, some compromises were made in terms of the distance between the switching elements. For example, the upper switch could be physically closer to the DUT. Nevertheless, both the peak voltage and current never exceeded 120% of the nominal testing ratings. The resulting rise trand fall tftimes, the voltage dv/dt and current di/dt slew rates, as well as the turn-off Eoff and turn-on Eon energy are listed in Table 2, for all the experiments conducted, as per the IEC 60747-8 standard [20]. As a reminder, the turn-on and turn-off energies are calculated by (2) and (3), respectively: Eon =ZtV10% tI10% vDS(t)·iD(t)dt (2) Eoff =ZtI10% tV10% vDS(t)·iD(t)dt (3) where tV10% and tI10% are the times at which the voltage and current have dropped to 10% of their nominal test values, respectively. The nand pbranches behaved similarly, with the nbranch exhibiting overall faster characteristics and lower energy losses, which is in agreement with the respective manufacturers’ datasheets. It is important to note that the turn on TABLE II SWITCHING ENERGY AND TIME MEASUREMENTS Branch Measurement Symbol Unit Temperature 25◦C 105◦C n– Turn-on Energy Eon µJ 1.4 1.5 Turn-off Energy Eoff µJ 40.8 37.1 Rise Time trns 26 22 Fall Time tfns 28 22 Voltage Slew Rate (dv/dt)on V/ns 5.61 5.22 (dv/dt)off V/ns 4.02 4.32 Current Slew Rate (di/dt)on A/ns 0.59 0.56 (di/dt)off A/ns 0.51 0.43 p– Turn-on Energy Eon µJ 10.6 10.4 Turn-off Energy Eoff µJ 51.2 55.7 Rise Time trns 45 43 Fall Time tfns 50 42 Voltage Slew Rate (dv/dt)on V/ns 3.07 3.35 (dv/dt)off V/ns 3.56 3.54 Current Slew Rate (di/dt)on A/ns 0.52 0.43 (di/dt)off A/ns 0.42 0.48 losses for both branches are significantly lower than the turn off losses. This is theorized to be caused by the interactions between capacitances of the diode and the FETs, but further research needs to be conducted on this topic. C. AC Chopping The final step to the experimental evaluation of the proposed MTSS device is a demonstrator of its capability to be used in a power electronics application. For this reason, an AC chopping test was performed with the assistance of the dynamic evaluation setup. The diode was disconnected from the board, and in its place, a 100 Ωpower resistor is connected, serving as the load of the AC chopper. The input voltage was set to 120 V RMS, via a grid-connected step-down transformer. Both the n-channel and p-channel branches were switched simultaneously, at a frequency of 1 kHz. This configuration is depicted in Fig. 10 (a). From the resulting AC-chopped resistor current waveform shown in Fig. 10 (b), the utilization of the MTSS device in a power electronics application has been demonstrated. IV. CONCLUSIONS AND FUTURE WORK This paper presents a novel bidirectional switch concept, namely a multi-terminal selector switch. This bidirectional blocking and conducting device can be controlled via a single reference electrode, which is shared when multiple of these devices are switching between different drain voltages. A discrete proof-of-concept realization was designed and evaluated, both in terms of its static and dynamic characteristics. Combined with the AC chopping demonstration, the full utilization of the MTSS in power electronics application has been successfully showcased. Thus, the way is paved for truly N-level capable and scalable power converters, without the steep power and signal isolation requirements that plague today’s multilevel inverter structures. Future work shall include the co-packaging of the MTSS in a single power module, to be used in new and existing power electronics converter topologies. Additionally, further investigation into the switching dynamics, and especially the interactions between the capacitance of the diodes and the FETs shall be carried out. on off (a) on off100 Ω 120 V Time [ms] (b) 0 5 10 15 20 25 VAC [V] -200 -100 0 100 200 ID [A] -2 -1 0 1 2 Fig. 10. (a) Dynamic evaluation board configuration for the AC chopping test and (b) resulting current waveform. REFERENCES [1] International Energy Agency, “Net Zero by 2050,” Paris, 2021. [Online]. Available: https://www.iea.org/reports/net-zero-by-2050 [2] J. Biela, M. Schweizer, S. Waffler, and J. W. Kolar, “SiC versus Si—Evaluation of Potentials for Performance Improvement of Inverter and DC–DC Converter Systems by SiC Power Semiconductors,” IEEE Transactions on Industrial Electronics, vol. 58, no. 7, pp. 2872–2882, 2011. [3] E. O. Prado, et al., “An Overview about Si, Superjunction, SiC and GaN Power MOSFET Technologies in Power Electronics Applications,” Energies, vol. 15, no. 14, 2022. [4] Y. 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