I2DS: FPGA-based Deep Learning Industrial Intrusion Detection System

I2DS: FPGA-based Deep Learning Industrial Intrusion Detection System Ioannis Morianos1,2[0000−0001−9750−5977], Konstantinos Georgopoulos1[0000−0002−6600−4907], Andreas Brokalakis1[0000−0001−7479−5190], Thomas Kyriakakis1,2[0000−0002−0654−1452], and Sotiris Ioannidis1,2[0000−0001−9340−2241] 1Technical University of Crete, Chania, Crete, Greece imorianos, tkyriakakis, abrokalakis, kgeorgopoulos, sioannidis @tuc.gr 2Dienekes, Heraklion, Crete, Greece Abstract. The use of IoT systems in industrial environments provides tremendous benefits and economic value leading to an exponential rise in their adoption. Their extended use, however, does not come without concerns related to potential security threats, thereby creating an obstacle in their further use in the field. To address these security concerns, we introduce a specialized Industrial Intrusion Detection System (I2DS). Our proposed system merges the capabilities of deep learning (DL) with FPGA-based hardware acceleration techniques, enabling it to detect subtle anomalies and potential cyber threats that may evade conventional rule-based intrusion detection systems (IDS) in an effective way. More specifically, by implementing the system on FPGA hardware, we achieve low-latency, high-throughput processing of network traffic, essential for real-time intrusion detection in industrial settings. Our architecture is scalable and can be adapted according to network bandwidth requirements, while remaining lightweight, making it an ideal solution for the stringent resource constraints often encountered in IoT environments. The proposed solution has been validated with the modbus TON-IoT dataset, achieving up to two orders of magnitude higher performance compared to a software equivalent implementation. Keywords: Intrusion detection systems ·Deep learning ·Industrial environments ·Hardware Acceleration ·FPGA. 1 Introduction With the proliferation of Internet of Things (IoT) devices and the expanding inter-connectivity of industrial networks, the exposure to cyber threats has escalated considerably [5, 23]. As a result, Industrial Intrusion Detection Systems (I2DS) schemes play a crucial role in mitigating these risks by actively monitoring network traffic for suspicious activities. Traditionally, Intrusion Detection Systems (IDS) like SNORT1have relied on rules and signatures [16, 17] to identify known patterns of malicious behavior. 1https://www.snort.org/ 2 Morianos et al. While effective for known threats, these rule-based approaches struggle to adapt to the evolving landscape of cyber threats, leaving industrial systems vulnerable to novel attacks and sophisticated adversaries. Consequently, during the past decade we have witnessed a notable surge in the adoption and development of Deep Learning (DL) and Machine Learning (ML) techniques [11, 19, 26] applied to intrusion detection systems. Driven by the availability of large-scale datasets (containing both normal and malicious network traffic), advances in computing power and breakthroughs in algorithmic innovation, it has been able to train those IDSes to distinguish between benign and suspicious behavior and report new and previously unseen threats. As such, MLand DL-based IDSes (e.g. [7, 22, 27, 20, 8]) have emerged as a powerful alternative to traditional rule-based IDSes. However, the use of ML-based IDSes is not without challenges and compared to rule-based IDSes, they can generate more false positives although in the case of industrial environments, where security is paramount, this may be an acceptable tradeoff. ML-based IDSes, however, require significantly more computational resources than typical IDS systems and this can be challenging for an Industrial IoT installation. Cost, latency issues (especially when real-time monitoring is required) and scalability concerns when multiple nodes and highbandwidth network traffic have to be handled can be a show-stopper for such computationally-heavy solutions. To mitigate this challenge, custom hardware solutions may prove to be an efficient alternative. In particular, Field-Programmable Gate Arrays (FPGAs) can offer a promising solution by providing hardware acceleration for ML tasks. Unlike CPUs and GPUs, which are general-purpose processors, FPGAs can be tailored to specific applications at the hardware-level, offering higher efficiency, lower latency and lower power consumption for computational tasks. At the same time, compared to ASICs, they retain their flexibility and are able to adapt to changes and updates post-deployment, which is crucial for security solutions. As such, in this paper, we propose a novel approach that combines the power of ML-based approaches with the efficiency of FPGA-based hardware acceleration to develop an Industrial Intrusion Detection System (I2DS) tailored to industrial data requirements. Our contributions are the following: –By leveraging ML/DL techniques, our I2DS can detect subtle anomalies and potential cyber threats that may evade traditional rule-based IDS. Furthermore, by accelerating the computational tasks on FPGA hardware, we achieve low-latency, high-throughput processing of network traffic, essential for real-time intrusion detection in industrial environments. –Our implementation targets devices that integrate ARM CPU cores and FPGA hardware providing high degrees of flexibility and performance. –Our architecture is scalable by employing parallelization techniques to enhance throughput, thus it can be adapted to different scenarios of varying performance requirements. I2DS: FPGA-based Deep Learning Industrial Intrusion Detection System 3 –Compared to equivalent software solutions, the proposed solution offers orders of magnitude higher performance at power envelopes that are suitable for deployment at almost all levels of IoT environments. The paper is structured as follows. Section 2 summarises previous work on FPGA-based IDSes and ML-based IDSes and the background of this paper. Section 3 describes the process required for the preparation and training of the I2DS ML model. Section 4 describes the proposed hardware architecture. Section 5 presents the experimental setup and the results of our work. Finally, Section 6 concludes the paper and comments on future work directions. 2 Background and related work The concept of using hardware accelerators in the form of FPGA devices for intrusion detection systems is by no means a new one. Implementations such as those reported in [21, 2, 10, 28] have gained significant traction, due to their ability to efficiently process and analyze network traffic in real-time. By offloading processing tasks onto specialized hardware [4, 15], these systems can perform deep packet inspection, pattern matching, and anomaly detection with minimal impact on network performance. Ioannou et al. [9] trained a three-layer fully connected neural network with one hidden layer containing 21 hidden neurons on the NSL-KDD dataset. They accelerated this network using a Xilinx Zynq Z-7020 FPGA and their architecture reportedly supports a throughput of more than 10 Gbps, while achieving an accuracy of 80.52%. While the aforementioned solutions follow a fully-custom hardware design approach, several frameworks have emerged that assist the mapping of a softwarebased model to an FPGA. AMD (Xilinx) has developed Vitis AI2, a tool that produces Deep-Learning Processor Units (DPUs) that can be instantiated in the fabric of the FPGA and support a rich set of AI models that can be accelerated. Similarly, frameworks exist for a more model-specific/custom hardware design implementations such as HLS4ML3, which is a Python package for machine learning inference in FPGAs. Fahim et al. [6] propose a framework that translates traditional open-source machine learning package models into C++ code that can be employed by modern High Level Synthesis (HLS) tools. Recently, AMD (Xilinx) introduced FINN [25, 3, 18], an open-source framework designed to implement specialized accelerators on FPGAs by harnessing reduced-precision datatypes and streaming dataflow architectures. This framework tailors hardware architectures to suit the specific requirements of Deep Neural Network (DNN) topologies and precise datatypes. Each layer is instantiated with dedicated compute units in hardware and on-chip data streams connect these units to establish the desired network topology. By leveraging the compact size of reduced-precision DNNs, FINN enables the storage of all parameters on 2https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html 3https://opensource.web.cern.ch/HLS4ML 4 Morianos et al. the chip, thereby, circumventing potential memory bottlenecks associated with off-chip memory access. To describe the generated Quantized Neural Network (QNN) accelerators, FINN generates synthesizable C++-based HLS code. Using the FINN toolchain for FPGA implementation, Le Jeune et al. [12] present a near real-time NIDS trained using UNSW-NB15 and CICIDS2017 datasets. They propose the utilization of flow buckets for extraction of raw trafficbased features and the acceleration of neural network architectures for intrusion detection. They additionally demonstrate that their deep learning architectures retain performance even when quantized towards 2-bit weights and activations. Umuroglu et al. [24] introduced LogicNets as an approach to co-design neural networks and hardware circuits specifically targeted to extreme-throughput applications. By representing neurons as truth tables with defined input and output bit sizes, LogicNets enable scalable designs capable of high clock frequencies of up to 471 MHz while maintaining strong performance with 91.30% accuracy on a network architecture trained with the UNSW-NB15 dataset. Lastly, Ngo et al. [14] deployed an FPGA anomaly-based AI-assisted IDS for IoT devices by using the IoT-23 dataset. Their results show 40.5x speedup over the Quadro M2000 GPU. They use DMA for the communication between the Programmable Logic (PL) and Processing System (PS) and the performance of the hardware accelerated IDS is bounded only by the memory access overheads. The aforementioned works demonstrate the performance benefits that FPGA acceleration offers to ML-based IDSes. However, because of the complexity of the designs at the hardware level, almost all modern solutions rely on high-level frameworks to generate the hardware accelerators that are mapped to the reconfigurable resources. While for productivity and functional verification purposes, this is definitely the design approach that is most beneficial, we recognize that such high-level approaches introduce overheads that cannot be ignored, both at the performance level and at the resources that are required. As such, we propose a design approach that on one hand leverages this high-level workflow from model design to hardware generation, but employs a more custom architecture and replaces python-related structures with lower level C code aiming to provide higher performance and minimize associated overheads. 3 QNN model design 3.1 Industrial enviroment dataset Our work targets the industrial IoT environments. As such, the model we designed was trained with the TON IoT4Modbus dataset of the UNSW [1, 13]. Modbusservice simulates the functionality of the Modbus devices found in many industrial applications. These devices interact with each other using a masterslave communication to transmit register types such as input, discrete, holding and Coil over serial lines. 4https://research.unsw.edu.au/projects/toniot-datasets I2DS: FPGA-based Deep Learning Industrial Intrusion Detection System 5 Fig. 1. TON IoT Modbus description. [1] 3.2 Quantization and training For the quantiazation-training and evaluation of the model we used the Pytorch framework with the Brevitas library. The model is a Multi Layer Perceptron (MLP) that initially undergoes quantization, through the utilization of Quantization Aware Training (QAT) within Brevitas. By integrating quantization directly into the training pipeline, Brevitas enables deep learning models to learn parameters that are aware of the reduced precision requirements imposed by FPGA hardware. This approach addresses the challenge of accuracy degradation often associated with low-bit precision quantization, as the model adapts and optimizes its parameters during training to account for quantization effects. Our neural network was trained using 2-bit quantization for both weights and activations. The MLP consists of four Fully-Connected (FC) layers: three hidden layers, each with 64 neurons, and a final output layer with a single output. The model underwent training using a Stochastic Gradient Descent (SGD) optimizer with an initial learning rate of 0.001. During the learning process, the learning rate was reduced by a factor of 10, whenever no improvement was observed over the last 10 epochs. As a result, training proceeded for a total of 100 epochs while the training dataset was a quantized version of the TON IoT modbus dataset. Eventually, the trained model achieved an accuracy of 96.37%, with 99% precision and 89% recall leading to 94% f1-score. 4 Hardware Implementation 4.1 Mapping the Software Model to a Hardware Implementation Following the training process, we employ the FINN compiler for the construction of hardware layers to deployed in the FPGA resources. The process involves several key steps. Initially, optimization techniques are employed to eliminate floating-point operations from the model. This involves redistributing and consolidating these operations within multi-thresholding layers, facilitating their transformation into HLS layers. Once all non-supported operations have been addressed, the model is synthesized into hardware using Xilinx Vivado through FINN. The initial hardware designed produced by FINN can be further customized, optimized and re-synthesized using the Vivado manually (as is the case 6 Morianos et al. for our work). Subsequently, this synthesized hardware can been deployed to the actual FPGA hardware device. For our work, we have used the ZYNQ UltraScale+ XCZU7EV MPSoC device hosted on a ZCU104 prototyping board5. 4.2 Hardware model Figure 2 demonstrates the basic hardware component architecture, i.e. the hardwarebased model component. This component consists of the four hardware layers, each one having as many Processing Elements (PEs) as the neurons of the layer, for both interas well as intra-layer parallelization. The weights are integrated at the layers, minimizing the cost of weight loading. Fig. 2. Hardware layers of accelerated model. 4.3 I2DS architecture The aforementioned hardware model is the main computational kernel that performs the intrusion detection tasks. To produce a working IDS system, an engine that can properly feed this computational kernel with the network data streams is required, as well as a controller for its operation. For the former, the hardware model is integrated with a Direct Memory Access (DMA) engine that moves data from the data packet memory to the accelerator. Network data is written in a DDR4 memory connected directly to the FPGA resources (PL side of the MPSoC chip) and through the DMA engine they are loaded to a FIFO structure. The hardware accelerator accesses the network data sequencially from the FIFO memory that acts as a buffer. Both DMA engine and FIFO memory are connected through high performance AXI4 interfaces. The control of the process is handled by software running on the general purpose CPU cores of the MPSoC device (ARM Cortex-A53). The CPU employs AXI4-lite interfaces to communicate with the memory resources and pass configuration data to the accelerator. Detection alerts are laso conveyed from the accelerator to the software components through this interface. According to the application performance requirements, the aforementioned architecture can be scaled. As there are no practical dependencies between data, 5https://www.xilinx.com/products/boards-and-kits/zcu104.html I2DS: FPGA-based Deep Learning Industrial Intrusion Detection System 7 several I2DS modules (a module consists of a hardware detection engine, a DMA core and a FIFO memory) can be used in parallel to simultaneously process different network packets or streams. The practical limiting factors for scaling is the performance of the memory interface and the available reconfigurable resources of the FPGA device. In the device of our development board, we have been able to scale our architecture up to four instances and this system is depicted in Figure 3. Fig. 3. I2DS architecture. 4.4 Implementation For the implementation of the hardware system, we have used Vivado 2020.2, targeting the XCZU7EV-2FFVC1156 FPGA device. The hardware accelerator has been implemented through FINN, according to the process described in Section 4.2. Although FINN can generate both the bitstream that is used to program the reconfigurable hardware resources as well as the python code that targets the Processing System (PS), we opted for a semi-custom solution. On the hardware side, we used the synthesizable hardware kernel for the model that FINN produced and manually connected it to the AXI DMA and FIFO components as well as the different interfaces and other components required to produced the system decsribed in Figure 3. The software components handling control and communications, produced in python code by the FINN framework, were also replaced by our C code to remove the performance overheads introduced by the high-level interpreted software. 8 Morianos et al. 5 Evaluation 5.1 System performance and resources utilization To evaluate the performance of our proposed solution, we have produced three implementations. A software-equivalent (marked as SW-EQ in the figures below) inference of the model is executed on an AMD Ryzen 9 3900X 3.80GHz, while the hardware accelerated implementation is loaded on the ZYNQ UltraScale+ MPSoC ZCU104 development board hosting an UltraScale+ FPGA integrated with ARM Cortex-A53 (1.3GHz). Two hardware accelerated implementations are provided. The first one (FINN) is the hardware accelerated version of the IDS using the FINN framework (marked as FINN), while the other is based on the modifications and optimizations discussed in the previous section. For the latter, three different configurations have been produced, with one (marked as I2DS), two (I2DSx2) and four (I2DSx4) accelerator engines. It should be noted that both software and hardware-accelerated implementations are equivalent: the hardware model provides the exact same accuracy as the software model (96.37%) and the same data set has been used in both cases. The metric that is used to report the performance is records per second (rps). Every record is a new input of data from the dataset with all the modbus headers. In every experiment a dataset of 10,000 records was used for equal comparison. By measuring the inference runtime for every implementation we can estimate the performance in rps (records per second). During the verification of the model at the developing server, the throughput of the SW-EQ of the model has been measured at 84,746 rps. Before the implementation of the proposed architecture, the full steps of the FINN framework were followed, resulting in an accelerated hardware model and a Python code with a throughput of 4,878,048 rps combined. As mentioned before, in the final implementation of our architecture, a custom design was used, incorporating the model-IP generated by FINN, DMA, and FIFOs targeting the PL part of the MPSoC, along with optimized C code in the PS part. The experimental results of the I2DS using C code showed a throughput of 14,285,714 rps, almost four times higher than the performance provided by initial FINN generated system. Finally, the parallel optimized architecture with two parallel models and four parallel models achieved throughputs of 28,011,204 and 52,631,579 rps respectively. Figure 4 demonstrates the performance achieved in all cases. Our system targets IoT-Industrial environments that usually are resource constrained. Vivado reports (provided in Table 2) show that our implementations consume less than 30% of the total resources of the FPGA fabric even with four levels of parallelization. As such, smaller FPGA devices than our prototype platform can be adopted to reduce costs and/or energy consumption or additional logic may be integrated in the FPGA (for example the model can be extended or refined, while other components providing additional functionality can also be implemented alongside our accelerator). It should be noted that all hardware implementations are using a 100 MHz clock. I2DS: FPGA-based Deep Learning Industrial Intrusion Detection System 9 SW-EQ FINN I2DS I2DSx2 I2DSx4 0 2 4 6 ·107 84,746 4.88 ·106 1.43 ·107 2.8·107 5.26 ·107 Implementation Performance (rps) Fig. 4. Performance (in terms of records per second) of software and hardware implementations. Table 1. Relative performance comparison of software and hardware implementations. SW-EQ FINN I2DS I2DSx2 FINN 57.6x I2DS 168.6x 2.9x I2DSx2 330.6x 5.7x 1.9x I2DSx4 620.9x 11x 3.7x 1.9x Table 2. Resource utilization of hardware implementations on a ZCU104 board. Resources Available FINN I2DS I2DSx2 I2DSx4 LUT 230400 20733 (9.00%) 16423 (7.13%) 32072 (13.92%) 62746 (27.23%) LUTRAM 101760 996 (0.98%) 881 (0.87%) 1672 (1.64%) 3178 (3.12%) FF 460800 11079 (1.64%) 12010 (2.61%) 23414 (5.08%) 45345 (9.84%) BRAM 312 2 (0.64%) 7 (2.24%) 14 (4.49%) 28 (8.97%) 5.2 Discussion Hardware implementations achieve up to two orders of magnitude higher performance compared to the software equivalent implementation, thus demonstrating clearly the benefit of employing hardware acceleration in the specific application.