Operating efficiency in the capital-intensive semiconductor industry: A nonparametric frontier approach

Qiao, Guangshun; Lu, Yulin Article Operating efficiency in the capital-intensive semiconductor industry: A nonparametric frontier approach Economics: The Open-Access, Open-Assessment Journal Provided in Cooperation with: De Gruyter Brill Suggested Citation: Qiao, Guangshun; Lu, Yulin (2024) : Operating efficiency in the capital-intensive semiconductor industry: A nonparametric frontier approach, Economics: The Open-Access, OpenAssessment Journal, ISSN 1864-6042, De Gruyter, Berlin, Vol. 18, Iss. 1, pp. 1-17, https://doi.org/10.1515/econ-2022-0050 This Version is available at: https://hdl.handle.net/10419/306072 Standard-Nutzungsbedingungen: Die Dokumente auf EconStor dürfen zu eigenen wissenschaftlichen Zwecken und zum Privatgebrauch gespeichert und kopiert werden. Sie dürfen die Dokumente nicht für öffentliche oder kommerzielle Zwecke vervielfältigen, öffentlich ausstellen, öffentlich zugänglich machen, vertreiben oder anderweitig nutzen. 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If the documents have been made available under an Open Content Licence (especially Creative Commons Licences), you may exercise further usage rights as specified in the indicated licence. https://creativecommons.org/licenses/by/4.0/ Research Article Guangshun Qiao* and Yulin Lu Operating Efficiency in the Capital-Intensive Semiconductor Industry: A Nonparametric Frontier Approach https://doi.org/10.1515/econ-2022-0050 received January 31, 2023; accepted October 05, 2023 Abstract: This article uses a nonparametric production frontier approach to investigate the operating efficiency differences by the impacts of capital expenditure and business model in the global semiconductor industry. Handling the impact of capital expenditure as a fixed input by the directional distance estimator, this study compares the operating efficiencies in the global semiconductor industry between the integrated device manufacturers and the fabless and foundry firms over 1999–2018. The estimation results indicate that the operating efficiencies do vary in the semiconductor by the business model. The vertically integrated manufacturers dominate the semiconductor industry, and the capital-intensive manufacturers operate more efficiently than the assetlight fabless firms on average. Keywords: semiconductor industry, CAPEX, integrated device manufacturer, nonparametric frontier, directional distance estimator 1 Introduction Integrated circuits (ICs) are essential components of virtually all modern electronic devices. Since Bell laboratories invented the transistors in 1947 and Texas Instruments released the first working IC in 1958, the semiconductor industry, which is the aggregate of companies engaged in the design and fabrication of semiconductor devices or IC chips, has been at the forefront of the digital economy for decades. From laptop to smartphone and artificial intelligence (AI), semiconductor devices are present in nearly all aspects of modern technology. The personal computer revolution in the 1970–1980s was a result of advances in semiconductor technology, such as the Intel 8,008 microprocessor (Ceruzzi, 1996). In the development and expansion of the World Wide Web revolution in the 1990s, application-specific integrated circuits played a significant role in enabling fast and efficient networking and data processing, contributing to the growth of web-based technologies and consumer electronics (Makimoto, 2002).Theriseofthesmartphoneinthe2010swassupported by higher-performance system-on-a-chip (SoC), such as the Apple A series and Qualcomm Snapdragon series. ChatGPT, latterly the most popular deep learning workload, required significant computational power and was trained on Nvidia 1 graphics processing units (GPUs). Due to the growth in emerging technologies such as AI, cloud computing, Internet of Things, 5G networks, autonomous vehicles, industrial automation, and renewable energy systems, the needs for more powerful, energy-efficient, and miniaturized semiconductor devices have been consistently increasing. The 2023 Semiconductor Industry Association (SIA) factbook reported that the global semiconductor sales reached the highest-ever annual total of $574 million in 2022. 2 McKinsey’s preliminary forecast shows that the global semiconductor industry is poised to become a trillion-dollar industry by 2030 (Burkacky et al., 2022). 1.1 Structural Change History in the Semiconductor Industry The semiconductor industry has a long history of structural change. Prior to the 1980s, a few integrated device  * Corresponding author: Guangshun Qiao, School of Finance and Trade, Wenzhou Business College, Wenzhou, 325035, China, e-mail: [email protected] Yulin Lu: School of Accounting, Jilin Business and Technology College, Jilin, 130507, China  1Nvidia Corporation (Nasdaq: NVDA) is a leading technology company specializing in the design and development of GPUs and AI computing solutions. 2https://www.semiconductors.org/the-2023-sia-factbook-your-sourcefor-semiconductor-industry-data/. Economics 2024; 18: 20220050 Open Access. © 2024 the author(s), published by De Gruyter. This work is licensed under the Creative Commons Attribution 4.0 International License. manufacturers (IDMs), such as Intel, Infineon, 3 ST, 4 and Texas Instruments, were the dominant players in the semiconductor industry. These IDMs have in-house capabilities to perform all of the production processes (e.g., research and design [R&D], front-end fabrication, and back-end assembly and test [A&T]). For example, as a leading IC manufacturer, Intel has several fab production sites (located in the US, Ireland, Israel, etc.), A&T sites (located in the US, China, Malaysia, Vietnam, etc.), and tens of thousands employees and partners all over the world. The vertical integration of managing the entire production process internally allows Intel to have greater control over quality, intellectual property (IP), and the ability to optimize the manufacturing process for specific needs (Malone, 2014). The semiconductor industry is renowned for its rapid technological advancements. This dynamic field continually pushes the boundaries of innovation, driving progress in areas of miniaturization, performance improvements, power efficiency, and emerging technologies. For example, the semiconductor industry had experienced significant shrinks in process technology nodes, 5 from around 130 nm in 2000, to 32 nm in 2010, and 7 nm in 2020 (Flamm, 2017). However, due to physical constraints, manufacturing challenges, heat dissipation, and power consumption issues, semiconductors with ever-expanding complexity approach the limits of Moore’slaw 6 (Mack, 2011). The expenses of building a semiconductor fabrication facility had increased from around $1 billion in the 2000s to more than $10 billion nowadays (e.g., see Ibrahim et al., 2014; Lambrechts et al., 2018). The substantial increase in fab construction costs became prohibitive for almost all the IC suppliers. It stimulated business model innovation in the semiconductor industry and gave birth to the fabless–foundry business model in the mid-1980s (Sarma & Sun, 2017). In the fabless–foundary business model, fabless companies dedicate their time to IC design and brand operation, while pure-play foundries devote themselves to frontend fabrication, and a third group of companies are allotted for back-end outsourced semiconductor assembly and test (OSAT) operations. By specializing in IC design with brand operation, fabless companies can concentrate their efforts and resources on creating differentiated and competitive chips where technological innovation meets strategic marketing, leveraging the manufacturing capabilities of semiconductor foundries and OSATs (Hurtarte et al., 2011). At the same time, foundries and OSATs take care of the actual manufacturing process, fabrication, and quality control, allowing fabless companies to focus on their core competencies, resulting in a more flexible semiconductor business ecosystem. A milestone of the vertical disintegration in the semiconductor industry is the establishment of the Taiwan Semiconductor Manufacturing Company (TSMC) in 1987. TSMC introduced the concept of a pure-play semiconductor foundry, specializing solely in the manufacturing of ICs and committed to be a long-term non-competitive partner with the fabless firms. By continuously investing in advanced process technologies, TSMC quickly established itself as a leader in semiconductor manufacturing. Presently, TSMC is the first company to commercialize the 7nm process technology 7 and the largest dedicated semiconductor foundry worldwide. 8 Its advanced process technologies, highly automated manufacturing facilities, the ability to scale production, and a strong focus on customer satisfaction have helped TSMC to build long-term relationships with its customers, enabling it to capture a significant share of the highend semiconductor market and making it a crucial player in the semiconductor ecosystem (e.g., see Hsieh et al., 2002). 1.2 CAPEX Plays a Crucial Role The fabless–foundry business model has significantly changed the structure of the semiconductor value chain over the last  3Infineon Technologies AG (Infineon) is Germany’s largest semiconductor manufacturer. It was established on April 1, 1999, as a spinoff from Siemens AG, taking over Siemens’semiconductor operations including its research, development, manufacturing, and sales activities. Infineon has been a leader in developing and producing highquality power MOSFETs (metal-oxide-semiconductor field-effect transistors) for various applications. 4STMicroelectronics (ST) is a global semiconductor company headquartered in Geneva, Switzerland. It was formed in 1987 through a merger between the semiconductor divisions of Italy’s STET (Società Finanziaria Telefonica) and France’s Thomson Semiconducteurs. 5Historically, the process technology node (also process node or simply node) was named after the physical gate length of a transistor. Shrinks in process node offer numerous advantages, including increased transistor density, improved performance, enhanced power efficiency, cost reduction, miniaturization, advanced functionality, and manufacturing advancements. 6Moore’s law was first observed in 1965 and later revised in 1975 by Gorden Moore, the co-founder and chairman emeritus of Intel. Moore’s law states that the number of components per IC doubles about every 2 years.  7The 7 nm process has helped TSMC win major customers such as Apple (A series Bionic chips), Qualcomm (Snapdragon 800-series chipsets), and Nvidia (RTX 30 series GPUs). 8TSMC had invested more than $16 Billion at its Fab 18, a new fab in the Southern Taiwan Science Park for producing 5nm and 3nm process technology. 2Guangshun Qiao and Yulin Lu few decades and has been a topic of wide interest (e.g., see Adner & Kapoor, 2010; Macher et al., 2007; Sarma & Sun, 2017). Many factors might affect production costs and productivity in the innovation-driving IC industry, such as capital allocation (Brown et al., 2005), technological capability (Park et al., 2021; Sher & Yang, 2005), business model (Shin et al., 2017), device type (Park et al., 2018), institutional factor (Gugler & Siebert, 2007; Lu et al., 2013; Walheer & He, 2020), and foreign competition (Henderson & Scott, 2018). The major challenges in the capital-intensive semiconductor industry are the heavy capital expenditure (CAPEX) for cleanroom and costly equipment for front-end fabrication and back-end A&T procedures. Cleanrooms must be free of all airborne particles, which requires advanced filtration systems, controlled air flow, and rigorous cleaning procedures. Additionally, due to the complexity of the manufacturing processes and the need for precision and accuracy in the production of semiconductor chips, the equipment used in front-end fabrication and back-end A&T is costly (Monch et al., 2012). For example, extreme ultraviolet lithography (EUV) 9 is a critical technology for advanced semiconductor manufacturing processes. Each EUV machine made by ASML 10 costs around $200 million or even higher. The high costs associated with CAPEX can be a significant barrier for new companies looking to enter the semiconductor industry, as well as a challenge for existing companies looking to expand their manufacturing capacity (Powell et al., 2015). Another challenge in the semiconductor industry is the cyclicality of demand (Rastogi et al., 2011; Tan & Mathews, 2010). The semiconductor industry is highly dependent on end-market demand, which can be volatile and subject to rapid shifts. It is difficult for companies to accurately forecast demand and plan production capacity, which might lead to costly overproduction or underproduction. In order to achieve full-capacity utilization, the foundries and OSATs seek to optimize productivity by serving many fabless companies, while even IDMs are renting their idle capacity to competitors to reduce the financial burden. It also triggered many of the IDMs to start outsourcing manufacturing partially from the dedicated foundries and became fab-lite 11 (Saha, 2015). In comparison, the fabless companies, mostly startups or spin-offs that are getting rid of the burden in setting up, maintaining, and upgrading fabs, are more flexible to integrate within local knowledge networks and focus in less crowded niche markets, specialized applications, or innovative technologies to explore technological diversity and comparative advantage, and compete with the IDMs. Besides the huge equipment expenditures, R&D costs for developing leading-edge products such as microprocessors and radiofrequency devices also raise steadily. With the shrinking of process node, technological complexity and design complexity increase exponentially. The slow progress in node technology requires continuous investments in both R&D and advanced fabrication facilities. Based on the 2023 SIA factbook, US semiconductor companies accounted for sales totaling $275 billion in 2022, or 48% of the global market. At the same time, US semiconductor firms also invested $58.8 billion in R&D, the highest in history to remain competitive in the industry. The uncertainty of R&D investments and the IP protection by incumbents set high barriers to entry and favor the success of large IDMs, such as Intel, ST, and Texas Instruments, which are able to make risky investments and thus have a higher chance to foresee and lead the technology evolutions. 1.3 Trade-offs Between Business Models There has been a long-lasting debate on which business model is operating more efficiently, or which business model is more likely to dominate the semiconductor industry. On the one hand, the reduced barriers to entry by vertical specialization drastically reduces the burden of CAPEX and ensures the domination of new markets by the fabless design houses. The entry of new fabless companies, most of which are spinoffs from industry incumbents, spur innovation and propel the diversification of products in various applications (Pellens & Della Malva, 2018). Furthermore, vertical disintegration in the semiconductor value chain is accompanied and twisted by the trend of industry globalization (Brown et al., 2005). Since the 1990s, fabless firms have had substantial shares or even dominated in most of the fastest-growing market segments (Balconi & Fontana, 2011). Foundries are also becoming technology transferors rather than merely manufacturing capacity providers in the semiconductor value chain (Li et al., 2011). In addition, the collaboration between the asset-light fabless and the pure-play foundry provides more robust protection of IP rights (Sarma & Sun, 2017). When the fabless firms pass on their design blueprints to  9EUV uses extreme ultraviolet light with a wavelength of near 13.5 nm to create intricate patterns on silicon wafers, allowing for the production of smaller and more complex ICs. 10 Advanced semiconductor material lithography (ASML) is a Dutch multinational corporation and the sole supplier in the world of EUV photolithography machines used to manufacture the most advanced chips, targeting 5 and 3 nm process nodes. 11 Fab-lite, also called fab-light, refers to a semiconductor company that retains some in-house fabrication facilities but also relies on outsourcing a large portion of its production to external foundries. Operating Efficiency in the Capital-Intensive Semiconductor Industry 3 pure-play foundries, the threats of replication and the risk of IP theft are relatively low, comparing with the early years when fabless firms’ICs could only be manufactured by their rival IDMs. On the other hand, despite a trend toward vertical specialization driven by the entry of fabless firms, the vertically integrated IDMs have continued to persist and coexist with the fabless entrants in the semiconductor industry. Dibiaggio (2007) and Monteverde (1995) credit the efficiency of IDMs to the internalization of transaction costs. Ernst (2005), Macher (2006), and Kapoor and Adner (2012) hold the knowledge-based view that the IDMs achieve performance advantages when technological developments involve complex problems. Kapoor (2013) proposed and found that the incumbents who persist with vertical integration increase their emphasis on systemic innovations. Due to the inherently increasing complexity of the semiconductor supply chain, currently there does not exist an adequate reference model for the semiconductor industry, and more appropriate and state-of-the-art models are in great demand to analyze the semiconductor supplychain(Monchetal.,2012). The semiconductor industry is commonly characterized as both technology-intensive and capital-intensive. Much research on the topic of structural change in the semiconductor industry emphasizes the evolution of technology (Chen et al., 2019; Cho, 2020; Hwang & Choung, 2014; Shin et al., 2017). The impacts of capital investments in the semiconductor industry have not been discussed adequately. Besides the research shown earlier that focus on analyzing the impacts of technology evolution in the semiconductor industry, this study plans to emphasize the feature of capital intensive in comparing the trade-offs of business model in the semiconductor industry. This study applies up-to-date econometric methods to handle the impacts of CAPEX as a lump sum fixedinputandexploresthedifferences of operating efficiency by business model in the highly dynamic semiconductor industry in the past two decades. The methodological contributions of article will be discussed in the next subsections. 1.4 Brief Literature Review Taking advantage of a flexible functional form, data envelopment analysis (DEA) is one of the most popular approaches for efficiency estimation. There are rich records for performance evaluation in the semiconductor industry using the DEA approach. For instance, Kozmetsky and Yue (1998)examined the cost efficiency of 56 IC companies worldwide and showed that US, Japanese, South Korean, and Taiwanese IC companies had become the major participants in the global semiconductor industry in the early 1990s. Lu and Hung (2010) compared the managerial performance efficiency of 48 leading vertically disintegrated firms in Taiwan’sICvalue chain and noted that fabless companies perform better than foundries and OSATs. Jang et al. (2016) measured the cumulative change in R&D efficiency of 49 global leading fabless companies and noted that during the period 2007–2013, the overall R&D efficiency declined slightly. Li et al. (2019) explored 64 major Chinese enterprises in the semiconductor industry and found that the most significant factor limiting future improvements to innovation efficiency was a low level of scale efficiency. One common problem of these studies, among others, such as Lu et al. (2013), Hsu (2015), Hung et al. (2014), and Tsai et al. (2017), is the slow convergence rate of the nonparametric DEA estimator. 12 Accompanied by the increasing numbers of input and output dimensions, the convergence rate in DEA estimation is decreasing sharply. In cases when the observations are restricted to a small number either by geographic boundary or by business model boundary, the issue of slow convergence rate in DEA estimation may become severe and critical. For example, the research of Kuo and Yang (2012), Lu and Hung (2010), and Wu et al. (2006) used a small number of 38–39 companies to evaluate the performance of the fabless corporations in Taiwan, while in some extreme cases, such as Chen and Chen (2011), Hung and Lu (2008), Lin et al. (2019), and Liu and Wang (2008), the studies contained only 10–25 companies. The effective parametric sample size of the DEA estimators in these approaches was very small, which might lead to unconvincing results. 13 1.5 Methodological Features The main methodological feature in this study, after highlighting the slow convergence rate in DEA estimation, is to provide an empirical example of choosing the appropriate estimation methods in analyzing the operational efficiencies of the semiconductor industry, aiming to gain a faster convergence rate and hence a lower order of estimation error.  12 The convergence rate quantifies how fast the estimation error decreases when increasing the sample size n . Generally, the convergence rate in a linear regression is − n 1 2, while the convergence rate of a nonparametric estimator is slower than its parametric counterpart. 13 For example, Hung and Lu (2008) used the DEA to estimate efficiencies of 25 companies by 4 input and 3 output variables. The effective parametric sample size of Hung and Lu (2008) was only ≈ + 25 3 2 43 . Appendix A explains how to calculate the effective parametric sample size. 4Guangshun Qiao and Yulin Lu The semiconductor industry is, indeed, a highly globalized industry. For example, Silicon Valley, located in the southern San Francisco Bay Area of California, US, renowned for its collaborative ecosystem that fosters entrepreneurship and innovation, has attracted a cluster of famous fabless semiconductor companies, such as Nvidia, Qualcomm, 14 AMD, 15 and Xilinx. 16 While the US has a strong presence in the fabless semiconductor sector, there are also fabless companies based in other countries such as the UK, Israel, Japan, and China. In order to support the growth of the fabless semiconductor industry on a global scale, foundries and OSATs are located in various regions around the world to cater to the global demand for semiconductor production and ensure a diverse supply chain for semiconductor manufacturing. Hence, this study considers the deeply globalized semiconductor value chain as an aggregated industry and collects data on 470 semiconductorcompaniesallovertheworldwith5,136observations in 1999–2018. The global database not only provides a worldwide perspective of the semiconductor industry, but also gains a faster convergence rate in DEA estimation. Furthermore, this study uses a dimensionality reduction techniquetofurtherimprovetheconvergencerate. Another methodological feature in this article is to treat the CAPEX as a fixed input by using the directional distance measure. CAPEX is a kind of lump sum investment, which involves significant upfront expenses that are expected to yield long-term benefits. By allocating funds toward acquiring new technology, upgrading infrastructure, and expanding facilities, companies can enhance productivity, improve operational efficiency, and leverage the latest technological advancements to stay competitive in the market. Although CAPEX decisionsplayacrucialroleindetermining the level of productivity and technology within an organization, in the short run, CAPEX is not under managers’ direct control. The directional distance estimator provides a convenient method to distinguish the non-discretionary fixed input CAPEX with other variables. The setting of this method will be discussed further in the next section. Another methodological feature in this article is to investigate the impacts of the business model in the semiconductor industry through a conditional nonparametric frontier approach. Recent developments in nonparametric frontier estimation (Daraio & Simar, 2014; Daraio et al., 2020) provide tools to analyze the operating efficiencies in the semiconductor industry under various types of constraints such as capital investments and the business model. While the heterogeneity by CAPEX is treated as a fixed input variable by the directional distance estimator (Daraio et al., 2020), the heterogeneity by the business model is handled by the conditional efficiency estimators (Daraio & Simar, 2007). In addition, separability test recommended by Simar and Wilson (2020) is applied to choose the optimal conditions considering both the heterogeneities by the business model and time. 1.6 Findings and Organization This article aims to follow the Daraio et al.'s (2020)approach to shed light on disentangling the impact of capital investments and comparing the technical efficiencies between IDMs and vertically disintegrated fabless and foundry firms in the semiconductor industry. The estimation results indicate that CAPEX plays a crucial role in the semiconductor industry and vertically integrated manufacturers dominate the industry. Since semiconductor companies heavily rely on CAPEX to acquire advanced equipment, to establish and upgrade manufacturing facilities, and to develop cuttingedge technologies, the capital-intensive IDMs and OSATs operate more efficiently than the asset-light fabless firms on average. It is worth noting that such kind of operating efficiency is probably not attributed to management improvement, but generated from subsidies or M&A (VerWey, 2019). In fostering a healthy and competitive semiconductor ecosystem, we suggest to tilt the subsidies of the semiconductor industry towards the fabless sector to encourage more innovation and diversification. This article is organized as follows. Section 2 explains the nonparametric frontier framework and discusses the diagnostics and test statistics to choose a suitable estimator in this research. Section 3 introduces the data and defines the variables. Section 4 presents the empirical results and discusses the effect of capital investment and business model in the semiconductor industry. Section 5 concludes. 2 Methodology 2.1 DEA Approach The economic theory of efficiency in production can be traced to Farrell (1957). Attributed by its flexibility and adaptability, DEA (Charnes et al., 1978) is considered the  14 Qualcomm holds significant IPs and patents related to Code Division Multiple Access (CDMA) technology and has established itself as a leader in mobile technology with its Snapdragon processors. 15 Advanced Micro Devices, Inc. (AMD), headquartered in Santa Clara, is a major fabless semiconductor company known for its CPUs. AMD competes with Intel in the computer processor market. 16 Xilinx, Inc., located in San Jose, is a well-known fabless company specializing in field-programmable gate arrays (FPGAs) and SoCs. Operating Efficiency in the Capital-Intensive Semiconductor Industry 5 mainstream approach in frontier analysis for assessing technical efficiency. 17 A large and growing literature has developed on the application of the DEA approach in the semiconductor industry (e.g., see Jang et al., 2016; Li et al., 2019; Sueyoshi & Ryu, 2020; Tsai et al., 2017; Zhou et al., 2020). This article follows the DEA approach and applies the latest methodological advancements of Bădin et al. (2012), Daraio et al. (2020), and Simar and Wilson (2020) to address the impacts of CAPEX, business model, and time in the ever-evolving semiconductor industry. Production theory primarily examines how the production process works within a firm to combine p inputs to achieve the desired level of q outputs and analyzes the factors that affect production decisions. The idea in the DEA approach is to estimate the efficiency score of a production plan ( x y,), or the distance from ( x y,) to the boundary of the production set = Ψ  { () ∣ }∈ ++ xy x y,can produce pq .Asa nonparametric approach, DEA does not require explicit assumptions about the underlying production function, allowing for a flexible data-driven analysis. Hence, we select the DEA approach in handling the efficiency estimation of the semiconductor industry. 2.2 Directional Distance Measure There are four kinds of commonly used efficiency measures in the DEA approach, namely, input-oriented Debreu–Farrel measure, out-oriented Debreu–Farrel measure, hyperbolic measure (Wilson, 2012), and directional distance measure (Chambers et al., 1998). The input-, output-, and hyperbolic oriented measures are radial measures that allow for only nonnegative values. In contrast, the directional distance measure is an additive measure. The directional distance measure is given by: (∣ ) {∣( )}=−+∈ β xyd d βx βd y βd,,,Ψsup , Ψ, xy x y (2.1) which projects ( x , y ) onto the technology in a specified direction ( − d x , d y ). The directional distance measure (‖ ) β xyd d,,,Ψ xy nests the inputand output-oriented measure as a special case by setting the direction vector ( d d, xy )as( x ,0)and ( y0, ), respectively. The directional distance measure allows for negative values of x and y , as it adds the feasible quantities to a unit’s output and simultaneously subtracts proportional quantities from its input. The choices of the directions d x and d y are also flexible. Some direction can be set equal to zero to represent a non-discretionary input or output (Simar & Vanhems, 2012). This feature is used to proxy CAPEX in the semiconductor industry in this study, by categorizing CAPEX into a fixed input that is not under managers’direct control in the short run. 2.3 Estimation of the Frontier The attainable set Ψ is unobserved. Nonparametric methods such as DEA and free disposal hull (FDH) are developed to estimate the unobservable production set Ψ . The FDH estimator  Ψ FDH is defined as:   {( ) ∣ }=⋃ ∈ ≥ ≤ ∈++ xy x Xy Y Ψ ,, , XY pq iiFDH , ii n (2.2) where  {( ) } =XY, nii . FDH estimator  (∣ )β xyd d,,,Ψ xy FDH is obtained by replacing Ψ with  Ψ FDH . DEA estimator  Ψ DE A is the convex hull of  Ψ FDH (Banker et al., 1984). 18 The trade-offbetween FDH and DEA is not trivial. Simar and Wilson (2015) summarized that the FDH and DEA estimators converge to limiting distributions at rates of + n pq 1 and ++ n pq 21, respectively. The convergence rate for the FDH and the DEA estimator slows down with the increasing of dimensionality + p q . 19 To minimize the estimation error empirically, we can either increase the sample size n or decrease the total dimensions of + p q . If the sample size n is restricted to a small number by real-world constraints, including the market scale or scope of the industry, geographical or political restrictions, and the high cost of data collection, dimension reduction such as the principal component analysis (PCA) may become an attractive solution. Appendix A provides an introduction of PCA. After the diagnostics of dimension reduction, a test of convexity is recommended for the trade-offbetween  Ψ FDH and  Ψ DE A (Kneip et al., 2015). If the null hypothesis of convexity is rejected, the FDH estimator is the only consistent estimator. Alternatively, if the null hypothesis is not rejected, the DEA estimator might be preferred. However, the test of convexity (Kneip et al., 2015; Kneip et al., 2016) depends on randomly split the original sample into two independent subsamples for the bias term calculations. This study applies a  17 Lampe and Hilgers (2015) surveyed 4,782 publications on performance measurement in 1978–2012 and found that 4,021 were for DEA, and 761 were for stochastic frontier analysis (SFA).  18 To be more precise, the notation DEA is for the variable-returns-toscale DEA in this study. 19 The estimation error will increase with the slowdown of convergence rate. This is known as the curse of dimensionality in nonparametric estimation. 6Guangshun Qiao and Yulin Lu bootstrap algorithm (Simar & Wilson, 2020) for the convexity test to overcome this issue. 2.4 Conditional Efficiency Measures There exist factors such as the business model, constraints of technology and regulatory, and differences in ownership, which are beyond control of the manager but may influence the production process. These factors are denoted as environmental factors ∈ Zr . Daraio and Simar (2005) proposed to investigate the joint behavior of ( ) XYZ,, in probability terms by defining the conditional attainable set as = Ψ z  { () ∣ } ∈= ++ xy x y Z z, can produce when pq . Note that =⋃ ∈ Ψ Ψ zZ z. The probability distribution of ( X Y,) conditional on = Z z can be written as: (∣) ( ∣ )=≤≥= ∣ H xyz X xY yZ z,Prob, . XYZ, (2.3) A conditional directional distance measure is given by: (∣ ) {∣ ( ∣) } =−+ > ∣ β xyd d z βH x βd y βdz,,, sup , 0. xy XYZ x y,(2.4) Plugging a nonparametric estimator of ( ) ⋅ ∣ H XYZ,into equation (2.4) can derive the estimation of the conditional efficiency score accordingly. 20 2.5 Second Stage Analysis In a particular case, Z has no impact on the boundaries of the Ψz and = ΨΨ z . Simar and Wilson (2007, 2011) called it the separability condition and argued that if the separability condition is not hold, naive regression in a second-stage analysis may provide inconsistent estimation. Alternatively, Bădin et al. (2012, 2014) suggested a flexible nonparametric location-scale model (∣)== β XYZ z, () ()+μz σzεin a secondstage regression, where ( ) μz measures the average effect of z and ( ) σzprovides additional information on the dispersion of the efficiency distribution. Bădin et al. (2012) derived the pure efficiency from the location-scale model as: () (∣)() () =− ε zβxyz μz σz , . (2.5) The pure efficiency in equation (2.5)providesameasureof inefficiency whitened from the main effect of the environmental factors. This article uses the pure efficiency to measure the impacts of business model and time in the semiconductor industry. 3 Data and Variable Specification The data are collected from the Sub-Industry of Semiconductors in the Compustat database. In order to provide a global perspective for the semiconductor value chain, we combined data from both the Compustat North America database and the Compustat Global database to cover companies in the industry worldwide. As the semiconductor industry is famous for being a cyclical industry (e.g., see Rastogi et al., 2011; Tan & Mathews, 2010), we gather 20 years of data in 1999–2018 to cover a sufficient period with multiple business cycles in the industry. We exclude liquid crystal display manufacturers, light-emitting diode manufacturers, and photovoltaic producers from the dataset, limiting the sample to only IC manufacturers in a narrow sense. Hence, the panel data include 5,136 observations from 470 unique companies in the global semiconductor industry in 1999–2018. The reason for the data to begin in 1999 is twofold. First, the global semiconductor value chain has been preliminarily established in the late 1990s since the inception of the fabless–foundry business model in the late 1980s. Since 1999, there are plenty of available annual reports for the fabless and foundry firms on the open market. Second, the year 1999 is a suitable starting point to observe the development trend in the global semiconductor industry. Two years after the 1997 Asian financial crisis, the semiconductor industry is in a golden decade without massive exogenous shocks until the 2008 financial crisis. Identifying the inputs and outputs of the production function has always been a subject of controversy, either in parametric or in nonparametric frontier estimations, without exception in the semiconductor industry. Hence, we sort the most commonly used variables in 37 empirical studies, which apply the DEA approach in the semiconductor industry. Besides a few variables chosen for specific topics, the commonly used variables in these articles are highly concentrated into two input and two output categories. The first input category measures variable inputs, including labor, raw material, R&D, sales, and marketing expenditure, while the second input category measures fixed assets. Therefore, we specify p =5 inputs (labor, measured by the number of employees [ X 1 ]; COGS [ X 2 ]; R&D expenditure [ X 3]; sales and marketing expenditure [ X 4]; and fixed assets, measured by property, plant, and equipment [PP&E] [ X f ]). Note that we distinguish the notation of  20 Appendix B introduces a fast and efficient computation of the directional distance measure. Operating Efficiency in the Capital-Intensive Semiconductor Industry 7 the fixed input X f from the other variable inputs X 1 , X 2 , X 3, and X 4. Comparably, the first output category measures revenue and the second output category measures the market value of the firms. Hence, we specify q =2outputs(total revenue [ ]Y1 ;andshareholders’equity, measured by common ordinary equity [CEQ] [ ]Y 2 ). For the output variable Y 2 ,weuse shareholders’equity instead of the market value of a firm, because the variable of market value is suffering from missing data in the Compustat database, and the variable shareholders’equity is also a widely used proxy for the value of a firm. The same dataset had been used in Qiao and Wang (2021), but in this approach, we add the variable X f to emphasize the impact of CAPEX, and measure it as a fixed input by the directional distance estimator to achieve more robust results. Table 1 gives the summary statistics for the variables in 1999–2018 pooled data. In order to provide a uniform standard across years, all the variables except X 1 are expressed in US $ millions, and their values have been adjusted to 2018 US dollar by GDP deflator. The distribution of all the variables is heavily skewed to the right, owning to the domination of several semiconductor giants in the market. Besides inputs and outputs, we specify r =2 environmental variables (business model [ Z1 ]; and time, measured by the years 1999–2018 [ Z2 ]). The business model Z1 is a discrete variable, which categorizes the business models of fabless, IDM, foundry, and A&T into three groups. The first group contains the fabless, which are labor-intensive for IC design. The second group contains foundries and OSATs, that are capital-intensive for fabrication. The third group contains IDMs that are both labor-intensive and capitalintensive. Alternatively, Z2 can either be a continuous variable or a discrete one. If Z2 is treated as a continuous variable, choosing the optimal time windown for Z2 is critical, which will be discussed further in the next section. Table 2 breaks down the 5,136 observations by the business model. It is no surprise that over half of the companies are fabless. As the barriers to entry, which rely heavily on CAPEX, are much lower for fabless than for the others, fabless companies spring up like the mushrooms in the late 1990s to the early 2000s. At the same time, the number of firms operating in other kinds of business models remains relatively stable. After the golden decade of fast growth in the semiconductor industry come to an end in the mid-2000s (e.g., see Flamm, 2017), the proportions of firms in each business model are gradually fixed. Around 60% of the firms are fabless, while 20% of the firms are IDMs and the rest 20% are either front-end wafer fabs or back-end OSATs. 4 Empirical Results Most nonparametric estimators suffer from the curse of dimensionality. Based on the three diagnostics introduced in Appendix A, the necessity for dimension reduction is unambiguous. With seven dimensions ( = p5 and = q 2 )in the original data, the effective parametric sample size mfor annual data is small, no matter using FDH or DEA estimators. We calculate the values of the largest eigenvalue of the moment matrices of ′XX and ′ Y Yto the corresponding sum of eigenvalues to be = R 91.19% xand = R 98.31% y,indicating high correlations among the inputs and among the outputs. Therefore, dimension reduction can reduce estimation error. Aslightdifference in processing PCA for the directional Table 1: Summary statistics for 1999–2018 pooled data Variable Min Q1 Median Mean Q3 Max X1 0.001 0.160 0.486 3.082 2.011 107.600 X 20.001 24.170 88.008 475.252 301.645 18226.000 X 3 0.000 4.302 18.330 160.217 67.001 13543.000 X 40.549 5.885 20.087 125.406 67.185 1982.015 X f0.005 6.065 27.787 554.060 174.405 48976.000 Y 1 0.003 47.283 161.799 1064.110 563.655 70848.000 Y 2 0.175 44.279 151.749 1114.748 487.730 74563.000 Obs. 5,136 Uniq. Obs. 470 Note. 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Performance evaluation and prediction of the integrated circuit industry in China: A hybrid method. Socio-Economic Planning Sciences,69, 100712. Operating Efficiency in the Capital-Intensive Semiconductor Industry 15 Appendix A Principal Component Analysis PCA is a mapping ⟼ ++++ RR Ψ : pq 1 1 . In matrix notation, × pn matrix X and × qn matrix Y are transformed to × n1 matrices ′ X Λx1and ′YΛy1by pre-multiplying the first eigenvector Λ x 1 and Λ y 1 of the moment matrices ′XX and ′ Y Y, respectively. Unfortunately, there is no theorem that precisely identifies situations where dimension reduction should be used. Wilson (2018) provides three diagnostics for empirical research. The first diagnostic is to compute the effective parametric sample size m,incaseof n observations in a nonparametric estimation. Setting =mn κ 1 2, and thus, ≈⌊ ⌉mn κ2, where the convergence rate = + κ pq 1for FDH estimator and = ++ κ pq 21for DEA estimator, and ⌊⌉adenotes the integer nearest a . Hence, the criterion of judging the minimum sample size min parametric estimation can be used as reference in judging the minimum sample size n in nonparametric estimation. Figure A1: Optimal time window of Z2 by LSCV. 16 Guangshun Qiao and Yulin Lu A second diagnostic is to consider the proportion of n observations that yield efficiency scores equal to one. Since the, FDH estimator converges slower than the DEA estimator, a robust diagnostic for the curse of dimensionality should use the FDH efficiency estimator. If more than 25–50% of the observations yield efficiency scores equal to one, the estimation results are not convincing. A third diagnostic is to determine the ratios R xand R y of the largest eigenvalue of the moment matrices ′XX and ′ Y Yto the corresponding sum of eigenvalues for ′XX and ′ Y Y. The ratios of R xand R yprovide measures of how close the corresponding moment matrices are to rank-one. For example, if R x=0.9, then the matrix with dimension reduction ′ X Λx1contains 90% of the independent linear information in the original matrix X . In practice, Wilson (2018) proposed standardizing the matrices X and Y before PCA to ensure that the inputs or outputs have the same scale, in case of excessive number of inputs or outputs. B Computation of the Directional Distance Measure This study follows the Daraio et al. (2020) approach to compute the directional distance measure using the FDH estimator. First, use the Hadamard component-wise division of vectors ⊘ to do a monotonic transformation of the data as: =⊘ =⊘ X Xd YYd *and * . xy Then, the directional distance estimator in equation (2.1) can be expressed explicitly as: (∣ ) { ∣ ( ∣) } [{ }] {∣ } => − +> =−− ∣ ≤ βxyd d β H x βy βx xXYy ,, sup 0 *,* 0, max min **,**, xy nXYX f iX x ii ,**f fi f, (A1) where n is the sample size, {}∈in1,2, …, , and X f is the fixed input. Similarly, the conditional directional distance estimator in equation (2.4) can be expressed as: (∣ ) [{ }] {∣ ∣ ∣ } = −− ≤−≤ β xyd d z x XY y ,,, max min * *,**, xy iX x Z z h ii , fi f i,(A2) where Z denotes a vector of environmental variables. C Kernel Method A nonparametric estimator of ( ) ⋅ ∣ H XYZ,in equation (2.3) can be obtained by standard kernel smoothing, i.e.,  (∣) () = ∑≤≥ ⎛ ⎝⎞ ⎠ ∑⎛ ⎝⎞ ⎠ ∣ − − H xyz XxYyK K I ,, , XYZ i nii Zz h i nZz h , i i where ()⋅ K is a kernel function and h is a vector of bandwidths ( ) = h hh,…, r1.Bădin et al. (2010, 2012), Hall et al. (2004), Jeong et al. (2010), and Li et al. (2013) had discussed extensively how to choose the optimal bandwidth h by least-square cross-validation (LSCV). In this study, the optimal bandwidth h of the time Z2 is calculated by minimizing () ()     ()() ()     ∑∑⎡ ⎣ ⎢≤≤≥− ⎤ ⎦ ⎥ − =≠ ∑≤≤≥ ∑ ≠ −≠ xxx xyy nn I,, 1, i nji ni j fi fj ij xxx xyyKzz Kzz I 1,, ,, , , 2 nki nkj fk fj kj hik nki nhik 1,, 11 where () ( ) = K tK hht h 1. The patterns in Figure A1 represent the optimal time window by the business model using LSCV. Operating Efficiency in the Capital-Intensive Semiconductor Industry 17