Attention-based SNN on Low-Power FPGAs

Copyright © 2025 1 European Conference on EDGE AI Technologies and Applications - EEAI 20-22 October 2025, Naples, Italy The intersection of imagination and execution, where edge AI learns to create, reason, and act. Copyright © 2025 European Conference on EDGE AI Technologies and Applications - EEAI Milan, Ita20-22 October 2025 Naples, Italy 2 Copyright © 2025 Gianluca Leone, Paola Busia, Mauro Orrù, Paolo Meloni Università degli Studi di Cagliari Attention-based SNN on Low-Power FPGAs Copyright © 2025 Presentation Outline •Introduction •Research Goal •Target Use Case •Hardware Implementation •Comparison to the State of the Art •Conclusions and Future Research 3 Copyright © 2025 Introduction Spiking Neural Networks for Near-Sensor Signal Processing ▪Leverage event-based processing ▪Sparse computations ▪Binary representation: computations based on additions ▪Energy efficiency Deep-edge Performant processors and microcontrollers, CPUs, GPUs, TPUs, ASICs Micro-edge Embedded low-power microcontrollers, smart sensors Meta-edge CPUs, GPUs, FPGAs sensors actuators cloud 𝑖 𝑡 = ∑𝑤𝑖∙ 𝑠𝑖 𝑣 𝑡 = 𝛼𝑣 𝑡 − 1 + 1 − 𝛼 𝑖 𝑡 𝑠 𝑡 = 𝑣 𝑡 > 𝜃 𝑣 𝑡 = 𝑣(𝑡)(1 − 𝑠 𝑡 ) Copyright © 2025 Research Goal Attention-based Spiking Neural Networks ▪Leverage event-based processing ▪Reduce the accuracy gap with ANN alternatives Z. Zhou, Y. Zhu, C. He, Y. Wang, S. Yan, Y. Tian, and L. Yuan,“Spikformer: When spiking neural network meets transformer” Spiking Self-Attention (SSA) 𝐴𝑡𝑡𝑒𝑛𝑡𝑖𝑜𝑛(𝑄, 𝐾, 𝑉) = 𝑄 ∙ 𝐾𝑇 𝑠𝑐𝑎𝑙𝑒 ∙ 𝑉 Copyright © 2025 Research Goal Attention-based Spiking Neural Networks ▪Control modules near data-crunching logic ▪Flexibility to implement custom encoding and signal processing ▪Affordable cost ▪Leverage event-based processing ▪Reduce the accuracy gap with ANN alternatives ▪Z. Zhou, Y. Zhu, C. He, Y. Wang, S. Yan, Y. Tian, and L. Yuan,“Spikformer: When spiking neural network meets transformer” ▪Validate the advantages of attention integration in biological signal processing at the wearable scale ▪Support for ultra-low-power inference on low-end FPGAs: ESTU design Copyright © 2025 Target Use Case sEMG hand gesture classification 7 Thalmic Myo Armbands DELTA ENCODING Encoded input Input SPIKING CLASSIFIER Output Rate Rest + 12 gestures Embedding Encoder Classifier Layer Dense Dense DenseQ DenseK DenseV MatMulQK MatMulV Dense Dense Dense Dense Size 32x64 64x64 64x64 64x64 64x64 4x16x1 4x16x200 4x200x1 4x16x200 64x64 64x128 128x64 64x13 Parameters 2112 4160 4160 4160 4160 - - 4160 8320 8256 845 Layer Dense Dense Dense Dense Size 32x64 64x128 128x64 64x13 Parameters 2112 8320 8256 845 Vanilla SNN [1] [1] M. A. Scrugli, G. Leone, P. Busia, L. Raffo and P. Meloni, "Real-Time sEMG Processing with Spiking Neural Networks on a Low-Power 5K-LUT FPGA," in IEEE Transactions on Biomedical Circuits and Systems, doi: 10.1109/TBCAS.2024.3456552 Attention-based SNN Dataset: NinaPro DB5 S. Pizzolato et al “Comparison of six electromyography acquisition setups on hand movement classification tasks,” PloS one, vol. 12, no. 10, p.e0186132, 2017 S=200 time steps K, V Attention Mem H=4 Attention Heads Copyright © 2025 Target Use Case sEMG hand gesture classification 8 ▪Classification accuracy: 87.21% vs 84.77% of the Vanilla SNN ▪Small drop to 86.97% after uniform-scale quantization to 8 bit for network weights ▪20 bit fixed-point representation for neuron membrane potentials Copyright © 2025 Hardware Implementation Attention acceleration on FPGA: ESTU 9 SERV RV-core I/D MEM Encoding Slot Decoding Slot Timer SPI ESTU SoC on iCE40UP5K UART Oscillators Stack Control I-Mem Spike mems Integer mems 1 ESTU LIF module (bypass) Configurable interconnect x + LUT & FF BRAM SPRAM DSP Clock 4301 (81%) 30 (100%) 2 (50%) 6 (75%) 21 MHz Resource Requirements Lattice iCE40UP5k ▪Configurable encoding/decoding slot ▪RISC-V soft-core for input/output data flow and power management ▪Micro-code configurable acceleratore core (ESTU) ▪2 8-bit multipliers (Dense-int) ▪32 and-gates (spike-spike, spike-int mul) ▪Addition module with 2 16-bit adders, a 2-input 20-bit accumulator, a 16-bit popcounter ▪Leaky Integrate and Fire module G. Leone, P. Busia, M. Orrù, L. Raffo and P. Meloni, "ESTU: Enabling Spiking Transformers on Ultra-Low-Power FPGAs," in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2025.3626209. Copyright © 2025 [email protected] For your attention Copyright © 2025 Thank You Copyright © 2025 Event Organisers 17 SMARTY - Scalable and Quantum Resilient Heterogeneous Edge Computing enabling Trustworthy, focuses on cloud-edge continuum for heterogeneous systems, that protects data-in-transit and data-in-process, employing novel accelerators for quantum resilient communications, confidential computing, and software defined perimeters. https://www.smarty-project.eu/ EdgeAI (Edge AI Technologies for Optimised Performance Embedded Processing) develops new electronic components and systems, processing architectures, connectivity, software, algorithms, and middleware through the combination of microelectronics, edge AI, embedded systems, and edge computing. www.edge-ai-tech.eu EdgeAI NEUROKIT2E SMARTY dAIEDGE dAIEDGE is the European Network of Excellence for distributed, trustworthy, efficient, and scalable AI at the Edge and promotes the application, development, and deployment of Artificial Intelligence (AI) on edge computing platforms. https://daiedge.eu/ NEUROKIT2E (Open source deep learning platform dedicated to Embedded hardware and Europe) proposes a Deep Learning Platform for Embedded Hardware around an established European value chain (AI HW/SW). The solutions developed support neural network design, optimisation, and implementation on constrained HW. https://www.neurokit2e.eu/ NEUROKIT2E Copyright © 2025 Event Organisers 18 REBECCA (Reconfigurable Heterogeneous Highly Parallel Processing Platform for safe and secure AI) aims to democratize the development of edge AI systems and create a complete hardware and software stack centered around a RISC-V CPU, which offer higher performance, energy efficiency, safety, and security than existing systems. www.rebecca-chip.eu TRISTAN aims to expand, mature, and industrialize the European RISC-V ecosystem to compete with commercial options by leveraging the Open-Source community to gain productivity and quality. A European strategy for RISC-V designs will be defined, creating a repository of industrial rate building blocks for SoC designs in various application domains. www.tristan-project.eu CLEVER (Collaborative edge-cLoud continuum and Embedded AI for a Visionary industry of thE futuRe) proposes innovations in hardware accelerators, design stack, and middleware software that revolutionize the ability of edge computing platforms to operate federated, leveraging sparse resources that are coordinated to create a powerful swarm of resources. www.cleverproject.eu SMARTEDGE TRISTAN CLEVER REBECCA The SmartEdge project aims to achieve dynamic integration of decentralized edge intelligence while prioritizing reliability, security, privacy, and scalability. The SmartEdge solution includes a low-code tool programming environment with three main tools: Continuous Semantic Integration, Dynamic Swarm Network, and Low-code Toolchain for Edge Intelligence. https://www.smart-edge.eu/ Copyright © 2025 Event Organisers 19 The objectives of LoLiPoP IoT (Long Life Power Platforms for Internet of Things) are to develop energy harvesting-based innovative Long Life Power Platforms that enable retrofit of wireless sensor network edge devices for asset tracking, condition and performance monitoring. www.lolipop-iot.eu LoLiPoP IoT EdgeAI-Trust AIMS5.0 SC4EU SC4EU is a unique Chips JU "Innovation Action" project to take the supply chain management of semiconductor production in Europe to a new level. A true demand platform, along with its ontology as a formal description of all information within the chain, facilitates close interaction and smooth, transparent collaboration, making even highly complex supply chains resilient, flexible, and agile. https://sc4.eu/ EdgeAI-Trust addresses an advanced, trustworthy edge AI ecosystem through cuttingedge hardware, software, and tools. The project aims to enhance decentralized EdgeAI operations that are secure, reliable, and sustainable. By integrating AI-based algorithms, devices, and APIs, EdgeAI-Trust fosters interoperability and secure data exchange across diverse platforms. from sensor-actuated devices to cloud systems, all within a dynamic zero trust environment. https://www.edgeai-trust.eu/ AIMS5.0 aims to boost the economy by adopting, extending, and implementing AIenabled HW and SW components and systems across the entire industrial value chain. New technologies from IoT and based on Semantic Web ontologies, ML and AI help European manufacturers to shift from Industry 4.0 to Industry 5.0, creating humancentric workplace conditions and a climate-friendly production. https://aims50.eu/ Copyright © 2025 Supporting Organizations 20 The European Technology Platform on Smart Systems Integration is an industrydriven policy initiative, defining research, development and innovation needs as well as policy requirements related to Smart Systems Integration and integrated Microand Nanosystems. The main objective is to develop a vision and to set up a Strategic Research Agenda. www.smart-systems-integration.org Inside Industry Association is the European Technology Platform for research, design and innovation on Intelligent Digital Systems and their applications. The Association is a membership organisation for the European research and innovation actors with more than 200 members and associates from all over Europe. www.inside-association.eu Chips Joint Undertaking supports research, development, innovation, and future manufacturing capacities in the European semiconductor ecosystem. Launched as part of the Chips for Europe Initiative, it confronts semiconductor shortages and strengthens Europe's digital autonomy, engaging a significant EU, national/regional and private industry funding of nearly €11 billion. https://portal.chips-ju.europa.eu/ EU AENEAS EPoSS INSIDE Chips JU AENEAS standing for Association for European NanoElectronics ActivitieS, is an industrial Association, established in 2006, providing unparalleled networking opportunities, policy influence & supported access to funding to all types RD&I participants in the field of micro and nanoelectronics enabled components and systems. https://aeneas-office.org/