SYNtzulA: Open-Source Hardware for Energy-Efficient Spiking Neural Network Inference

Martis, Luca; Leone, Gianluca; Raffo, Luigi; MELONI, PAOLO

doi:10.5281/zenodo.17974727

SYNtzulA: Open-Source Hardware for Energy-Efficient Spiking Neural Network Inference

Martis, Luca; Leone, Gianluca; Raffo, Luigi; MELONI, PAOLO

Publisher: Zenodo
DOI: 10.5281/zenodo.17974727
Repository: zenodo.org
Language: en

Abstract

Spiking Neural Networks (SNNs) represent a promising class of neural networks that emulate the behavior of biological neurons,offering significant advantages in terms of energy efficiency and computational power. These networks achieve optimal performance on neuromorphic processors, however, such hardware remains constrained by prohibitive costs and limited accessibility. To address this gap, open source Process Design Kits (PDKs) and ElectronicDesign Automation (EDA) tools can be used to facilitate broader access to hardware development. In this work, we present SYNtzulA (SYNtzulu on ASIC), a system-on-chip that integrates a RISC-V softcore with a dedicated accelerator for SNNs. The chip layout was developed using the open-source IHP-SG13G2 PDK and the OpenROAD flow, reducing development costs and promoting wider accessibility to neuromorphic hardware solutions. SYNtzulA occupies an area of approximately 5.2 mm2 and operates at a maximum frequency of 125 MHz. The system is capable of processing 109 synapses per second at its maximum frequency, while maintaining a power consumption during inference that scales linearly with the operating frequency, dissipating approximately 632 𝜇W/MHz.

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Copyright © 2023 European Conference on EDGE AI Technologies and Applications - EEAI Milan, Ita17-19 October 2023 Athens, Greece 1 Copyright © 2023 SYNtzulA: Open-Source Hardware for Energy-Efficient Spiking Neural Network Inference Martis Luca, Gianluca Leone, Luigi Raffo, Paolo Meloni University of Cagliari, Italy Copyright © 2023 AI at the edge 2 AI Based Output Sensor AI algorithm Input Target Platform MCUs Low Power FPGAs Edge AI accelerators Main challenges in implementing AI algorithms at the edge: •Limited computational capabilities •Strict energy consumption limitations Copyright © 2023 Spiking Neural Network 3 𝑈[𝑡]=෍𝑤𝑠 𝑡 +𝛽𝑈𝑡−1 −𝑆𝑜𝑢𝑡 𝑡−1𝜃 𝑆𝑜𝑢𝑡 =ቊ1, 𝑖𝑓𝑈𝑡 >𝜃 0, 𝑖𝑓𝑈𝑡 < 𝜃 𝜃 𝑈[𝑡] 𝑡 𝑆𝑜𝑢𝑡[𝑡] •Event-based version of NNs • Inputs: Spikes (0 or 1) •addition operations, instead of multiply and accumulate operations •Building blocks: LIF neurons •Have a memory: U[t] •Elaborate Spikes 𝑡0𝑡1 𝑡1 𝑡0𝑡1 𝑡1 Copyright © 2023 SoA SNN Hardware accelerator 4 High development costs.High energy efficiency Restricted accessibility. En/SOP Power [1] Antonio Vitale et al. “Neuromorphic Edge Computing for Biomedical Applications: Gesture Classification Using EMG Signals”. In: IEEE Sensors Journal 22.20 (2022), pp. 19490–19499. doi: 10.1109/JSEN.2022.3194678. [2] F. Akopyan, J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur,P. Merolla, N. Imam, Y. Nakamura, P. Datta, G.-J. Nam, B. Taba,M. Beakes, B. Brezzo, J. B. Kuang, R. Manohar, W. P. Risk, B. Jackson,and D. S. Modha, “Truenorth: Design and tool flow of a 65 mw 1million neuron programmable neurosynaptic chip,” IEEE Transactionson ComputerAided Design of Integrated Circuits and Systems, vol. 34,no. 10, pp. 1537–1557, 2015. [3] Zhijie Yang, Lei Wang, Yao Wang, Linghui Peng, Xiaofan Chen, Xun Xiao, Yaohua Wang, and Weixia Xu. 2022. Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons. In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC '22). Association for Computing Machinery, New York, NY, USA, 943–948. https://doi.org/10.1145/3489517.3530563 [4] S. B. Furber, F. Galluppi, S. Temple and L. A. Plana, "The SpiNNaker Project," in Proceedings of the IEEE, vol. 102, no. 5, pp. 652-665, May 2014, doi: 10.1109/JPROC.2014.2304638. [5] A. Di Mauro, A. S. Prasad, Z. Huang, M. Spallanzani, F. Conti and L. Benini, "SNE: an Energy-Proportional Digital Accelerator for Sparse Event-Based Convolutions," 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2022, pp. 825-830, doi: 10.23919/DATE54114.2022.9774552. [1] 41 mW /24 pJ [2] 65mW/27 pJ [3] 85 W / 2.35 pJ [4] 0,74 W /8 pJ [5] 11 mW/0,22 pJ Copyright © 2023 Democratize Neuromorphic Hardware Our approach 5 Encoding Decoding Lightweight SNN Input Output Low Power FPGAs Open-Source ASICs Low-cost approach High quiescent power consumption Compromise between the accessibility of FPGAs and the high costs associated with proprietary EDA tools and PDKs for chip development Reliance on legacy technology nodes Target Platform Copyright © 2023 Open-Source PDKs + EDA 6 Open Source EDA tools Tool Name Application Yosys Synthesis OpenROAD Floorplan/Place/Route Klayout GDSII Generation PDK name Tecnology SKY130 130 nm GF180MCU 180 nm IHP SG13G2 130 nm Open Source PDKs Copyright © 2023 RTL-GDSII flow 7 Copyright © 2023 From SYNtzulu to SYNtzulA 8 SYNtzulA is inspired by our previously published open-source architecture SYNtzulu [6], which was deployed on a low-power FPGA. We made some modifications to adapt it from the FPGA implementation to the new PDK: •the encoding scheme is fixed •BRAM/SPRAM blocks were replaced with flip-flops and SRAM macros available on the PDK •clock gating through dedicated cell [6] Gianluca Leone, Matteo Antonio Scrugli, Lorenzo Badas, Luca Martis, Luigi Raffo, and Paolo Meloni. 2024. Syntzulu: a tiny risc-v-controlled snn processorfor real-time sensor data analysis on low-power fpgas. IEEE Transactions on Circuits and Systems I: Regular Papers, 1–12. doi:10.1109/TCSI.2024.3450966. Copyright © 2023 RISC-V Softcore: SERV 9 SERV in our architecture is used for: ▪I/O management: ▪Receiving of weights and input samples via SPI ▪Sending inferences via UART ▪Power management ▪System clock gating