CMOS MAPS upgrade for the Belle II Vertex Detector

HAL Id: hal-03931052 https://hal.science/hal-03931052v1 Submitted on 4 Apr 2023 HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. CMOS MAPS upgrade for the Belle II Vertex Detector M. Babeluk, M. Barbero, J. Baudot, T. Bergauer, F. Bernlochner, S. Bettarini, F. Bosi, Y. Buch, G. Casarosa, J. Dingfelder, et al. To cite this version: M. Babeluk, M. Barbero, J. Baudot, T. Bergauer, F. Bernlochner, et al.. CMOS MAPS upgrade for the Belle II Vertex Detector. 15th Pisa Meeting on Advanced Detectors, May 2022, La Biodola, Italy. pp.168015, �10.1016/j.nima.2023.168015�. �hal-03931052� CMOS MAPS upgrade for the Belle II Vertex Detector M. Babeluka, M. Barberob, J. Baudotc, T. Bergauera, F. Bernlochnerd, S. Bettarinie,f, F. Bosie,f, Y. Buchg, G. Casarosae,f, J. Dingfelderd, T. Fillingerc, C. Finckc, A. Freyg, C. Huc, C. Irmlera, C. Marinash, M. Massae,f, L. Massaccesie,f, M. Minutie,f, H. Phamc, G. Rizzoe,f, C. Schwandaa, B. Schwenkerg, M. Schwickardig, C. Wesseld,∗, on behalf of the Belle II VTX collaboration aInstitute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna, Austria bAix Marseille Universit´e, CNRS/IN2P3, CPPM, Marseille, France cUniversit´e de Strasbourg, CNRS, IPHC, UMR 7178, Strassbourg, France dUniversity of Bonn, Bonn, Germany eINFN Sezione di Pisa, Pisa, Italy fDipartimento di Fisica, Universi`a di Pisa, Pisa, Italy gII. Physikalisches Institut, Georg-August-Universitaet Goettingen, Goettingen, Germany hIFIC - Instituto de F´ısica Corpuscular (CSIC/University of Valencia), Valencia, Spain Abstract The success of the Belle II experiment in Japan relies on the very high instantaneous luminosity, close to 6 ×1035cm−2s−1, expected from the SuperKEKB collider. The corresponding beam conditions at such luminosity levels generate large rates of background particles and creates stringent constraints on the vertex detector, adding to the physics requirements. Current prospects for the occupancy rates in the present vertex detector (VXD) at full luminosity fall close to the acceptable limits and bear large uncertainties. In this context, the Belle II collaboration is considering the possibility to install an upgraded VXD system around 2027 to provide a sufficient safety margin with respect to the expected background rate and possibly enhance tracking and vertexing performance. The VTX collaboration has started the design of a fully pixelated VXD, called VTX, based on fast and highly granular Depleted Monolithic Active Pixel Sensors (DMAPS) integrated on light support structures. The two main technical features of the VTX proposal are the usage of a single sensor type over all the layers of the system and the overall material budget below 2 % of radiation length, compared to the current VXD which has two different sensor technologies and about 3 % of radiation length. A dedicated sensor (OBELIX), taylored to the specific needs of Belle II, is under development, evolving from the existing TJ-Monopix2 sensor. The time-stamping precision below 100 ns will allow all VTX layers to take part in the track finding strategy contrary to the current situation. The first two detection layers are designed according to a self-supported all-silicon ladder concept, where 4 contiguous sensors are diced out of a wafer, thinned and interconnected with post-processed redistribution layers. The outermost detection layers follow a more conventional approach with a cold plate and carbon fibre support structure, and light flex cables interconnecting the sensors. This document will review the context, technical details and development status of the proposed Belle II VTX. Keywords: Belle II, VXD, SVD, PXD, VTX, Upgrade, CMOS, DMAPS 1. Introduction1 The Belle II experiment [1] located at KEK in Tsukuba,2 Japan, is an all-purpose full solid angle particle detector. It3 records data from collisions at the interaction point of the asym-4 metric e+e−SuperKEKB collider [2], which operates at a centre5 of mass energy of √s=10.58 GeV, corresponding to the mass6 of the Υ(4S) resonance, which decays into two Bmesons in7 nearly 100 % of all cases. To fulfill the physics requirements of8 Belle II the vertex detector (VXD) is an essential part of the sys-9 tem. However, the SuperKEKB team is working on improve-10 ments to the final focusing magnets and the interaction region11 to be able to achieve the target luminosity. Because of this, it12 might be necessary to change the position or the shape of the13 ∗Corresponding author Email address: [email protected] (C. Wessel) final focusing magnets, or both, potentially resulting in a re-14 design of the interaction region. In case of substantial changes15 of the interaction region, the VXD likely cannot be kept and16 a new detector will be necessary, independent of the hit rates17 and radiation environment. To ensure safe operation of the ex-18 periment while guaranteeing high tracking and vertexing per-19 formance towards the high luminosity of 6 ×1035cm−2s−1, the20 VTX collaboration is developing a new fully pixelated CMOS21 detector to replace the VXD in the timescale of 2027 [3]. This22 new detector is one of four proposals for the (partial) replace-23 ment of the VXD; the other three proposals are a new DEPFET24 pixel detector as replacement for the current DEPFET based25 PXD, a refined strip detector with smaller strip pitch in zdi-26 rection and a reduced sensor thickness as replacement for the27 current strip detector, and a silicon on insulator pixel detector28 to cover the full VXD volume similar to the VTX.29 The remaining part of this document first introduces the con-30 Preprint submitted to Nuclear Inst. and Methods in Physics Research, A December 16, 2022 27 cm 75 cm Figure 1: A CAD rendering of the VTX layout. The baseline concept contains 5 straight barrel layers filling the current VXD volume. cept of the VTX and the underlying technology in Section 2,31 followed by a conclusion and outlook to further developments32 in Section 3.33 2. Concept of the VTX34 In its innermost part, the Belle II experiment is currently35 equipped with two layers of DEPFET [4] pixels (PXD) at radii36 of 1.4 and 2.2 cm, and four layers of double sided silicon strip37 sensors (SVD) [5] at radii between 3.9 and 13.5 cm, which to-38 gether form the VXD, which corresponds to the configuration39 defined in the technical design report for Belle II. Its main task40 is the precise estimation of decay vertices in addition to very41 low momentum track finding. The VXD is surrounded by the42 central drift chamber (CDC) as the main tracking device, rang-43 ing from 16 cm to 112 cm in radius. The PXD is also needed44 to be able to resolve the vertices of decaying Bmesons to en-45 able measurements of oscillation of neutral Bmesons, which46 requires the resolution of the impact parameters d0and z0to be47 in the order of 10 µm. As the difference in flight length between48 both particles is only about 150 µm due to a boost of βγ =0.2849 caused by the asymmetric beam energies of 7 GeV (4 GeV) of50 the electrons (positrons), a highly granular vertex detector is51 mandatory.52 To achieve the target instantaneous luminosity, the nano53 beam scheme [6] is used. While the vertical beam size al-54 ready is reduced significantly to previous accelerators and ex-55 periments, further reduction is foreseen for the next years to56 shrink the beam size in the interaction point to tens of nm in the57 vertical direction. This requires strong focusing of the beams,58 resulting in large amounts of beam induced backgrounds, which59 especially affects the VXD as the innermost detector.60 The goal of the VTX is to develop a fully pixelated detector61 based on Depleted Monolithic Active Pixel Sensors (DMAPS)62 using industry standard CMOS processes, which is foreseen63 to replace the full VXD after 2027. The currently proposed64 Figure 2: Design schematic for the OBELIX chip. concept includes five layers using sensors based on the Tower-65 Jazz 180 nm process, as depicted in Figure 1. The figure shows66 the central beam pipe surrounded by the two innermost layers67 (called iVTX) in the centre at radii of 1.4 and 2.2 cm, which are68 followed by the three outer layers (called oVTX) at radii of 3.9,69 9, and 14 cm. The radii and the number of layers are not yet70 final but need further studies for optimisation. Low material71 budget is essential, as the particles in Belle II are very soft, thus72 multiple Coulomb scattering needs to be minimised. Consid-73 ering the high background level expected in the VTX, with hit74 rates up to 120 MHz/cm2in the innermost layer, correspond-75 ing to TID of 10 Mrad/year and NIEL of 5 ×1013neq/cm2/year,76 the expected power consumption of the fast DMAPS chip under77 development will be about 200 mW/cm2.78 In the VTX design we plan to have a material budget of 0.1 %79 X0for the two innermost layers, about 0.3 % X0for the two fol-80 lowing layers and about 0.8 % X0in the outermost layer. In or-81 der to achieve the very low material budget, the two innermost82 layers are designed to be self-supported air cooled all-silicon83 ladders, while the three outer layers are water cooled and on a84 carbon fibre structure for support, which is also visible in Fig-85 ure 1.86 The sensor size is foreseen to be 3×2 cm2, with pixel pitches87 of 30 µm to 40 µm in both directions. The sensor under de-88 velopment, called OBELIX, is derived from the existing TJ-89 Monopix2 chip [7, 8]. Several different front end flavours exist,90 and the final decision on one flavour has not yet been made.91 Timestamp clock signals of down to 25 ns can be used to be92 able to cope with the target hit rate of 120 MHz/cm2.93 Compared to the TJ-Monopix2, which features a triggerless94 architecture with no memory on the periphery, the digital logic95 needs to be adapted to fit the needs of Belle II. OBELIX will96 have a triggered readout architecture, with a fixed latency of97 about 5 µs, and will be operated up to 30 kHz trigger rate. With98 the foreseen short acquisition window of about 100 ns, we can99 limit the data throughput to 320 Mbps, even with the high tar-100 get hit rate expected. A schematic layout of the OBELIX chip101 is shown in Figure 2. The active area of about 3 ×1.5 cm2 102 covers the main part of the chip. In the periphery an additional103 2 Support structure ~1 mm Passive components RDL metal (Cu) Post processing bulk silicon Polymer Polymer Vias Flex cable Metal pads (Al) Mounting hole ~100 µm gap Flex cable Bond pads ~30 mm ~140 mm RDL metal (Cu) Demonstrator: Resistive heaters later: DMAPS sensors Support Structure ~1 mm ~22 mm Thinned to ~40 µm Thinned to ~400 µm 700 µm wafer Figure 3: Sketch of the all silicon ladder concept of the iVTX. Four dummy sensors with a length of about 30 mm are shown in blue on the silicon support structure (grey) with a width of about 22 mm and a length of about 140 mm. The yellowish lines indicate power and data transition lines, one line of both to each chip. Power is supplied to the ladder by a flex cable (left), which also transmits data to and from the chips in for the final chips. Figure 4: Eye openings of the iVTX data transmission lines at four different positions on the ladder. area of about 3 ×0.3 cm2is required for data (pre-)processing104 and triggering as well as LDO regulators, data transceiver, and105 monitoring circuits. A first design prototype of the new chip106 will be submitted in autumn 2022.107 2.1. First iVTX demonstrator108 Figure 3 shows a schematic drawing of the iVTX demonstra-109 tor ladder with an overall length of about 140 mm and a width110 of about 22 mm. Instead of actual sensors the ladder is equipped111 with four dummy chips with integrated surface resistors. These112 resistors are used to mimic the estimated heat load in order to113 test the cooling concept. In addition, it is also equipped with re-114 distribution layers (RDL) for power and data to connect every115 chip with the flex cable at the end of the ladder. The sensitive116 areas are thinned down to about 40 µm to test the mechanical117 integrity of the assembly and to develop the thinning process.118 The overall support is provided by the remaining thicker frame119 around the active area.120 Signal quality at the far end, power delivery, and the full as-121 sembly process are to be tested. Eye diagrams from simulation122 with a transfer rate of 640 Mbps are depicted in Figure 4, indi-123 cating that data rates of 320 Mbps will be possible.124 Figure 5: Prototype of the layer 5 truss, which is the longest truss. It is made from thin carbon fibre structures and evolved from the ALIC ITS2 space frame concept. Figure 6: First prototype of the cold plate. The figure only shows one end. One coolant tube (golden) is connected to the cold plate (black) and turns 180◦on the other end (not shown) so that the coolant flows both directions and thus leaves on the same side it starts. In total five demonstrators can be produced on a 200 mm125 wafer. First thinned multi-chip CMOS demonstrator ladders126 have been produced and characterised with different thickness127 and geometries, showing a homogeneous thickness over an area128 of 10 cm2.129 2.2. oVTX development130 The oVTX is not self-supported, as the distance required to131 cover the acceptance is too large, the mechanical integrity is132 provided by a carbon fibre support structure called truss, as de-133 picted in Figure 5. This structural design evolved from the AL-134 ICE ITS2 space frame concept [9]. With a length of 70 cm and135 a weight of only 5.8 g it is able to carry more than 40 sensors136 in two rows next to each other with a small overlap, achieving137 a very low material budget. In order to cool the sensors a cold-138 plate concept is in development, as shown in Figure 6. The139 sensors are glued to the cold-plate, which is then mounted to140 the truss. For each sensor row, a polyimide cooling tube runs141 over all sensors and turns back at the other end, such that the142 heated coolant leaves on the same side. Depending on the ther-143 mal testing, it will either be guided back to the cooling system,144 or fed into another ladder.145 An explosion drawing of a fully assembled layer 5 ladder is146 shown in Figure 7. In addition to the carbon fibre structure (bot-147 tom), two cold plates for the two neighbouring sensor rows are148 Flex circuits forward/backward 30 mm 20 mm Chips Coldplates Support structure (length = 70 cm) Polyimid cooling pipes Figure 7: Explosion drawing of a fully assembled layer 5 ladder. 3 Power supply board Flex cable prototype Probe Figure 8: Test of the oVTX transmission line signal integrity. Figure 9: Eye diagram for the oVTX transmission line signal integrity of the layer 5 flex cable. shown, as well as the flex cables for power and data transmis-149 sion (top). With the truss assembled, first thermo-mechanical150 tests were performed. These first tests demonstrated that the151 first resonance frequency is at 200 Hz, which is above the fre-152 quencies of typical earthquakes in Japan, and that the thermal153 properties are good.154 Since the transmission lines and the flex cable need to be as155 thin as possible, but also need to ensure save data transmission,156 the 70 cm long outermost ladders are equipped with two flex157 cables per ladder, one from each side of the truss. Figure 8158 shows the setup to test the signal integrity of one of the 35 cm159 long transmission lines for data transmission rate of 500 Mbps.160 The signal is injected on the left side and read out on the right161 side. The resulting eye diagram of the measurement is shown in162 Figure 9. A clear difference between high and low can be seen,163 indicating an excellent signal integrity for the 35 cm long flex,164 providing a good starting point for further developments.165 3. Conclusion and outlook166 The necessary changes to the SuperKEKB interaction region167 in the core of the Belle II detector might alter the detector168 boarder, which could make it impossible to keep the current169 VXD in place. In order to prepare for this scenario, and to170 cope with potentially high occupancies, the VTX project was171 started, aiming for a pixelated all-CMOS replacement of the172 VXD. While simulations indicate substantial improvements in173 the tracking and physics performance with a five layer CMOS174 pixel detector replacement for the VXD [10], the development175 and testing of the VTX is ongoing. Low material budget fitting176 the needs of the Belle II experiment can be achieved, as well177 as high signal integrity and sufficient cooling for the expected178 200 mW/cm2of dissipated power. As a final goal, low power179 OBELIX chip suiting the needs of Belle II is developed along-180 side the necessary infrastructure for power delivery, readout,181 and cooling. The VTX collaboration will contribute to a con-182 ceptual design report for the Belle II upgrade by early 2023 and183 continue to work on testing and developing the system, aiming184 for installation in 2027.185 4. Acknowledgment186 This work was supported by Grant CIDEGENT/2018/020 of187 Generalitat Valenciana (Spain) and has received funding from188 European Union’s Horizon 2020 program under grant agree-189 ment no. 101004761 (AIDAinnova).190 References191 [1] Belle II Collaboration, T. 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