Silicon-Proven Learning With OpenPDKs and MPW Access for IC Education
Holguin Weber, Eduardo Javier
- Publisher
- Zenodo
- Language
- en
Abstract
This presentation describes a practice-centered approach to microelectronics education in Latin America, where students progress from theoretical circuit analysis and simulation to working directly with fabricated silicon. Using open-source EDA flows (Yosys, OpenLane, Magic, KLayout) together with openly available PDKs such as SkyWater SKY130, GlobalFoundries GF180, and the IHP SG13G2 open PDK, undergraduate teams at the Universidad San Francisco de Quito (USFQ) have completed multiple end-to-end ASIC projects. These designs have been manufactured through the Tiny Tapeout multi-project wafer program as well as through collaborative initiatives including UNICCASS and the GF180 Synopsys Workforce Development program. A central focus of the talk is the complete design-to-silicon link. The chips fabricated by students are used as laboratory instruments and not only as academic milestones. Students evaluate post-silicon behavior including timing divergence, process-corner sensitivity, mismatch effects, routing artifacts, and signal integrity limitations, and compare these results with their own simulations, extracted parasitics, and signoff analyses. This provides a direct connection between theoretical learning, HDL implementation, physical design constraints, and the nonideal characteristics of real silicon, revealing aspects of IC behavior that cannot be captured through simulation alone. Open hardware ecosystems combined with MPW access have enabled a scalable and fabricationbacked educational model for IC design in Latin America. This approach allows universities to teach a complete sequence from design, to fabrication, to measurement using accessible tools and real silicon. The presentation will outline the methodology, discuss technical and instructional challenges, and describe the educational impact observed across several generations of siliconproven student projects.
Full text
Eduardo Holguín Silicon-Proven Learning With Open PDKs and MPW Access for IC Education
Summary ➢Motivation and Context ➢IC Design Flow (Concept to Silicon) ➢Capstone IC Design at USFQ ➢Conclusions
Summary ➢Motivation and Context ➢IC Design Flow (Concept to Silicon) ➢Capstone IC Design at USFQ ➢Conclusions
Motivation –Barriers in Latin America •High costs of EDA tools and fabrication. •Strict NDAs that prevent open academic use. •A limited industrial ecosystem. In Ecuador: •Early efforts in the 1990s (1.2 µm CMOS chips) were discontinued due to cost. •The first modern microchip appeared in 2022. 4 Historically, IC design in countries such as Ecuador has faced:
Rise of Open-Source EDA •Open-source EDA tools and public PDKs (e.g. SKY130,GF180mcu, SG13G2) have enabled new opportunities. •Toolchains like Yosys and OpenLane (Librelane), with MPW services such as Tiny Tapeout, support complete ASIC flows without proprietary software. •Democratization of IC design: accessible to universities, researchers, and independent developers. MPW = multiple designs on same wafer → shared cost
Essential IC Design Tools (Digital & Analog) 6 Design Task Cadence Synopsys Open -Source Tools Digital Simulation Xcelium VCS Icarus Verilog, Verilator Synthesis Genus Design Compiler Yosys Place & Route Innovus IC Compiler II OpenROAD Timing Analysis Tempus PrimeTime OpenSTA DRC / LVS Pegasus / Assura IC Validator Magic, Netgen Analog Schematic Virtuoso Custom Compiler Xschem Analog Simulation Spectre HSPICE Ngspice Analog Layout Virtuoso Custom Compiler KLayout , Magic
Open Source vs Proprietary 7 Advantages of the Open-Source Approach •Accessible from anywhere in the world •Ideal for universities, research centers, and prototyping •Enables exploration and modification of tools for specific use cases Advantages of the Industrial (Proprietary) Approach •High integration with commercial fabrication flows •Professional support and quality certification •Optimized for high-complexity and high-volume designs
Summary ➢Motivation and Context ➢IC Design Flow (Concept to Silicon) ➢Capstone IC Design at USFQ ➢Conclusions
IC Design Methodologies 9 RTL / Semi-Custom (Top-Down) •Design described in Verilog (RTL) •Logic synthesized into standard cells •Automated Place & Route •Used for large digital systems and SoCs Full-Custom Design •Transistor-level circuit and layout design •Not directly described in Verilog •Verified using SPICE and layout extraction •Used for analog, mixed-signal, and custom digital blocks Verilog (RTL) → Synthesis → P&R → GDS Transistors → Custom Layout → DRC/LVS/PEX
Digital Design: Layout & Integration ▪Place-and-route via OpenLane + Magic checks ▪Fits into 160 ×100 μm² Tiny Tapeout tile ▪1.8 V supply 16
(Example) Fabrication & Testing Platform ▪Fabricated in Tiny Tapeout 6 MPW run ▪Integrated padframe: 4 inputs, 5 outputs ▪Breakout board used for measurements ▪IOs labeled, standard 3.3 V interface 17
Measurement Results (TT06) ▪Both designs produced nearly identical results, validating the architectures. ▪Measured outputs showed linear relation between input frequency and 5-bit digital code. Other Examples: ▪Analog Comparator TT07 Index 231 ▪Sky130 Digital Playground TTsky25a Index 419 ▪Dual-Channel PWM with SPI Control + Extra Test Logic: TTsky25b Index 805
Some Examples: 19
Summary ➢Motivation and Context ➢IC Design Flow (Concept to Silicon) ➢Capstone IC Design at USFQ ➢Conclusions
Conclusions •Open-source EDA tools and public PDKs enable end-to-end IC design education with real silicon outcomes •MPW access (e.g., Tiny Tapeout) makes fabrication affordable and scalable for universities •Students gain industry-relevant skills from specs to post-layout verification •The USFQ model demonstrates that silicon-proven IC education is feasible in Latin America 21
Thanks for your attention
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